DR80390XP high performance, area optimized soft core single-chip 8-bit
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High Performance Configurable 8-bit Microcontroller 3.01
DR80390XP high performance, area optimized soft core single-chip 8-bit embedded controller dedicated operation with fast (typically on-chip) slow (off-chip) memories. core been designed with special concern about power consumption. Additionally advanced power management unit makes DR80390XP core perfect portable equipment where power consumption mandatory. DR80390XP soft core 100% binarycompatible with industry standard 80C390 8-bit microcontroller. There configurations DR80390XP: Harward where external data program buses separated, Neumann with common program external data bus. DR80390XP RISC architecture times faster compared standard architecture executes 65-200 million instructions second. This performance also exploited great advantage power applications where core clocked seven times more slowly than original implementation performance penalty. DR80390XP fully customizable, which means delivered exact configuration meet users' requirements. There need extra used features wasted silicon. includes fully automated testbench
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with complete tests allowing easy package validation each stage design flow.
FEATURES
100% software compatible with industry standard 80390
LARGE mode 8051 instruction FLAT mode 80390 instruction
RISC architecture enables execute instructions times faster compared standard 8051 times faster multiplication times faster division Data Pointers (DPTR) faster memory blocks copying
Advanced modes Auto-switch current DPTR
bytes internal (on-chip) Data Memory bytes contiguous Program Memory bytes external (off-chip) Data Memory User programmable Program Memory Wait States solution wide range memories speed
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User programmable External Data Memory Wait States solution wide range memories speed De-multiplexed Address/Data allow easy connection memory Interface additional Special Function Registers Fully synthesizable, static synchronous design with positive edge clocking internal tri-states Scan test ready virtual clock frequency 0.35u technological process
priority levels external interrupt sources interrupt sources from peripherals
Four 8-bit Ports
addressable data direction each line Read/write single line 8-bit group
Three 16-bit timer/counters
Timers clocked internal source Auto reload 8/16-bit timers Externally gated event counters
Full-duplex serial port
Synchronous mode, fixed baud rate 8-bit asynchronous mode, fixed baud rate 9-bit asynchronous mode, fixed baud rate 9-bit asynchronous mode, variable baud rate
PERIPHERALS
DoCDdebug unit
Processor execution control Halt Step into instruction Skip instruction Read-write processor contents Program Counter (PC) Program Memory Internal (direct) Data Memory Special Function Registers (SFRs) External Data Memory Hardware execution breakpoints Program Memory Internal (direct) Data Memory Special Function Registers (SFRs) External Data Memory Hardware breakpoints activated certain Program address (PC) Address write into memory Address read from memory Address write into memory required data Address read from memory required data Three wire communication interface
controller Master
7-bit 10-bit addressing modes NORMAL, FAST, HIGH speeds Multi-master systems supported Clock arbitration synchronization User defined timings lines Wide range system clock frequencies Interrupt generation
controller Slave
NORMAL speed FAST speed HIGH speed 3400 Wide range system clock frequencies User defined data setup time lines Interrupt generation
Master Slave Serial Peripheral Interface
Supports speeds system clock Mode fault error Write collision error Four transfer formats supported System errors detection Allows operation from wide range system
Power Management Unit
Power management mode Switchback feature Stop mode
clock frequencies (build-in 5-bit timer)
Interrupt generation
Extended Interrupt Controller
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Programmable Watchdog Timer
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16-bit Compare/Capture Unit
Events capturing Pulses generation Digital signals generation Gated timers Sophisticated comparator Pulse width modulation Pulse width measuring
Memory style Program Memory type Program Memory waitstates
Harward Neumann synchronous asynchronous used (0-7) unused used unused synchronous asynchronous used (0-7) unused used unused used unused used unused subroutines location
Program Memory writes Internal Data Memory type External Data Memory size External Data Memory wait-states Second Data Pointer (DPTR1)
Fixed-Point arithmetic coprocessor
Multiplication 16bit 16bit Division 32bit 16bit Division 16bit 16bit Left right shifting bits Normalization
Floating-Point arithmetic coprocessor IEEE754 standard single precision
FADD, FSUB addition, subtraction FMUL, FDIV- multiplication, division FSQRT- square root FUCOM compare FCHS change sign FABS absolute value
Data Pointers decrement Data Pointers auto-switch Interrupts Timing access protection Power Management Mode Stop mode debug unit
used unused used unused used unused used unused
Floating-Point math coprocessor IEEE-754 standard single precision real, word short integers
FADD, FSUB- addition, subtraction FMUL, FDIV- multiplication, division FSQRT- square root FUCOM- compare FCHS change sign FABS absolute value FSIN, FCOS- sine, cosine FTAN, FATAN- tangent, arcs tangent
Besides mentioned above parameters available peripherals external interrupts excluded from core changing appropriate constants package file.
DELIVERABLES
Source code: VHDL Source Code or/and VERILOG Source Code or/and Encrypted, plain text EDIF netlist VHDL VERILOG test bench environment Active-HDL automatic simulation macros ModelSim automatic simulation macros Tests with reference responses Technical documentation Installation notes
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CONFIGURATION
following parameters DR80390XP core easy adjusted requirements dedicated application technology. Configuration core prepared effortless changing appropriate constants package file. There need change parts code.
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core specification Datasheet Synthesis scripts Example application Technical support Core implementation support months maintenance
SYMBOL
reset ramdatai(7:0)
Delivery Core updates, minor major versions changes Delivery documentation updates Phone email support
sfrdatai(7:0)
prgdatai(7:0)
LICENSING
Comprehensible clearly defined licensing methods without royalty fees make using Core easy simply. Single Design license allows Core single FPGA bitstream ASIC implementation. Unlimited Designs, Year licenses allow Core unlimited number FPGA bitstreams ASIC implementations. cases number Core instantiations within design, number manufactured chips unlimited. There time restriction except Year license where time limited months. Single Design license
VHDL, Verilog source code called Source Encrypted, plain text EDIF called Netlist
xramdatai(7:0)
ramdatao(7:0) ramaddr(7:0) ramoe ramwe sfrdatao(7:0) sfraddr(7:0) sfroe sfrwe prgdatao(7:0) prgdataz prgaddr(23:0) prgrd prgwr xramdatao(7:0) xramdataz xramaddr(23:0) xramrd xramwr
int0 int1 int2 int3 int4 int5 int6 docddatai
port0i(7:0) port1i(7:0) port2i(7:0) port3i(7:0) gate0 gate1 t2ex capture0 capture1 capture2 capture3 rxd0i rxd1i mscli msdai sscli ssdai scki
docddatao docdclk stop port0o(7:0) port1o(7:0) port2o(7:0) port3o(7:0)
Year license
Encrypted Netlist only
Unlimited Designs license
Source Netlist
Upgrade from
Source Netlist Single Design Unlimited Designs
rxd0o txd0 rxd1o txd1 msclhs msclo msdao ssclo ssdao sso(7:0) scko sckz
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BLOCK DIAGRAM
reset prgdatai(7:0) prgdatao(7:0) prgdataz prgaddr(23:0) prgrd prgwr xramdatai(7:0) xramdatao(7:0) xramdataz xramaddr(23:0) xramrd xramwr ramdatai(7:0) ramdatao(7:0) ramaddr(7:0) ramoe ramwe sfrdatai(7:0) sfrdatao(7:0) sfraddr(7:0) sfroe sfrwe docddatai docddatao docdclk
Opcode Decoder
PINS DESCRIPTION
reset ramdatai[7:0]
TYPE
input input input input input input input input input input input input input input input input input input input input input input input input input input input input input input input input input input input input input input output output output output output output output output output
DESCRIPTION
Global clock Global synchronous reset Data from Internal Data Memory Data from user SFRs Input data from Program Memory Data from External Data Memory External interrupt line External interrupt line External interrupt line External interrupt line External interrupt line External interrupt line External interrupt line DoCDdata input Port input Port input Port input Port input Timer clock line Timer clock line gate control Timer clock line Timer clock line gate control Timer clock line Timer control Timer capture line Timer capture line Timer capture line Timer capture line Serial receiver input Serial receiver input Master clock line input Master data input Slave clock line input Slave data input slave select slave input master input clock input Data Internal Data Memory Internal Data Memory address Internal Data Memory output enable Internal Data Memory write enable Data user SFRs User SFRs address User SFRs output enable User SFRs write enable Program Memory address
Program Memory Interface
sfrdatai[7:0]
Control Unit
prgdatai[7:0] xramdatai[7:0]
int0 int1 int2 int3 int4 int5 int6 port0i(7:0) port1i(7:0) port2i(7:0) port3i(7:0) port0o(7:0) port1o(7:0) port2o(7:0) port3o(7:0)
int0 int1 int2 int3 int4 int5 int6 docddatai port0i[7:0] port1i[7:0] port2i[7:0] port3i[7:0] gate0 gate1
External Memory Interface
Interrupt Controller Interrupt Controller
Internal Data Memory Interface Ports User Interface
DoCDDebug Unit
Power Management Unit
stop
Floating Point Unit
Multiply Divide Unit
t2ex capture0
gate0 gate1
t2ex
capture1 capture2 capture3 rxd0i rxd1i mscli msdai sscli ssdai scki ramdatao[7:0] ramaddr[7:0] ramoe ramwe sfrdatao[7:0] sfraddr[7:0] sfroe sfrwe prgaddr[23:0]
Timer
Timers
capture0 capture1 capture2 capture3 rxd1o rxd1i txd1 msclhs mscli msclo msdai msdao sscli ssclo ssdai ssdao
Compare Capture Unit
Watchdog Timer
UART
UART
rxd0o rxd0i txd0 scko scki sckz sso(7:0)
Master Unit Unit Slave Unit
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prgdatao[7:0] prgdataz prgrd prgwr xramdatao[7:0] xramdataz xramaddr[23:0] xramrd xramwr docddatao docdclk stop port0o[7:0] port1o[7:0] port2o[7:0] port3o[7:0] rxd0o txd0 rxd1o txd1 msclo msclhs msdao msclo msdao sso[7:0] scko sckz
output output output output output output output output output output output output output output output output output output output output output output output output output output output output output output output
Output data Program Memory PRGDATA tri-state buffers control line Program Memory read Program Memory write Data External Data Memory XDATA tri-state buffers control line External Data Memory address External Data Memory read External Data Memory write DoCDdata output DoCDclock line Power management mode indicator Stop mode indicator Port output Port output Port output Port output Serial receiver output Serial transmitter line Serial receiver output Serial transmitter line Master clock output High speed Master clock line Master data output Slave clock output Slave data output slave select lines slave output master output clock output clock line tri-state buffer control
UNITS SUMMARY
Arithmetic Logic Unit performs arithmetic logic operations during execution instruction. contains accumulator (ACC), Program Status Word (PSW), registers related logic such arithmetic unit, logic unit, multiplier divider. Opcode Decoder Performs instruction opcode decoding control functions other blocks. Control Unit Performs core synchronization data flow control. This module directly connected Opcode Decoder manages execution microcontroller tasks. Program Memory Interface Contains Program Counter (PC) related logic. performs instructions code fetching. Program Memory also written. This feature allows usage small boot loader loading program into RAM, EPROM FLASH EEPROM storage UART, SPI, DoCDmodule. Program fetch cycle length programmed user. This feature called Program Memory Wait States, allows core work with different speed program memories. External Memory Interface Contains memory access related registers such Data Pointer High (DPH0, DPH1), Data Pointer (DPL0, DPL1), Data Page Pointer (DPP0, DPP1), MOVX address register (MXAX) STRETCH registers. performs memory addressing data transfers. Allows applications software access external data memory. DPP0, DPP1 registers used segments swapping. STRETCH register allows flexible timing management while accessing different speed system devices programming XRAMWR XRAMRD pulse width between clock periods. Internal Data Memory Interface Internal Data Memory interface controls access into internal bytes memory. contains 8-bit Stack Pointer (SP) register related logic. User SFRs Interface Special Function Registers interface controls access special registers. contains standard used defined registers related logic. User defined external devices quickly accessed (read, written, modified) using direct addressing mode instructions.
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Interrupt Controller Interrupt control module responsible interrupt manage system external internal interrupt sources. contains interrupt related registers such Interrupt Enable (IE), Interrupt Priority (IP), Extended Interrupt Enable (EIE), Extended Interrupt priority (EIP) (TCON) registers. Ports Block contains 8051's general purpose ports. Each port's read/write single 8-bit called Power Management Unit Block contains advanced power saving mechanisms with switchback feature, allowing external clock control logic stop clocking (Stop mode) core lower clock frequency (Power Management Mode) significantly reduce power consumption. Switchback feature allows UARTs, interrupts processed full speed mode enabled. very desired when microcontroller planned portable power critical applications. DoCDDebug Unit it's real-time hardware debugger provides debugging capability whole system. contrast other onchip debuggers DoCDprovides non-intrusive debugging running application. halt, run, step into skip instruction, read/write contents microcontroller including registers, internal, external, program memories, SFRs including user defined peripherals. Hardware breakpoints controlled program memory, internal external data memories, well SFRs. Hardware breakpoint executed write/read occurred particular address with certain data pattern without pattern. DoCDsystem includes three-wire interface complete tools communicate work with core real time debugging. built scalable unit some features turned save silicon reduce power consumption. special care power consumption been taken, when debugger used automatically switched power save mode. Finally whole debugger turned when debug option longer used. Floating Point Unit Block contains floating point arithmetic IEEE-754 compliant instructions float, int, long types supported). used execute single precision floating point operations such addition, subtraction, multiplication, division, square root, comparison absolute value number change
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sign. Basing specialized CORDIC algorithm full trigonometric operations also allowed: sine, cosine, tangent, arctangent. also built-in integer floating point vice versa conversion instructions. supports single precision real numbers, 16-bit 32-bit signed integers. This unit included standard software interface allows easy usage interfacing with user C/ASM written programs. Multiply Divide Unit It's fixed point fast 16-bit 32-bit multiplication division unit. provides shift normalize operations, additionally. operations performed using unsigned integer numbers. contains operands, result registers control register called ARCON. This unit included standard software interface allows easy usage interfacing with user C/ASM written programs. Timers System timers module. Contains bits configurable timers: Timer (TH0, TL0), Timer (TH1, TL1) Timers Mode (TMOD) registers. timer mode, timer registers incremented every periods when appropriate timer enabled. counter mode timer registers incremented every falling transition their corresponding input pins (T0, T1), gates opened (GATE0, GATE1). input pins sampled every period. used clock source UARTs. Timer Second system timer module contains 16-bit configurable timer: Timer (TH2, TL2), capture registers (RLDH, RLDL) Timer Mode (T2MOD) register. work 16-bit timer counter, 16-bit autoreload timer counter. also supports compare capture unit it's presented system. used clock source UART0. Compare Capture Unit compare capture reload unit most powerful peripheral units core. used kinds digital signal generation event capturing such pulse generation, pulse width modulation, measurements etc. Watchdog Timer watchdog timer 27-bit counter which incremented every system clock periods (CLK pin). performs system protection against software upsets. UART0 Universal Asynchronous Receiver Transmitter module full duplex, meaning transmit receive concurrently. Includes
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Serial Configuration register (SCON), serial receiver transmitter buffer (SBUF) registers. receiver double-buffered, meaning commence reception second byte before previously received byte been read from receive register. Writing SBUF0 loads transmit register, reading SBUF0 reads physically separate receive register. Works asynchronous synchronous modes. UART0 synchronized Timer Timer UART1 Universal Asynchronous Receiver Transmitter module full duplex, meaning transmit receive concurrently. Includes Serial Configuration register (SCON1), serial receiver transmitter buffer (SBUF1) registers. receiver double-buffered, meaning commence reception second byte before previously received byte been read from receive register. Writing SBUF1 loads transmit register, reading SBUF1 reads physically separate receive register. Works asynchronous synchronous modes. UART1 synchronized Timer Master Unit controller Master module. core incorporates features required specification. Supports both 7bit 10-bit addressing modes bus. works master transmitter receiver. programmed operate with arbitration clock synchronization allow operate multi-master systems. Built-in timer allows operation from wide range input frequencies. timer allows achieve non-standard clock frequency. controller supports transmission modes: Standard, Fast High Speed 3400 kbs. Slave Unit controller Slave module. core incorporates features required specification. works slave transmitter/receiver depending working mode determined master device. controller supports transmission modes: Standard, Fast High Speed 3400 kbs. Unit it's fully configurable master/slave Serial Peripheral Interface, which allows user configure polarity phase serial clock signal SCK. allows microcontroller communicate with serial peripheral devices. also capable interprocessor communications multi-master system. serial clock line (SCK) synchronizes shifting sampling
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information independent serial data lines. data simultaneously transmitted received. system flexible enough interface directly with numerous standard product peripherals from several manufacturers. Data rates high CLK/4. Clock control logic allows selection clock polarity choice fundamentally different clocking protocols accommodate most available synchronous serial peripheral devices. When configured master, software selects four different rates serial clock. automatically drives slave select outputs SSO[7:0], address slave device exchange serially shifted data. Error-detection logic included support interprocessor communications. writecollision detector indicates when attempt made write data serial shift register while transfer progress. multiplemaster mode-fault detector automatically disables output drivers more than devices simultaneously attempts become master.
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PERFORMANCE
following tables give survey about Core area performance Programmable Logic Devices after Place Route (all features have been included):
Device ORCA Speed grade Fmax
8000 6420 6000
4000 1550 2000
80C51 (12MHz) DR80390XP (40MHz) 80C310 (33MHz)
Core performance LATTICE® devices
user most important application speed improvement. most commonly used arithmetic functions their improvements shown table below. improvement computed {80C51 clock periods} divided {DR80390XP clock periods} required execute identical function. More details available core documentation.
Function 8-bit addition (immediate data) 8-bit addition (direct addressing) 8-bit addition (indirect addressing) 8-bit addition (register addressing) 8-bit subtraction (immediate data) 8-bit subtraction (direct addressing) 8-bit subtraction (indirect addressing) 8-bit subtraction (register addressing) 8-bit multiplication 8-bit division 16-bit addition 16-bit subtraction 16-bit multiplication 32-bit addition 32-bit subtraction 32-bit multiplication Average speed improvement: Improvement 7,20 6,00 6,00 7,20 7,20 6,00 6,00 7,20 10,67 9,60 7,20 7,64 9,75 7,20 7,43 9,04 7,58
Area utilized each unit DR80390XP core vendor specific technologies summarized table below.
Component CPU*
DPTR1 register DPTR0 decrement DPTR1 decrement DPTR0 DPTR1 auto-switch Timed Access protection
Area
[LC/PFU] [FFs]
1590
Interrupt Controller
INT2-INT6
Dhrystone Benchmark Version used measure Core performance. following table gives survey about DR80390XP performance terms Dhrystone/sec MIPS rating.
Device 80C51 80C310 DR80390XP Target ORCA Clock frequency Dhry/sec (VAX MIPS) (0.153) 1550 (0.882) 6420 (3.654)
Power Management Unit ports Timers Timer UART0 UART1 Master Unit Slave Unit Unit Compare Capture Unit Watchdog Timer Multiply Divide Unit Total area
4250/841
1090
*CPU consisted ALU, Opcode Decoder, Control Unit, Program Internal External Memory Interfaces, User SFRs Interface
Core components area utilization
Core performance terms Dhrystones
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main features each DR80390 family member have been summarized table below. gives briefly member characterization helping user select most suitable Core application. User specify peripheral (including listed below others) requests core modifications.
Program Memory space Internal Data Memory space External Data Memory space External Data Memory Wait States Power Management Unit Interface additional SFRs Program Memory Wait States
Architecture speed grade
Compare/Capture
Interrupt sources
Stack space size
Timer/Counters
Interrupt levels
Master Controller Slave Controller
Design
DR80390CPU DR80390 DR80390XP
DR80390 family High Performance Microcontroller Cores
main features each DR8051 family member have been summarized table below. gives briefly member characterization helping user select most suitable Core application. User specify peripheral (including listed below others) requests core modifications.
Program Memory space Internal Data Memory space External Data Memory space External Data Memory Wait States Power Management Unit Interface additional SFRs Program Memory Wait States
Architecture speed grade
Compare/Capture
Interrupt sources
Stack space size
Timer/Counters
Interrupt levels
Master Controller Slave Controller
Design
DR8051CPU DR8051 DR8051XP
DR8051 family High Performance Microcontroller Cores
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Fixed Point Coprocessor Floating Point Coprocessor
Data Pointers
Watchdog
Ports
UART
Fixed Point Coprocessor Floating Point Coprocessor
Data Pointers
Watchdog
Ports
UART
CONTACTS
modification special request please contact Digital Core Design local distributors. Headquarters: Wroclawska 41-902 Bytom, POLAND e-mail: iinffo@dcd.pll o@dcd tel.
Field Office: Texas Research Park 14815 Omicron suite Antonio, 78245,USA e-mail: iinffoUS@dcd.pll oUS@dcd tel. 8268 7511
Distributors: Micro Tech Components GmbH Reitweg 89407 Dillingen, GERMANY
e-mail MTCiinffo@mttc.de
tel. 9071 7945-0 9071 7945-20 Territory: Germany, Austria, Switzerland
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