DFPIC165X low-cost, high performance, 8-bit, fully static soft Core, d

The Datasheet Archive - 100 Million Datasheets from 7500 Manufacturers.

DFPIC165X low-cost, high performance, 8-bit, fully static soft Core, d

Datasheet Thumbnail

Top Searches for this datasheet

High Performance 8-bit RISC Microcontroller 1.42
DFPIC165X low-cost, high performance, 8-bit, fully static soft Core, dedicated operation with fast memory (typically on-chip). core been designed with special concern about power consumption. DFPIC165X software compatible with industry standard PIC16C54, PIC16C55, PIC16C56, PIC16C57 PIC16C58. employs modified RISC architecture times faster than original implementation). DFPIC165X have enhanced core features configurable hardware stack. separate instruction data buses allow wide instruction word with separate -bit wide data. DFPIC165X typically achieve code compression speed improvement over other 8-bit microcontrollers class. Core lines 8-bit timer/counter with 8bit programmable prescaller. power-down mode SLEEP allow user reduce power consumption. User wake controller from SLEEP through user reset watchdog overflow. integrated Watchdog Timer with it's clock signal provides protection against software lock-up. DFPIC165X Microcontroller fits perfectly applications ranging from highAll trademarks mentioned this document trademarks their respective owners.
speed automotive appliance motor control low-power remote transmitters/receivers, pointing devices telecom processors. Built-in power save mode small used area programmable devices make this perfect applications applications with space power consumption limitations. DFPIC165X delivered with fully automated testbench complete tests allowing easy package validation each stage design flow.
FEATURES
Software compatible with industry standard PIC16C5X Harvard architecture times faster compared original implementation instructions wide instruction word bytes internal Data Memory bytes Program Memory Configurable hardware stack Power saving SLEEP mode Fully synthesizable, static synchronous design with internal tri-states Scan test ready
http://www.dcd.pl
Copyright 1999-2003 Digital Core Design. Rights Reserved.
PERIPHERALS
Three ports
Three 8-bit corresponding TRIS registers
Timer
8-bit timer/counter Readable Writable 8-bit software programmable prescaler Internal external clock select Edge select external clock
cases number Core instantiations within design, number manufactured chips unlimited. There time restriction except Year license where time limited months. Single Design license
VHDL,
Verilog source code called
Source
Encrypted, plain text EDIF called Netlist
Year license
Encrypted Netlist only
Watchdog Timer
Configurable Time period 7-bit software programmable prescaler Dedicated independent Watchdog Clock input
Unlimited Designs license
Source Netlist
Upgrade from
Source Netlist Single Design Unlimited Designs
DELIVERABLES
Source code: VHDL Source Code or/and VERILOG Source Code or/and Encrypted, plain text EDIF netlist VHDL VERILOG test bench environment Active-HDL automatic simulation macros ModelSim automatic simulation macros Tests with reference responses Technical documentation Installation notes core specification Datasheet Synthesis scripts Example application Technical support Core implementation support months maintenance
Delivery Core updates, minor major versions changes Delivery documentation updates Phone email support
CONFIGURATION
following parameters DFPIC165X core easy adjusted requirements dedicated application technology. Configuration core prepared effortless changing appropriate constants package file. There need change parts code.
memory type size Program Memory size Number hardware stack levels synchronous asynchronous default kWords default default used unused used width unused used unused used unused
LICENSING
Comprehensible clearly defined licensing methods without royalty fees make using Core easy simply. Single Design license allows Core single FPGA bitstream ASIC implementation. Unlimited Designs, Year licenses allow Core unlimited number FPGA bitstreams ASIC implementations.
SLEEP mode WATCHDOG Timer Timer system PORTS A,B,C
PINS DESCRIPTION
trademarks mentioned this document trademarks their respective owners. http://www.dcd.pl
Copyright 1999-2003 Digital Core Design. Rights Reserved.
clkwdt mclr prgdata[11:0] ramdati[7:0] t0cki portai[7:0] portbi[7:0] portci[7:0] prgdata[11:0] ramdati[7:0] prgaddr[11:0] ramdatao[7:0] ramaddr[7:0] ramwe ramoe sleep portao[7:0] portbo[7:0] portco[7:0] trisa[7:0] trisb[7:0] trisc[7:0]
TYPE
input input input input input input input input input input input input
DESCRIPTION
Global clock Watchdog clock Global reset Power Reset User reset Data from program memory Data from int. data memory Timer input Port input Port input Port input Data from program memory Data from int. data memory clkwdt
Watchdog Timer
Hardware Stack
mclr sleep prgdata prgaddr
Control Unit
Controller
ramdatai ramdatao ramaddr ramwe ramoe portai portbi portci portao portbo portco trisa trisb trisc
t0cki
Timer Ports
output Program memory address output Data internal data memory output address output Data memory write output Data memory output enable output Sleep signal output Port output output Port output output Port output output Data direction pins Port output Data direction pins Port output Data direction pins Port
Arithmetic Logic Unit performs arithmetic logic operations during execution instruction. This module contains work register Status register. Control Unit performs core synchronization data flow control. This module manages execution instructions. Performs decode control functions other blocks. contains program counter (PC) hardware stack. Hardware Stack DFPIC165X configurable hardware stack. stack space part either program data space stack pointer readable writable. pushed onto stack when CALL instruction executed interrupt causes branch. stack popped while RETLW instruction execution. stack operates circular buffer. This means that after stack been pushed times, third push overwrites value that stored from first push. Controller performs interface functions between Data Memory DFPIC165X internal logic. assures correct Data memory addressing data transfers. DFPIC165X supports addressing modes: direct indirect. Direct Addressing 8-bit direct address computed from FSR(7:5) bits least significant bits instruction word. Indirect addressing possible using INDF register. instruction using INDF register actually accesses data pointed
http://www.dcd.pl
SYMBOL
clkwdt mclr prgdata(11:0) ramdatai(7:0) prgaddr(11:0) ramdatao(7:0) ramaddr(7:0) ramwe ramoe sleep portao(7:0) portbo(7:0) portco(7:0) trisa(7:0) trisb(7:0) trisc(7:0)
t0cki portai(7:0) portbi(7:0) portci(7:0)
BLOCK DIAGRAM
trademarks mentioned this document trademarks their respective owners.
Copyright 1999-2003 Digital Core Design. Rights Reserved.
file select register FSR. Reading INDF register indirectly will produce 00h. Writing INDF register indirectly results no-operation. effective 8-bit address obtained from 8bit register. Timer Main system's timer prescaler. DFPIC165X Timer operates modes: 8-bit timer 8-bit counter. "timer mode", timer registers incremented every periods. When prescaler assigned into TIMER prescale ration divided 256. "counter mode" timer register incremented every falling rising edge T0CKI pin, dependent T0SE OPTION register. Watchdog Timer free running timer. clock input separate from system clock. means that will even system clock stopped execution SLEEP instruction. During normal operation, timeout generates Watchdog reset. device SLEEP mode timeout causes device wake-up continue with normal operation. Ports Block contains DFPIC165X's general purpose ports data direction registers (TRIS). DFPIC165X three 8-bit full bi-directional ports PORT PORT PORT Read write accesses port performed their corresponding SFR's PORTA, PORTB, PORTC. reading instruction always reads status Port pins. Writing instructions always write into Port latches. Each port's corresponding TRISA, TRISB TRISC registers. When TRIS register this means that corresponding port configured input (output drivers into High Impedance).
OPTIONAL PERIPHERALS
There also available optional peripherals, included presented DFPIC165X Microcontroller Core. optional peripherals, implemented microcontroller core upon customer request. Full duplex UART Master Slave Serial Peripheral Interface
Supports speeds system clock Mode fault error Write collision error Software selectable polarity phase
rial clock
System errors detection Allows operation from wide range system
clock frequencies (build-in 5-bit timer)
Interrupt generation
Pulse Width Modulation Timer
independent 8-bit channels, concate-
nated 16-bit channel
Software-selectable duty from 100%
pulse period
Software-selectable polarity output wave-
form
controller Master
7-bit 10-bit addressing modes NORMAL, FAST, HIGH speeds Multi-master systems supported Clock arbitration synchronization User defined timings lines Wide range system clock frequencies Interrupt generation
controller Slave
NORMAL speed FAST speed HIGH speed 3400 Wide range system clock frequencies User defined data setup time lines Interrupt generation
trademarks mentioned this document trademarks their respective owners.
http://www.dcd.pl
Copyright 1999-2003 Digital Core Design. Rights Reserved.
PERFORMANCE
following tables give survey about Core area performance Programmable Logic Devices after Place Route (all features peripherals have been included):
Device ORCA ORCA ispXPGA Speed grade Fmax
IMPROVEMENT
Most instruction DFPIC165X executed within cycles. Except conditional program memory branches case that condition branch instruction met. table below shows sample instructions execution times: Mnemonic DFPIC165X operands (CLK cycles) ADDWF ANDWF DECFSZ 2(4)1 INCFSZ 2(4)1 BTFSC 2(4)1 BTFSS 2(4)1 CALL GOTO RETLW
PIC16C54
(CLK cycles)
Impr.
Core performance LATTICE® devices
Area utilized each unit DFPIC165X core vendor specific technologies summarized table below.
Component CPU* Timer Watchdog Timer Ports Total area AREA
PFU] [FFs]
4(8)1 4(8)1 4(8)1 4(8)1
*CPU consisted ALU, Control Unit, Controller, Hardware Stack, External Interrupt Controller
Core components area utilization
number clock case that result operation
DFPIC FAMILY family DFPICXX Cores combine high-performance, cost, small compact size, offering best price/performance ratio Market. DCD's Cores dedicated cost-sensitive consumer products, computer peripherals, office automation, automotive control systems, security telecommunication applications. DFPICXX Cores family contains three 8-bit microcontroller Cores best meet your needs: DFPIC165X 12-bit program word, DFPIC1655X 14-bit program word, DRPIC1655X single cycle microcontroller with 14-bit program word. three microcontroller cores binary compatible with widely accepted PIC16C5X PIC16CXXX. employ modified RISC architecture four times faster than original ones. DFPICXXX Cores written pure VHDL/VERILOG languages which makes them technologically independent. DFPICXX family members supports power saving SLEEP mode allows user configure watchdog time-out period number hardware stack levels. DFPICXX fully customized according customer needs.
Program Memory space Wake port change Watchdog Timer
Levels hardware stack
Program word length
Data Memory space
Number instructions
Sleep Mode
Ports
Design
DFPIC165X DFPIC1655X DRPIC1655X
DFPIC family High Performance Microcontroller Cores
trademarks mentioned this document trademarks their respective owners.
http://www.dcd.pl
Copyright 1999-2003 Digital Core Design. Rights Reserved.
Speed rate
External interrupts
Internal Interrupts
Timer
CONTACTS
modification special request please contact Digital Core Design local distributors. Headquarters: Wroclawska 41-902 Bytom, POLAND e-mail: iinffo@dcd.pll o@dcd tel.
Field Office: Texas Research Park 14815 Omicron suite Antonio, 78245,USA e-mail: iinffoUS@dcd.pll oUS@dcd tel. 8268 7511
Distributors: Micro Tech Components GmbH Reitweg 89407 Dillingen, GERMANY
e-mail MTCiinffo@mttc.de
tel. 9071 7945-0 9071 7945-20 Territory: Germany, Austria, Switzerland
trademarks mentioned this document trademarks their respective owners.
http://www.dcd.pl
Copyright 1999-2003 Digital Core Design. Rights Reserved.

DFPIC165X low-cost, high performance, 8-bit, fully static soft Core, d

Top Searches for this datasheet

Other recent searches