DFPAU uses specialized algorithms compute arithmetic functions. suppor

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DFPAU uses specialized algorithms compute arithmetic functions. suppor

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Floating Point Arithmetic Unit 1.30
DFPAU uses specialized algorithms compute arithmetic functions. supports addition, subtraction, multiplication, division, square root, comparison, absolute value, change sign number. input numbers format according IEEE-754 standard single precision real numbers. DFPAU prepared with 32-bit processors. Trigonometric functions supported indirectly, because they computed add, multiply divide operations software subroutines. DFPAU technology independent design that implemented variety process technologies. Flexible arguments result registers location Performs following functions:
FADD, FSUB FMUL, FDIV FSQRT
addition, subtraction multiplication, division
square root change sign, absolute examine input data comparison
FCHS, FABS
value
FXAM FUCOM
Exceptions built-in routines Masks each exception indicator:
Precision lack Underflow result Overflow result Invalid operand Division zero Denormal operand
APPLICATIONS
Math coprocessors algorithms Embedded arithmetic coprocessor Fast data processing control
Fully configurable Fully synthesizable, static synchronous design with internal tri-states
FEATURES
Direct replacement float software functions such /,==, !=,>=, interface supplied popular compilers: C/C++, 8051 compilers programming required IEEE-754 Single precision real format support float type
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DELIVERABLES
Source code: VHDL Source Code or/and VERILOG Source Code or/and Encrypted, plain text EDIF netlist VHDL VERILOG test bench environment
http://www.dcd.pl
Copyright 1999-2003 Digital Core Design. Rights Reserved.
Active-HDL automatic simulation macros ModelSim automatic simulation macros Tests with reference responses Technical documentation Installation notes core specification Datasheet Synthesis scripts Example application Technical support Core implementation support months maintenance
datai(31:0)1 addr(4:2)2
datao(31:0)1
Delivery Core updates, minor major versions changes Delivery documentation updates Phone email support
PINS DESCRIPTION
datai[31:0] addr[4:2] datao[31:0]
TYPE
Input Input Input Input Input Input
DESCRIPTION
Global system clock Global system reset Chip select read/write Data input Register address read/write Data write enable
LICENSING
Comprehensible clearly defined licensing methods without royalty fees make using Core easy simply. Single Design license allows Core single FPGA bitstream ASIC implementation. Unlimited Designs, Year licenses allow Core unlimited number FPGA bitstreams ASIC implementations. cases number Core instantiations within design, number manufactured chips unlimited. There time restriction except Year license where time limited months. Single Design license
VHDL,
Output Data output Output Interrupt request indicator
data configured depends processor's size address aligned work with (3:0), 16(3:1) (4:2) processors
BLOCK DIAGRAM
Mantissa performs operations mantissa part number. addition, subtraction, multiplication, division, square root, comparison conversion operations executed this module. contains mantissas work registers. Exponent performs operations exponent part number. addition, subtraction, shifting, comparison conversion operations executed this module. contains exponents work registers.
Verilog source code called
Source
Encrypted, plain text EDIF called Netlist
Year license
Encrypted Netlist only
Unlimited Designs license
Source Netlist
Upgrade from
Source Netlist Single Design Unlimited Designs
trademarks mentioned this document trademarks their respective owners.
http://www.dcd.pl
Copyright 1999-2003 Digital Core Design. Rights Reserved.
datai(31:0) datao(31:0) addr(4:2)
Exponent
Mantissa Interface
(8051 clk) divided (DR8051+DFPAU clk), required execute particular instruction.
IEEE-754 Instruction Addition Subtraction Multiplication Division Square Root Sine Cosine Tangent Arcs Tangent Average speed improvement: Improvement
Align
Shifter
Control Unit
Align performs numbers analyze against IEEE-754 standard compliance. Information about data classes passed result appropriate internal module. Shifter performs mantissa shifting during normalization, denormalization operations. Information about shifted-out bits stored rounding process. Control Unit manages execution instructions internal operation required execute particular function. Interface makes interface between external device DFPAU internal 32-bit modules. contains data, control status registers. configured work with 32-bit processors.
More details available core documentation. following table gives survey about DR8051+DFPAU performance compared 8051 microcontroller.
Device 80C51 DR8051 DR8051+DFPAU
Improvement
PERFORMANCE
following table gives survey about Core area performance LATTICE® devices after Place Route (all features have been included):
Speed LUTs/PFUs Fmax grade ORCA 2819/385 ispXPGA 2730/747 Core performance LATTICE® devices Device
80C51
DR8051
DR8051+DFPAU
DFPAU floating point instructions performance been compared standard library functions delivered with every commercial compiler. Each program executed same system environments. Number clock periods were measured between input data loading into work registers output result storing after operation. results placed table below. Improvement been computed number
trademarks mentioned this document trademarks their respective owners. http://www.dcd.pl
Copyright 1999-2003 Digital Core Design. Rights Reserved.
CONTACTS
modification special request please contact Digital Core Design local distributors. Headquarters: Wroclawska 41-902 Bytom, POLAND e-mail: iinffo@dcd.pll o@dcd tel.
Field Office: Texas Research Park 14815 Omicron suite Antonio, 78245,USA e-mail: iinffoUS@dcd.pll oUS@dcd tel. 8268 7511
Distributors: Micro Tech Components GmbH Reitweg 89407 Dillingen, GERMANY
e-mail MTCiinffo@mttc.de
tel. 9071 7945-0 9071 7945-20 Territory: Germany, Austria, Switzerland
trademarks mentioned this document trademarks their respective owners.
http://www.dcd.pl
Copyright 1999-2003 Digital Core Design. Rights Reserved.

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