D16550 soft Core Universal Asynchronous Receiver/Transmitter (UART) fu

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D16550 soft Core Universal Asynchronous Receiver/Transmitter (UART) fu

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Configurable UART with FIFO 1.05
D16550 soft Core Universal Asynchronous Receiver/Transmitter (UART) functionally identical TL16C550A. D16550 allows serial transmission modes: UART mode FIFO mode. FIFO mode internal FIFOs activated allowing bytes (plus bits error data byte RCVR FIFO) stored both receive transmit directions. D16550 performs serial-toparallel conversion data characters received from peripheral device MODEM, parallel-to-serial conversion data characters received from CPU. read complete status UART time during functional operation. Status information reported includes type condition transfer operations being performed UART, well error conditions (parity, overrun, framing, break interrupt). D16550 includes programmable baud rate generator that capable dividing timing reference clock input divisors (216-1), producing clock driving internal transmitter logic. Provisions also included this clock drive receiver logic. D16550 complete MODEM control capability, processor-interrupt system. Interrupts programmed user's requirements, minimizing computing required handle communications link. configuration capability allow user enable disable during Synthesis process Modem Control Logic FIFO's Control Logic,
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change FIFO size. applications with area limitation where UART works only 16450 mode, disabling Modem Control FIFO's allow save about logic resources.
APPLICATIONS
Serial Data communications applications Modem interface
FEATURES
Software compatible with 16450 16550 UARTs modes operation: UART mode FIFO mode Configuration capabilities FIFO mode transmitter receiver each buffered with byte FIFO reduce number interrupts presented Adds deletes standard asynchronous communication bits (start, stop, parity) from serial data UART mode receiver transmitter double buffered eliminate need precise synchronization between serial data Independently controlled transmit, receive, line status, data interrupts False start detection programmable baud generator
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Independent receiver clock input MODEM control functions (CTS, RTS, DSR, DTR, DCD) Fully programmable serial-interface characteristics:
8-bit characters Even, odd, no-parity generation detection 2-stop generation Baud generation
CONFIGURATION
following parameters D16550 core easy adjusted requirements dedicated application technology. Configuration core prepared effortless changing appropriate constants package file. There need change parts code.
Modem Control logic Register FIFO Control logic enable disable enable disable enable disable
Complete status reporting capabilities Line break generation detection. Internal diagnostic capabilities:
Loop-back controls communications link fault isolation Break, parity, overrun, framing error simulation
FIFO size
Full prioritized interrupt system controls Fully synthesizable static design with internal tri-state buffers
LICENSING
Comprehensible clearly defined licensing methods without royalty fees make using Core easy simply. Single Design license allows Core single FPGA bitstream ASIC implementation. Unlimited Designs, Year licenses allow Core unlimited number FPGA bitstreams ASIC implementations. cases number Core instantiations within design, number manufactured chips unlimited. There time restriction except Year license where time limited months.
DELIVERABLES
Source code: VHDL Source Code or/and VERILOG Source Code or/and Encrypted, plain text EDIF netlist VHDL VERILOG test bench environment Active-HDL automatic simulation macros ModelSim automatic simulation macros Tests with reference responses Technical documentation Installation notes core specification Datasheet Synthesis scripts Example application Technical support Core implementation support months maintenance
Delivery Core updates, minor major versions changes Delivery documentation updates Phone email support
Single Design license
VHDL, Verilog source code called Source Encrypted plain text EDIF called Netlist
Year license
Encrypted Netlist only
Unlimited Designs license
Source Netlist
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Source Netlist Single Design Unlimited Designs
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DESIGN FEATURES
functionality D16550 core based Texas Instruments TL16C550A. following characteristics differentiate D16550 from Texas Instruments devices: bi-directional data been split into separate buses: datai(7:0), datao(7:0) Signals wr2, xin, xout have been removed from interface Signal address latch have been removed DLL, registers reset zeros TEMT THRE bits Line Status Register, reset during second clock rising edge following write latches implemented original 16550 devices replaced equivalent flip-flop registers, with same functionality
addr
APPLICATION
addr latch addr(2:0) D16550 datai(7:0) datao(7:0) rxrdy txrdy out1 out2 baudout rclk
datao(7:0) datai(7:0)
Drivers
Typical D16550 processor connection shown figure above.
PINS DESCRIPTION
TYPE
input input input input input input input input input input input input input output output output output output output output output output output output
DESCRIPTION
Global reset Global clock Receiver clock Parallel data input Address Chip select input Write input Read input Serial data input Clear send input Data ready input Data carrier detect input Ring indicator input Parallel data output Serial data output Baud generator output Driver disable output Transmitter ready output Receiver ready output Request send output Data terminal ready output Output Output Interrupt request output
SYMBOL
rclk datai(7:0) addr(2:0) baudout intr datao(7:0) ddis txrdy rxrdy out1 out2
rclk datai[7:0] addr[2:0] datao[7:0] baudout ddis txrdy rxrdy out1 out2 intr
D16550
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BLOCK DIAGRAM
Data Buffer data Buffer accepts inputs from system generates control signals other D16550 functional blocks. Address ADDR(2:0) selects register read from/written into. Both signals active low. Both qualified ignored unless D16550 been selected holding low. Baud Generator D16550 contains programmable baud generator that divides clock input divisor range between (216-1). output frequency baud generator baud rate. formula divisor
UART will issue interrupt CPU. FIFO will continue store bytes until holds them. will accept more data when full. more data entering shift register will Overrun Error flag.
addr(2:0) datai(7:0) datao(7:0) ddis txrdy rxrdy out1 out2
Data Buffer
Receiver Control Shift Register
rclk
RCVR Buffer RCVR FIFO
divisor
frequency baudrate
Modem control logic
Transmitter Control Shift Register
8-bit registers, called divisor latches DLM, store divisor 16-bit binary format. These divisor latches must loaded during initialization D16550 order ensure desired operation baud generator. When either divisor latches loaded, 16-bit baud counter also loaded rising edge following write prevent long counts initial load. Modem Control Logic controls interface with MODEM data peripheral device emulating MODEM). Interrupt Controller D16550 consists fully prioritized interrupt system controller. controls interrupt requests interrupt priority. Interrupt controller contains Interrupt Enable (IER) Interrupt Identification (IIR) registers. Receiver Control D16550 receiver independent clock input RCLK. Receiving starts when falling edge Serial Input (SI) during IDLE State detected. After starting input sampled every RCLK cycles shown figure below. When logic state detected during START means that False Start detected receiver back IDLE state. Receiver FIFO FIFO levels deep, receives data until number bytes FIFO equals selected interrupt trigger level. that time interrupts enabled,
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baudout
Baud Generator
RCVR Buffer RCVR FIFO
Interrupt Controller
intr
Transmitter Control module controls transmission written (Transmitter Holding register) character serial output transmission starts next overflow signal internal baud generator (the worst case delay baudout cycle) after writing register Transmitter FIFO. Transmission control contains register transmitter shift register. Transmitter FIFO portion UART transmits data through soon loads byte into FIFO. UART will prevent loads FIFO currently holds characters. Loading FIFO will again enabled soon next character transferred shift register. These capabilities account largely autonomous operation UART starts above operations typically with interrupt.
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PERFORMANCE
following table gives survey about Core area performance LATTICE® devices after Place Route (all features have been included):
Speed LUTs/PFUs Fmax grade ORCA ORCA Core performance LATTICE® devices Device
CONTACTS
modification special request please contact Digital Core Design local distributors. Headquarters: Wroclawska 41-902 Bytom, POLAND
o@dcd e-mail: iinffo@dcd.pll
tel.
Field Office: Texas Research Park 14815 Omicron suite Antonio, 78245,USA
oUS@dcd e-mail: iinffoUS@dcd.pll
tel. 8268 7511
Distributor: Micro Tech Components GmbH Reitweg 89407 Dillingen, GERMANY
e-mail MTCiinffo@mttc.de
tel. 9071 7945-0 9071 7945-20 Territory: Germany, Austria, Switzerland
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D16550 soft Core Universal Asynchronous Receiver/Transmitter (UART) fu

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