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Behavioral Modeling VHDL Simulations Benefits Higher Levels Abstraction Complex Simulations Conference Presentation Lattice DesignCON, 1999
Presentation Introduction
This paper originally prepared presentation given PLDCon '99. format paper follows structure foil presentation that given conference. section headings actually represent headings that were used each foil. This allows follow presentation with graphics from presentation foils where appropriate.
Objectives
objective this paper associated presentation Identify basic requirements simulating programmable logic designs Show common mistakes made simulation Demonstrate simple test bench techniques exacerbate many errors Propose methods based behavioral modeling that provide superior simulation capabilities Show VHDL well suited behavioral modeling Demonstrate example project based modeling purpose this presentation exhaustive treatise methods techniques, review code included example will long toward instructing motivated reader.
Agenda
agenda presentation includes following: Acknowledgements Overview Simulating FPGA CPLD Designs Survey Common Methods VHDL Features that Support Modeling Abstraction Designing Test Bench using Models Evaluating Benefits References
Acknowledgements
would like thank following individuals acknowledge their contributions this effort: from Vantis: Doug Hardman, Andy Robin, Holland, Klein Kayla Kurucz; from Ramix Corporation: Saeed Karamooz, allowed Mach CPLD design example this paper; finally wife, Robin, whose patience encouragement enabled write this paper.
Overview Simulating FPGA CPLD Designs
Reasons Simulate
Improve product quality reliability
Controllability observability factors enabling proper testing design. Many times simulation test situations that difficult generate prototype debug environment. Boundary conditions easily checked when have complete control environment. Worst case conditions include simultaneous occurrence independent functions that very difficult achieve actual system.
Publication CP001-2 Ammendment:
Revision: Issue Date: February 1999
These conditions easily made coincide simulation that completely controllable. addition having more control over circuit, simulation also enables more complete observations design. Internal signals available regardless whether there spare pins device. With keystrokes, 64-bit data probed. that with logic analyzer! could take better part complex design instrumented monitoring.
Decrease time-to-market shortening debug integration cycle
same simulation advantages controllability observability allow errors caught more quickly easily than with hardware debugging. Even more important, design changed much more quickly simulation than hardware prototype. This shortens debug cycle makes integration easier, especially different modules have been simulated together before integration.
Reduce risk
only debug cycle decreased when simulation used, number magnitude design changes decreases well. This decreases chance that changes hardware will extensive enough require printed circuit board design. Turning easily adds weeks schedule. When pushing performance density limits, confidence that available programmable devices will perform desired functions. Simulation answer these questions before expending time expense building hardware prototype. When design breaks ground, even known early design cycle whether basic design approach feasible. Simulation inexpensive determining this simulation techniques powerful enough simulate system level aspects design.
Reasons Engineers Avoid Simulation
Lack discipline poor habits
Many engineers love tinker. These will often forgo rigorous analysis design assumptions because they feel more comfortable tweaking design into submission. Early SRAM FPGAs required tweaking because timing models were variable. Rigorous analysis front difficult difficult achieve actual devices. "blow methodology developed into high those days. With FPGA families like from Vantis, deterministic, delays high-speed designs achievable dependable. development tools that Vantis some other vendors have brought market also supporting ASIC-like methodologies that support rigorous analysis, modeling simulation.
Difficulty justifying simulation phase management
Many managers understand benefits simulation. They unwilling allow enough time schedule something that they understand. This difficult situation, better have engineer that understands importance simulation, even management requires some education. helpful utilize methods that increase productivity simulation enable more done less time.
Difficulty generating successful simulations
Some engineers trapped low-level methods antiquated simulation techniques, they have never made jump successfully simulating complex systems efficiently. using modeling techniques higher levels abstraction, they simulate their designs more efficiently achieve their objectives more easily.
Behavioral Modelling VHDL Simulations
Common Simulation Mistakes
Using simple methods complex designs Simple methods become tedious ineffective
designs become more complex, more powerful simulation techniques needed because they actually decrease complexity design verification. wise engineer once said that there only methods handling complexity, hierarchy abstraction. Modeling techniques make both these allow simulation complex system both manageable efficient.
fault coverage
fault coverage allows design errors missed during simulation. reason that test case considered properly during planning stages. While this more specification issue than implementation issue, more efficient simulation techniques enable individual team more aggressive specifying test scenarios. Another cause fault coverage that test scenario considered, properly implemented. When level methods used which adequately handle complexity design, engineer lose forest trees.
qualifying circuit responses properly
design increases size, becomes more more difficult characterize behavior circuit visual inspection waveforms. Unless test bench validates circuit responses automatically, burden finding each discrepancy rests with engineer. While this work well simple circuits, designs more complex, engineer longer capable keeping with vectors that generated.
Goals Good Test Bench
Completeness
High fault coverage essential effective simulation project. good simulation strategy will facilitate development test bench that covers pertinent operational scenarios. This best achieved using techniques that allow simulation designer work fairly high level abstraction. easier follow flow simulation specify individual steps macro level rather than atomic level. "Perform this operation" more easily understood validated than "Twiddle these bits". good simulation technique should support high level abstraction. VHDL, with many features that support behavioral modeling high level, easily satisfies this requirement.
Ease
almost goes without saying that simulation method should easy use. There trap here, however. methods that easy small design scale well larger design. Modeling allows build "virtual system" check design under test ("DUT") exercising realistic operational environment. This some overhead that makes impractical small projects, especially models built. However, verified models already available, even small designs done efficiently with virtual system approach.
Flexibility
good simulation methodology must flexible allow changes simulation knowledge gained requirements change. Object oriented techniques offer this kind flexibility programmers. Embedding functionality into system level components some similar benefits engineer designs simulation complex chip system.
Behavioral Modelling VHDL Simulations
Reusability
Design reuse becoming major driver closing productivity deep submicron VLSI design methodologies. High density FPGAs CPLDs that promise fast time market will require similar techniques these goals realized.
Modeling Meet Goals?
These goals largely complementary. simulation strategy that easy makes completeness easy achieve. flexible implementation method generally easy use. Flexibility generally helps reusability, allowing components used variety environments. Reuse familiar components tremendous impact ease use. Modeling techniques should meet these goals.
High levels abstraction should focus completeness
Simulation methods based modeling system level components naturally work high level abstraction. Having model allows types cycles specified. model complete, then assembly language code could actually used drive simulation. This allows engineer focus functional requirements test, leaving twiddling bits hardware model.
Benefits should outweigh effort model generation validation
benefits using models should outweigh effort model generation validation. After brief survey modeling techniques, reader will able decide this case.
Modularity encapsulation components should help flexibility
Properly designed components should mimic system should able modified system modified. Proper modeling should yield very flexible simulation architectures.
Behavioral models should reusable like integrated circuits
Components imply reusability they made generic. hardware components that typically used electronic board system made widely useful possible. will easy reuse VHDL components that model these same hardware devices.
Survey Common Methods
Typical Simple Test Bench
(Block Diagram Included Presentation)
Review Test Bench
typical test bench, structure simple flat. instantiated component, single process controls main test sequence. Circuit stimulus generated in-line code multiple wait statements control main sequence timing. Alternatively, multiple "after" conditions single transport statement each signal could used control timing. Most novice users VHDL simulation validate circuit responses inspecting resulting waveforms. test bench does little qualification circuit performance.
Simple Test Bench Coding Example
main stimulus process p_stim: process begin main stimulus process p_stim: process begin
Behavioral Modelling VHDL Simulations
'1'; '1'; end_in (others '0'); '1'; wait clk_period*2; '0'; wait clk_period; assert (out_bus x"5") report "Out reach count severity error; waitn '0'; wait clk_period*2; waitn '1'; wait clk_period*20; assert false report "Reached stimulus." severity note; process;
Simple Test Bench Coding Analysis
abstraction leads flat, difficult implementation
Because flat, simple structure this test bench, implementation difficult simplest simulations. example, might want vary timing control signals order verify that will tolerate allowed variation inputs. This very difficult achieve function timing input signals into single large process. There separation between function timing, flexibility compromised.
Wait statements transport statements
Multiple wait statements used control sequencing various signals. Unfortunately this cause timing individual signals interact this become quite complex. virtually impossible vary signals intelligently, example allow min/max timing. interaction signals that controlled common wait states would make this terribly complex problem. alternative individual transport statements each signal. This allows series delays specified each individual signal. While this decouples signal timing, multiple wait statements easier step through during debugging than transport statements. third alternative separate process each signal have them synchronized master process that marks start each cycle.
High level level controls intermixed
difficult concentrate many issues time. simple structure intermixes main test sequencing code with intricacies individual signal timing. This difficult model control, interpret modify. partitioning high level level code needed large, complex designs.
Repetitive code difficult manage
With abstraction, code often pasted implement repetitive operations, case cycles. This very difficult manage. better approach loop repeat steps, this flat model that gets complex several functions processes need repeated interactively.
Interactive code intuitive
Often best check interface interactive. device interface handshake, then reasonable have process test bench that responds that handshake. normal handle this with independent process that participates handshaking throttles transfer data. This efficient, moves away from mainline code. designed that structure function unified.
Behavioral Modelling VHDL Simulations
Improved Simple Test Bench
(Block Diagram included Presentation) improve this simple model slightly adding statements that will check responses DUT. will seen later, simple structure associated with this kind test bench does support very well addition code check responses.
Improved Test Bench Analysis
Checking data automatically mixed blessing
Adding data checking simple test bench improve efficiency relieving engineer some tedium checking simulation results. difficult with simple test bench have enough control checking that required make sure that hardware circuit will perform same simulated model does. Just sampling data correct time difficult. Checking setup hold times other parameters importance daunting task when code simulation forced reside single process fairly flat model. situation remedied somewhat setting multiple process check signals, parameters interfaces, again ad-hoc process, often with little guidance standardization.
Test Bench Using Modeling
(Block Diagram Included Presentation)
Improved Modeling Test Bench
(Block Diagram Included Presentation)
Characteristics Modeling
basic idea behind test bench based modeling create functional models board level components that surround design under test, DUT. top-level file usually composed structural VHDL code that ties various models together instantiated components. perhaps more) components DUT. other components functional equivalents devices that surround actual board. example, CPLD design destined Vantis M4A-192/965 needs simulated. design interface between i960RP microprocessor dual banks SRAM memory. allows memory accessed half speed alternating access banks SRAM. CPLD DUT, CPU, clocks, transceivers SRAM must modeled. VHDL modeling language that readily supports such device modeling.
Models Generate Stimulus
Since behavior actual components modeled test bench, models themselves generate stimulus DUT. This frees engineer from having explicitly define each vector. Instead, simulation driven high level operations that built into models. example, both memory SRAM controller slave devices. Therefore model drives simulation. designer needs only specify sequence cycles with method route data into design. model will generate individual signals. handling simulation this higher level, designer concerned with system level functions models handle details. Once models generated, complex functional simulation generated much faster than with level methods.
Models Check Responses
earlier example, check function could have been included test bench check address data hold time. This checking done better inside SRAM model because coded place will active time SRAM accessed. Control path timing function easily
Behavioral Modelling VHDL Simulations
implemented behavioral models. Some data path functions tested internal models, case generator/checker, which internally verify data, patterns. Other solutions implemented well. model might perform write readback cycles verify operation memory subsystem. SRAM model might implemented array, simply storing data array locations according address. Another choice would build model that could transfer address memory data disk file verification later inspection even have model read expected values from file compare them values received from simulation. example, memory implemented small array because there requirement pass large amounts data through design. model responsible verifying data integrity, SRAM model checks proper signal timing coming from DUT.
Main control process level test bench
main difference modeled test bench from simple case lack functional code. primarily structural module, mechanism controlling simulation sequence immediately evident. example, master system, driven program code. control simulation this case? straightforward encode into model operations that required tests. This allows test sequence specified necessary operations, writing reading data verify proper operation.
Using VHDL Modeling
VHDL originally defined pure modeling language
VHDL originally conceived pure modeling language. This some difficulties early those wanted VHDL synthesis because many useful modeling constructs were appropriate synthesis. full range VHDL's modeling capability used generating behavioral models used simulation. Very complex behavior specified without regard adhering standard synthesis. Even analog mechanical systems modeled using mathematical functions available. analog extensions being considered VHDL primarily extensions math functions that currently available language. Because simulation models have synthesized, many high level behavioral constructs used simplify generation functional models. Defining functions according components that perform them yields functional decomposition that encourages higher level abstraction. This decouples functional specification from low-level operational details simplifies task writing test program.
Structure Begets Structure
beauty getting started with modeling test bench that abstract arcane method needed figure start. really quite straightforward. structure hardware design structure test bench. like object oriented programming which required wholesale paradigm shift which challenging programmers been steeped structured programming methods. contrary, building test bench with functional models requires same analytical view than engineers have developed through years working with schematics equipment. simply replaces components board with functional components VHDL design, then figures model each component. Planning simulation much like planning early stages prototype debug when hardware engineer often writes diagnostic code first checkout. Planning control mechanism little trying, because different from simpler methods. once method controlling master established, exercising slave devices system simple matter. example, SRAM slave, merely responds memory controller. model another story. must controlled order control flow simulation. would impractical fully model complete CPU. simpler mechanism must devised. control functions could encoded actual assembly language directives, this would overkill would difficult use. more reasonable approach would implement basic operations that used
Behavioral Modelling VHDL Simulations
transfer data, encode these into special codes that could used control flow data through system. example, must execute single burst mode read write operations, these would place start. codes stored VHDL code model, could read model from text file that instructions listed desired order execution. Driving simulation with sequence high level commands satisfies need control simulation flow from high level abstraction, making easy focus system level considerations associated with covering pertinent test scenarios.
Behavior Encapsulated
Localizing function enhances flexibility
function SRAM model defined only once, inside SRAM model. timing SRAM independent timing, chip select decoder, other components system. Therefore other parts system modified independently without regard SRAM. This achieving flexibility. SRAM needs modified, definitions localized, they need changed only area. earlier example, timings interacted, were spread
Model characteristics defined independently
functions each model, thus each interface, more easily defined because they don't interact with characteristics other models. When defining SRAM, need only concerned with details SRAM itself. speed processor characteristics state machine consequence when defining SRAM model.
Validation Models
Models must validated level abstraction, looking explicitly detailed function timing. best done different engineer than will models prevent "selffulfilling prophecies". engineer develops models, validates them, uses them, same assumptions blind spots perpetuated throughout whole process. Encapsulation allows model validated independently final application. Generally speaking, model correct, model will work valid application.
VHDL Features that Support Modeling Abstraction
Multiple Architectures
would want multiple architectures simulation? There many good reasons. These just few:
re-implement difficult structures just simulation
Often structure design cause problems simulation. Consider case long counter, which requires many thousands simulation cycles before anything interesting happens. instantiate counter component that architecture synthesis that would require long timeout. second architecture, used only simulation, could have much shorter timeout cycle.
gate level behavioral models
Another multiple architectures could applied board level simulation multiple chips. Gate level models simulate much more slowly than behavioral models. could substitute behavioral models devices interest, then perform simulations much faster. Once design looks sound, gate level models could used.
Behavioral Modelling VHDL Simulations
iterate test bench design
Often simplest type simulation implement first time most efficient. example, first model that developed used simple process which control functions implemented directly VHDL code. This less efficient than model that used test language parser drive simulation, simpler bring first time. While bringing more complex parsing routine, could keep original model alternative architecture comparison with architecture.
Attributes
VHDL rich attributes that extract information from signals other objects that extremely useful simulations, especially checking functional timing operation. They universally attached prefix, case familiar "clk'event". most useful listed below: Signal'event Returns true value signal event (changed value) during current simulator tick. This useful synchronizing events with strobe signal. example, when goes high SRAM, then write cycle have taken place. This would appropriate time execute appropriate code inside process that models SRAM. Returns value signal prior last event. Returns time elapsed since most recent event signal. This could useful SRAM model address been stable throughout duration write cycle. Returns time elapsed since most recent transaction (scheduled event) signal Returns true value transaction (scheduled event) occurred signal during current simulator tick. Creates text image specified expression. This useful text reports. Expression must same type type which attribute attached. Returns value attached type Creates signal identical attached signal only delayed time. Creates Boolean signal that becomes true when signal stable specified time period. This could used checking setup hold times. Creates Boolean signal that becomes true when signal quite (having events scheduled) specified time period. Creates signal that toggles when transaction event occurs signal Returns position number particular value specified enumerated type. This useful generate integer that references value enumerated type. Returns value enumerated type from specified integer value. first enumerated value position number subsequent values have numbers 1,2,3. respectively.
Signal 'last_value signal 'last_event
signal 'last_active signal 'active type'image(expression)
type'value(string) signal 'delayed(time) signal 'stable(time) signal 'quite(time) signal 'transaction type'pos(value)
type'val(integer)
Control Structures
if-then-else, case, looping structures that VHDL provides sequential statements extremely useful controlling flow simulation program. Remember that if-then-else statements cause quite logic generated synthesis program, this consequence when developing models simulation only. if-then-else structure model very complex behaviors natural style that easy define. more structured conditional structures, case statement should used. various loop structures quite useful repetitive operation. should remember that VHDL, process automatically restarts once completed (subject whatever WAIT statements sensitivity lists included), explicit loop structure needed.
Behavioral Modelling VHDL Simulations
Wait Statements
Wait statements extremely useful controlling timing scheduling events assertions. three uses wait statement listed below:
Wait (time) Wait until (condition) Wait (sensitivity list)
Suspends execution until specified time period elapsed Suspends execution until specified condition true Suspends execution until event occurs signals listed sensitivity list
Transport Delay Specifications
Easier than wait statements?
transport delay specification used time signal transitions much same that wait statements used. difference that wait statements advance simulation time, affecting timing signals together. Transport delays control timing series transitions single signal, independent other signals. wait statement still required advance simulation time, timing sequence specified transport statement will roll simulation event wheel time advances. much easier specify signal transitions individually with transport statements, generally more difficult unravel timing when stepping through code during debug. alternative separate processes each signal using wait statements. This easily debugged also easily specified. This spreads code over many processes that difficult follow large number signals, benefits worth
Transport Example:
SIG0 transport after after after
Assert Statements
Generate messages during simulation
Assert statements check whether certain condition true generates message condition true. This enables self-checking models that will report violations automatically. They used check that data correct. Using signal attributes, they also validate that required specifications met. example, SRAM requires data address write pulse. data must write pulse, address must stable throughout. Assert statements used within SRAM model check these conditions report error they met. Remember that 'image attribute used generate string representations expressions that displayed message.
File 1076-1993
file input/output functions 1987 standard were somewhat limited. 1993 version added syntax enhancements features extend file capabilities language. file input functions VHDL used various ways. primary uses are: Application stimulus vectors Storage response vectors Storage expected responses comparison (using assert) Formatted reports
Behavioral Modelling VHDL Simulations
Reading custom test language files (which then parsed)
This last technique used with higher level abstraction control simulation. Since commands specified functional level, detailed implementation left functional models, which respond each command they have been programmed This very powerful technique driving simulations high level. designer's system-level knowledge leveraged greatest degree because control exercised level that most convenient checking system function.
File Commands
File_open(file,name,mode) File_open(status,file,name, mode) File_close(file) Read(file,object) Readline(file,line) Write(file,object) Writeline(file,line) Endfile(file) Opens file object with specified name mode read, write append. Opens file object with specified name mode read, write append, assigns value status type file_open_status that value OPEN_OK, STATUS_ERROR, MODE_ERROR NAME_ERROR Closes specified file Reads from specified file into specified object. Read line from specified file Writes specified object specified file Writes line specified file Returns boolean true value file pointer specified file file
Text
Additional text handling commands added standard textio package Apply_exponent This procedure reads numeric characters character uses them exponent rval parameter. indicates success operation through parameter. Apply_exponent This procedure reads numeric characters character uses them exponent rval parameter. indicates success operation through parameter. Apply_fraction This procedure reads numeric characters character from aline variable converts them into fractional number. indicates status conversion throught parameter. Apply_mantissa This procedure reads numeric characters character until encountering character. converts these characters into real number indicates problems through parameter. Extract_integer Once optional leading sign removed, integer contain only digits through (underscore) character. VHDL disallows successive underscores, leading trailing underscores. Extract_real This procedure reads numeric characters character until encountering character. converts these characters into real number indicates problems through parameter. Grow_line This procedure increases length specified line indicated increment Int_to_string This procedure convert string integer
Behavioral Modelling VHDL Simulations
C-Language Interface
Drive simulation from program:
Most VHDL simulation packages allow user interface actual executable programs simulation. These programs, usually written language, allow very complex behaviors implemented without speed space overhead associated with using VHDL models. Alternately, whole system could modeled This could faster than VHDL large simulations, would require mixed environment including both VHDL development tools. This could good approach engineer familiar with especially works company where systems simulated before they partitioned handed circuit designers implementation.
System Modeling
Saeed Karamooz Ramix, customer developed SRAM controller used this presentation, also developed unique method modeling. involved modeling system environment programming language writing stimulus vectors text file. vectors were then applied device under test straightforward fashion, response vectors stored another file. These were analyzed similar program, also written nice thing about this technique that applicable virtually simulation environment tool. biggest problem that interactive. Handshaking possible, does have power flexibility that would possible from writing VHDL models. this technique were used conjunction with language interface VHDL simulator, flexibility would lost.
Other Useful Features
Component Instantiation
Models simply instantiated design components. Signals used connect models DUT, just they were actual components board.
Generics
Generics allow passing numeric parameter, instance specific information, into entity. This allows parameterized models, which more flexible their application reuse. example, SRAM model could developed that would have variable size width. Even delays could passed into each instance component's instantiation.
Arrays User Defined Types
Arrays useful many reasons. simple sequence through list vectors patterns application circuit. technique that used example define array type that used specify what kind delay used simulation: None, Minimum, Typical Maximum.
Packages
Packages allow parameters test program defined common file. This useful type complex design, they especially useful defining
Behavioral Modelling VHDL Simulations
Designing Test Bench using Models
IEEE Notes Behavioral Modeling
SLIDE2N.HThese notes excellent guidelines writing behavioral models. Rather than rewrite them, have cited source, which study further your own. points made are: Model system multiple levels abstraction. Hide structure Focus behavior functionality level abstraction, ignore timing. Follow standard practices software engineering Simplifies maintenance reuse Structure design Define each component have strong cohesion Define components loosely coupled top-down iterative refinement abstract data typing hide encapsulate data Using VHDL, system designer model circuit (i.e., component system) multiple levels abstraction. prior lessons, have concentrated basic elements structural forms describing models VHDL. this module concentrate behavioral view, that describing circuit perform. hide structure design when modeling circuit behaviorally. Instead, vitally interested functionality circuit. highest levels abstraction, even ignore timing. When modeling VHDL important follow standard practices software engineering. Otherwise, model will hard maintain, even person wrote addition, reuse models, even "throw-away" models should created with care, with thought that others Typical model design coding practices include structuring design, iteratively refining high-level view model down final form, employing abstract data typing hide encapsulate data, organizing individual model components that they loosely coupled (small number interface signals) have strong cohesion (keep strongly related functions same architectural body). Reference:
Level Schematic
(Schematic Diagram Included Presentation) schematic, design CPLD-based SRAM controller linked models other major components design. This CPLD design belongs Ramix Corporation targeted Mach M4-192/96-7 part. This part chosen because SpeedLocking internal delays allowed part work effective internal frequency MHz. State changes were required both edges clock, part only with desired density that would work. Vantis' micron family, which sampling this paper written, will push usable frequency around MHz. models listed below with short description.
i960 model
architectures
model architectures. main process embedded VHDL code drives first itself. test language-parsing engine drives second. special instructions that recognized parser listed below. text-parsing engine seem like extra level complexity, first implementation offers great advantage flexibility ease use. first architecture requires that VHDL file recompiled loaded every time change test sequence made. This violates desire decouple high level tasks from low-level tasks. instructions
Behavioral Modelling VHDL Simulations
simple modeled after operations that required. Modeling assembly language codes would have been complex would have been less useful. this model, only instructions were needed, these include setting address data given operation.
Control Instructions
Address Data Write single Enable data checking Read single Number burst cycles Wait cycle Number wait cycles Write burst Read burst Model Control Instructions Specifies address used subsequent read write operations Specifies data used subsequent read write operations Performs single write cycle Enables checking data read back during read operations Performs single read cycle Specifies number burst cycles during subsequent burst reads writes Specifies which cycle cause wait cycle during burst reads writes. Specifying disables wait states. Specifies number wait cycles insert during subsequent burst reads writes wait cycles enabled) Perform burst write cycles Perform burst read cycles
With these instructions, various modes reading writing SRAM checked. Simple combinations commands used implement required test scenarios. This model used system that requires this functionality i960 CPU.
SRAM model
simplicity, SRAM model built from simple deep arrays data, lower address space model, other end. second array implemented allow access roll over from page another. model responds standard SRAM control signals, write enable, output enable, chip select, address data. Data stored into array when legal write cycle executed retrieved when legal read cycle executed. addition storing retrieving data, model also checks SRAM timing requirements, enabled. timing parameters selected none, minimum, typical maximum. minimum access time doesn't really matter, zero delay. When timing checks done model, where makes most sense, model used system will automatically function properly. error checking code doesn't have reimplemented each application. Thus ease use, reuse, enhanced.
Other Models Required
Chip Select Decode Model
This simple combinatorial decoder function with parameter checking. function propagation delay timing actual circuit duplicated. delay selected none, minimum, typical maximum.
Latched Transceiver Model
This simple sequential model with limited parameter checking setup hold. function propagation delay timing actual circuit duplicated. delay selected none, minimum, typical maximum.
Behavioral Modelling VHDL Simulations
Test Language Parsing Engine
test language parser powerful tool extending capability VHDL simulator which allows (with functional models) conceptualize simulation high level abstraction which increases productivity efficiency. cycles i960 will form basis custom test language. useful, instructions will also added read contents SRAM model directly, allow verification write functions independently read functions.
Test Scenarios
simple function this circuit requires very simple test cases. Each cycle types i960 model will exercised writing SRAM reading back. Single Write then Read Bank Start Burst Write then Read Bank Start With/without wait states With/without SRAM page break Overlap wait states with page break
Third Party Model Sources
standard models available (PCI, SCSI, VME, ISA, etc.) well more specific models that often supplied vendors cores. Logic Modeling division Synopsys offers wide variety interface models that verifying compliance interoperability standard designs. Many other third party vendors supply wide variety cores well. impressive list non-commercial model sources listed
Evaluating Benefits
Example Waveform Display
(Example Waveform Display from Model Technology Simulator Included Presentation)
High Level Simulation
following sample listing from simulation from modeling test bench. This examined seconds there were errors. While take more work first simulation running, that each time simulation run, time savings huge. Testing Single Write, Even Start Testing Single Read, Even Start **Error I960RP: Data Error, Address: 000000, Data was: uuuuuuuu 55555555 Testing Single Write, Start Testing Single Read, Start Testing Burst Write, Even Start, Page Break Testing Burst Read, Even Start, Page Break Testing Burst Write, Even Start, With Page Break Testing Burst Read, Even Start, With Page Break Testing Burst Write, Even Start, With Page Break last cycle Testing Burst Read, Even Start, With Page Break last cycle Testing Burst Write, Start, Page Break Testing Burst Read, Start, Page Break Testing Burst Write, Start, With Page Break Testing Burst Read, Start, With Page Break Testing Burst Write, Even Start, Page Break, single wait cycle Testing Burst Read, Even Start, Page Break, single wait cycle Testing Burst Write, Start, Page Break, single wait cycle
Behavioral Modelling VHDL Simulations
Testing Burst Read, Start, Page Break, single wait cycle Testing Burst Write, Start, With Page Break, single wait cycle **Error SRAM512: Address Changed during Write, Address: 000004, Data: aaaaaaaa Testing Burst Read, Start, With Page Break, single wait cycle Testing Burst Write, Start, Page Break, longer wait cycle Testing Burst Read, Start, Page Break, longer wait cycle Testing Burst Write, Start, With Page Break, longer wait cycle Testing Burst Read, Start, With Page Break, longer wait cycle Test Complete There were errors during this test
Comparison Results
Checking Waveform Checking Listing
Even simple waveform display, like shown presentation, many points that need checked. This becomes tedious page after page nearly impossible catch errors. this needs done after each several changes, very unreliable. Many errors could undetected. Checking listing from behavioral model test bench easy. last line tells there were errors. there were not, done. there were, quick inspection reveals location, along with clue location cause. checks done automatically each time simulation run. errors that missed easily corrected updating models, error should caught subsequent runs.
Completeness
Higher level abstraction
Testing designs such high level abstraction many benefits. First, frees engineer dealing with minute details signal timing sequencing while designing simulation flow necessary test cases. These details handled level model building. This focuses attention insuring that pertinent test scenarios covered
Components allow self-checking test benches
Using self-checking test bench makes running simulations validating results much easier because models checking automatically. This eliminates need scrutinize hundreds thousands lines vectors waveforms each time simulation run.
Modeling favors test benches which conform actual usage
Since structure function models test bench parallels actual hardware design, easier insure that tests cover operational modes interest.
Ease
Models generated separate group, developed without regard final circuit configuration. This advantage because jobs done parallel. Even without division labor, automatic encapsulation, which results from proper model design, limits scope specific parameters that model. design model never needs repeated used over over. overall design test bench also fairly straightforward since mirrors actual system design. control mechanism derived from actual system, case model example. greatest benefit comes from being able manipulate system from higher level abstraction than would otherwise possible. This makes very easy design simulation validate function.
Behavioral Modelling VHDL Simulations
Flexibility
Flexibility, which factor ease use, immediate benefit using functional models simulation. Models exchanged other models design changes. Models automatically decoupled, changes model affect other models. test scenarios added inserted easily because tests were specified high level abstraction.
Reusability
While reusability important consideration some others when initially choosing methodology, should overlooked. Design reuse become major methods proposed close design productivity gap. survey current literature will show plethora articles dealing with design reuse, intellectual property cores virtual socket interface (VSI). company develop intellectual property pre-validated library behavioral models commonly used components. These components general purpose reused just same hardware components used multiple designs. ultimate reuse flexibility could result from generating behavioral models object-oriented language like C++. Then, addition other benefits behavioral models, these objects could inherit characteristics according rules classes inheritance chosen language.
Summary
Building functional models create "virtual system" simulating programmable logic design allows engineer more efficient. Allowing focus higher levels issue, this techniques also yields much more flexible designs that easily validated, modified reused. features VHDL support these needs with robust modeling programming features.
References
Printed References
1076-1993 IEEE Standard VHDL Language Reference Manual, IEEE Press, 1993 VHDL Made Easy!, David Pellerin Douglas Taylor, Prentice Hall, 1997 Great overview with healthy treatment VHDL test benches Includes code parsing engine CDROM VHDL Reference Guide, Eamonn Quigley, Esperan Ltd. 1995 Ultra handy pocket guide
References
comp.lang.vhdl list Includes kinds useful information IEEE VHDL Interactive Tutorial Demo code models test benches this project
Trademarks Copyright 1999 Lattice Semiconductor Corporation. rights reserved. Vantis, Vantis logo combinations thereof, trademarks, MACH registered trademark Lattice Semicondcutor Corporation. Other product names used this publication identification purposes only trademarks their respective companies.
Behavioral Modelling VHDL Simulations

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