CUSB2 Device Controller Core Control endpoint fixed Bytes si

The Datasheet Archive - 100 Million Datasheets from 7500 Manufacturers.

CUSB2 Device Controller Core Control endpoint fixed Bytes si

Datasheet Thumbnail

Top Searches for this datasheet

Full compliance with specification
CUSB2
Device Controller Core
Control endpoint fixed Bytes size Configurable endpoints Configurable/programmable number size endpoints Configurable/programmable single, double, triple quad buffering
CUSB2 core implements complete high/full-speed (480/12 Mbps) peripheral controller that interfaces UTMI port transceiver side system's microprocessor other. user-configurable endpoints, includes power management remote wake-up functions. integrated configuration/enumeration support Philips ISP1501 transceiver options. Developed easy reuse, CUSB2 available optimized several Lattice devices, with competitive utilization performance characteristics.
Programmable type endpoints UTMI Transceiver Macrocell Interface Configurable 16-, 32-bit microprocessor interface Easy integration with wide range microprocessors architectures Interrupt request signals application microprocessor Interrupt vector autovectored interrupts Direct access endpoints buffers configurable 16-, 32-bit Slave FIFO interface Ready external module Synchronous interface FIFOs Suspend resume power management functions Remote Wake-Up function Optional configuration/Enumeration added before delivery Support standard requests (described Chapter Specification) Interface asynchronous with function descriptors Optional support Philips ISP1501 USB2.0 Transceiver added before delivery
Applications
Embedded microcontroller systems Communication systems
Block Diagram
July 2003
Symbol Diagram
Options Modifications
options available upon request before delivery. optional configuration/enumeration (finite state machine) available handle standard requests, relieving host processor from servicing control transfers. Support Philips ISP1501 transceiver also available.
Support
core delivered warranted against defects year from purchase. Thirty days phone email technical support included, starting with first interaction. Additional maintenance support options available.
Verification
core been verified through extensive simulation rigorous code coverage measurements.
Deliverables
core includes everything required successful implementation:
Implementation Results
following typical performance utilization results using Lattice ispXPGAdevice. (This minimum configuration includes endpoint.)
Lattice Device LFX500C-4 LUT4s 4694 Registers 1101 PFUs 1236 SysMEM EBRs External I/Os Speed (fmax, MHz) 29.7
Post-synthesis EDIF netlist (firm core) optimized specific Lattice device (HDL source code (soft core) also available) Sample wrapper Texas Instruments 16550 pincompatible replacement Testbenches (self-checking) Simulation script, vectors, expected results Synthesis (soft) place route (firm) script Comprehensive user documentation
CAST, Inc. Stonewall Court Woodcliff Lake, 076747 201-391-8300 201-391-8694 Copyright CAST, Inc. 2003, Rights Reserved. Contents subject change without notice. July 2003
http://www.latticesemi.com

CUSB2 Device Controller Core Control endpoint fixed Bytes si

Top Searches for this datasheet

Other recent searches