Lattice leading supplier In-System Programmable (ISPTM) devices device
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Introduction Boundary Scan Test In-System Programming
Lattice leading supplier In-System Programmable (ISPTM) devices devices that fully compliant with IEEE-1149.1 testability standard. Lattice product offering includes many devices that incorporate in-system programmability through 1149.1 compliant test access port (TAP). ispLSI® 1000EA, 2000VE, 2000VL, 5000V, 8000/V, ispMACH4A, 4000B/C, 5000VG, MACH® ispGDXV ispGDX® device families implement 1149.1 testability fully compliant with 1149.1 standard. ispLSI 2000E, 2000V, ispGAL®22LV10, MACH 1SP, ispPAC® device families offer in-system programmability, include 1149.1 boundary scan registers therefore considered 1149.1 compatible rather than compliant. In-system programming developed simplify programmable devices packaged fine pitch packaging (e.g. PQFP, TQFP BGA). manufacturing flow that doesn't take advantage devices requires additional handling, increasing probability that delicate leads will damaged decreasing overall manufacturing yield. Over past several years, devices increased devices programmed in-system. There very limitations placed type system used execute device algorithm. Today, most programmable logic companies offer programming solutions that range from programming single device through simple cable attached computer, programming multiple devices from different vendors part board test program. Embedded programming, ability program devices using microprocessor same board devices being programmed, also readily available gives users ability update programming device field.
Benefits Through JTAG
In-system programming using standard boundary scan test interface necessary compatibility with advanced board testing techniques. IEEE 1149.1 boundary scan test interface standard, sponsored Joint Test Action Group (JTAG), developed test printed circuit board connections. standard been commonly referred JTAG. standard also allows in-system programmable CPLDs programmed through same interface used test. 1149.1 standard defines simple, serial interface that allows program test multiple devices using basic desktop tools. design incorporates 1149.1-ISP devices, then separate programming interface needed. IEEE-1149.1 compatible compliant devices (logic, interconnect analog) used same scan chain. devices make design jobs easier simplifying device configuration. Designers have option soldering parts directly board then programming them through pins. design phase, devices designers implement redesigns within seconds making changes directly devices board. This speeds design process reduces time market. devices also offer benefits manufacturing. Lower inventory cost achieved because blank devices used manufacturing then programmed test time. This eliminates need maintain separate inventory part number each programmed part improves manufacturing process facilitating board connectivity testing. Once design finalized board assembled, manufacturing engineers testers both board connectivity testing programming. result, 1149.1-ISP eliminates cost separate programming stations, unnecessary manufacturing steps excessive handling. This shortens production time, reduces scrap cost increases reliability.
IEEE 1532 Programming Standard
IEEE 1532 refers industry standardization effort aimed simplifying challenge programming In-System Configurable (ISC) devices using industry standard IEEE 1149.1 Boundary Scan Test Access Port. IEEE 1532 effort focused standardization programming algorithm component level (silicon) www.latticesemi.com
bstisp_05
Lattice Semiconductor
Introduction Boundary Scan Test In-SystemProgramming
well definition software required describe programming algorithm associated programming data. silicon portion standard establishes common device behavior during programming IEEE 1149.1 state machine. device which claims compatibility compliance with this standard will behave predictably consistently when given instruction. software portion IEEE 1532 standard defines modified Boundary Scan Description Language file (ISC BSDL file) which been expanded cover instructions. Additionally, there data file (ISC data file) which contains device pattern-specific programming data.
History 1149.1 Standard
years, many companies have used proprietary test methodologies implemented with boundary scan registers reduce test complexity board system level. late 1980s, group European companies formed group with purpose standardizing method implementing performing boundary scan testability. composition this group included representatives from board-test companies, system design companies semiconductor manufacturers. year after this group formed, additional companies from both Asia United States joined this group continued work standard voted IEEE. 1990, this standard passed standard IEEE 1149.1-1990. This standard included definition Test Access Port (TAP), group both mandatory optional test registers, control mechanism timing both registers TAP, both mandatory optional test instructions. 1993, corrections additions were made standard, including language that used describe implementation given device. This language, called Boundary Scan Definition Language (BSDL), subset VHDL (another IEEE standard). 1149.1 working group continues meet regular basis constantly works improve standard.
What IEEE-1149.1?
simplest form, 1149.1 standard implemented using four-pin, dedicated test access port, 16-state, synchronous state machine group data registers. data registers include bypass register boundary scan register that used control inputs outputs device being tested. also needs instruction register instruction register decoder used control data registers. Figure shows top-level diagram basic implementation 1149.1 standard. Figure IEEE 1149.1 Block Diagram
Controller Data Registers Test Logic Instruction Register Instruction Register Decoder
System Device Logic
There four pins that make Test Access Port (TAP): (Test Data Input), (Test Mode Select), (Test Clock), (Test Data Output). additional defined standard, TRST (Test ReSeT), used asynchronously reset both controller instruction register. registers, along with controller, clocked using pin.
Lattice Semiconductor
Introduction Boundary Scan Test In-SystemProgramming
Boundary Scan Controller
Controller synchronous, finite state machine that controls both instruction various data registers. controls whether device reset mode, where core logic full control device, receiving instruction, receiving and/or transmitting data, idle state. state machine, illustrated Figure controlled clocked TCK. value located next each transition Figure
Boundary Scan Test Instructions
While controller heart 1149.1 implementation, instruction register instruction register decoder thought brains. instruction register stores information concerning which test register test circuitry active. instruction code selected, associated register and/or test circuit also selected. This requirements stated 1149.1 standard. Instructions shifted into instruction register when controller SHIFT-IR state become active when controller enters UDPATE-IR state. Figure Controller
Test-Logic-Reset Run-Test/Idle
Select-DR-Scan Capture-DR Shift-DR Exit1-DR Pause-DR Exit2-DR Update-DR
Select-IR-Scan Capture-IR Shift-IR Exit1-IR Pause-IR Exit2-IR Update-IR
Table shows boundary scan test instructions supported Lattice device families that IEEE 1149.1 controller state machine programming. Only ispLSI 2000E, 2000V, ispPAC ispGAL22LV10 device families have boundary scan registers support test. above instructions have unique, 8-bit code that shifted into instruction register. exception this BYPASS instruction that will turn whenever code selected when invalid code selected. Individual test instrution codes found device BSDL file. Lattice ispLSI 1000EA, 2000VE/VL, 5000V, 8000, ispMACH 4000B/C, 5000VG, MACH ispGDX ispGDXV devices support three mandatory instructions defined boundary scan definition: SAMPLE/ PRELOAD, EXTEST BYPASS. following paragraphs describe each these instructions. shift register defined within devices implement instruction shift register. devices that support boundary scan test, loading SAMPLE/PRELOAD EXTEST instructions results BYPASS function.
Lattice Semiconductor
Introduction Boundary Scan Test In-SystemProgramming
Table Summary Boundary Scan Test Instruction Support
ispMACH 4A/MACH ispMACH 4000B/C
ispMACH 5000VG
ispGDXV
MACH
ispGAL22LV10
ispLSI 1000EA
ispLSI 2000VE
ispLSI 2000VL
Required
ispLSI 8000/V
ispLSI 2000E
ispLSI 2000V
ispLSI 5000V
Optional
ispGDX
Boundary Scan Test Instruction BYPASS EXTEST SAMPLE HIGHZ IDCODE USERCODE Instruction Register Length
SAMPLE/PRELOAD instruction used take snapshot device normal functional operation. This instruction does interfere with normal operation device. SAMPLE part this instruction occurs during Capture-DR. loaded with state pins rising edge while Capture-DR. then shifted examination. PRELOAD part this instruction simply loading during Shift-DR. typically used before EXTEST instruction define initial state pins. EXTEST instruction drives external pins with values present Functional logic interrupted while running this instruction. This instruction used test external devices board-level connections. values pins loaded rising edge while Capture-DR. values shifted into during Shift-DR. values latched pins during Update-DR. BYPASS instruction used bypass device that accessed during part test. definition BYPASS instruction allows driven during Shift-IR. order shift correct instruction code, internal pull-up drive logic high. bypassed boundary scan device single bypass register between while Shift-DR. optional instructions, HIGHZ, IDCODE USERCODE, supported some Lattice devices. devices that support these instructions, loading them results BYPASS function. following paragraphs discuss these instructions more detail. HIGHZ instruction used disable functional pins. pins tri-state rising edge Update-IR with HIGHZ loaded. BYPASS register selected Shift-DR when this instruction loaded. pins re-enabled rising edge Update-IR with other standard boundary scan test instruction loaded. IDCODE instruction gives access hard-wired 32-bit boundary scan IDCODE. There ways access IDCODE register, state instruction. IEEE 1149.1, moving directly from Test-LogicReset Shift-DR will select IDCODE register. addition, loading IDCODE instruction Shift-IR will select IDCODE register Shift-DR. IDCODEs found individual device BSDL file. USERCODE instruction gives access user programmable 32-bit boundary scan USERCODE. USERCODE proven useful version control, especially with embedded applications. user program version number into USERCODE register. power on-board processor control unit verify that version correct USERCODE register. Since USERCODE read while device functional, interruption functional logic necessary.
ispPAC
Lattice Semiconductor
Introduction Boundary Scan Test In-SystemProgramming
BSDL Support Files
Boundary Scan Description Language (BSDL) files used describe individual device's boundary scan hardware configuration. Each BSDL file shows instructions supported different data shift registers lengths configurations. Individual BSDL files found Lattice site www.latticesemi.com.
Data Registers
data registers have been defined 1149.1 standard considered requirement. These BYPASS register boundary scan register (BSR). BYPASS register single-bit register used shift data from without affecting other circuitry. Figure illustrates BYPASS register. Figure BYPASS Register
BYPASS
boundary scan register (BSR) used capture send data from input pins. Each boundary scan register composed registers. first used either capture data from shift data into from TAP. second used drive data from first register onto input pin. Figure shows structure typical BSR. Figure Boundary Scan Register
Next
Input From Previous UPDATE-DR
Output
common boundary scan register implementation uses three boundary scan control registers attached first input, second output third output enable signal. looking these three registers, test software determine what happening particular I/O. output enable then will match value output cell. output enable `0,' configured input with value data input BSR. input clock would only have single would have output tied
Lattice Semiconductor
Introduction Boundary Scan Test In-SystemProgramming
anything, used observation only. Figure shows configurations this implementation both input pin. Figure Common Configurations Inputs I/Os
Next Cell Next Cell System Logic Macrocell
From Next Cell
device considered 1149.1 compliant, must have TAP, controller, boundary register instructions BYPASS, SAMPLE EXTEST. device that only controller compatible with 1149.1 standard work scan chain, will considered compliant. device that does have boundary scan register cannot tested using because there means controlling accessing input pins other than direct connection. ispLSI 1000EA, 2000VE, 5000V, 8000/ ispMACH 4000B/C, 5000VG, MACH ispGDX/V families compliant with 1149.1 standard while ispLSI 2000E, 2000V, ispGAL22LV10 ispPAC families compatible with
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