High-performance 32-bit Instruction Thumb® High-code-density 16-bit In
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Based ARM® SC100SecurCore32-bit RISC Processor Instruction Sets
High-performance 32-bit Instruction Thumb® High-code-density 16-bit Instruction 4-Gbyte Linear Address Space Neumann Load/Store Architecture Single 32-bit Data Instructions Data 3-stage Pipeline Architecture Fetch, Decode Execute Stages 8-bit, 16-bit, 32-bit Data Types On-chip Programmable System Clock Very Power Consumption: Industry Leader MIPS/Watt Low-power Idle Power-down Modes Bond Locations Conforming 7816-2 Protection 6000V Operating Ranges: 2.7V 5.5V, GSM/3G Compliant, Industry Compatible,
32-bit Secure Microcontroller Smart Cards
AT91SC25672RC
Memory
256K Bytes Program Memory Bytes EEPROM User Memory, Including Bytes
Typically More than 500,000 Write/Erase Cycles
Summary
Bytes
Peripherals
Ports
Configurable Support Communication Protocols, Including 7816-3 2-wire Protocols 7816 Controller kbps Serial Peripheral Interface (SPI) Controller MHz) 16-bit Timers Random Number Generator (RNG) 2-level, 12-vector Interrupt Controller Hardware Triple Checksum Accelerator Engine 32-bit Cryptographic Accelerator Public Operations Including GF(2N) RSA, DSA, ECC, Diffie-Hellman Advanced High-performance Hardware Java Card Accelerator
Security
Dedicated Hardware Protection Against SPA/DPA Attacks Advanced Protection Against Physical Attack Environmental Protection Systems Voltage Frequency Monitors Secure Memory Management/Access Protection
Development Tools
Hardware Development Support ATV3-91SC Voyager Emulation Platform.
ATV3-91SC Emulator Product Preview Further Details.
Rev. 1575CS-SMIC-09/03
Note: This summary document. complete document available under NDA. more information, please contact your local Atmel sales office.
Description
AT91SC25672RC low-power, high-performance, 32-bit RISC microcontroller with program memory, EEPROM data memory, cryptographic accelerator, based SC100 advanced secure processor. SC100 embedded core first member SecurCore family. This general-purpose 32-bit processor offers high performance, very power consumption, additional features help combat fraud. AT91SC25672RC features bytes high-performance EEPROM (fast erase/write time, high endurance). This allows system developers offer their customers true bytes EEPROM, while still being able remaining bytes their purposes (e.g. customization patches). cryptographic accelerator featured AT91SC series AdvXTM. based 32-bit multiplier-accumulator architecture which designed perform fast encryption authentication functions. This enables fast computation low-power operation. AdvX, conjunction with controlling firmware running within SC100 core, supports standard finite fields arithmetic functions (including RSA, DSA, ECC) GF(2N). MPU, real hardware firewall used increase overall security level application without intense software development. Unique hardware features significantly accelerate execution Java Card Byte Code removing common software bottlenecks encountered during implementation Java Virtual Machine. Additional security features include power frequency protection logic, logical scrambling program data addresses, power analysis countermeasures memory accesses controlled supervisor mode.
Configuration
AT91SC25672RC pinout conforms 7816-2 interface. also provides second port. I/O0 I/O1 MOSI MISO
Note:
Ground (reference voltage) Power supply input Input output serial data Second input output serial data Also used Slave Select line controller Master output Slave input Master input Slave output Clock Clock signal input internal clock operating circuit Reset signal input, state stops core
convention, corresponds signal 7816-3 Protocol. Both active low.
AT91SC25672RC
1575CS-SMIC-09/03
AT91SC25672RC
Architectural Overview
SC100 3-stage pipeline, 32-bit RISC processor. uses Neumann load/store architecture, which characterized single data address instructions data. SC100 processor employs unique architectural strategy known Thumb®, super-reduced instruction that ideally suited high-volume applications with memory restrictions, applications where code density important factor. Essentially, SC100 processor instruction sets: standard instruction uses 32-bit instructions offers maximum performance. Thumb instruction uses 16-bit instructions offers maximum code density.
Both instruction sets operate 8-bit, 16-bit, 32-bit data types. 16-bit instruction length allows achieve almost twice density standard code, while retaining most performance advantage over traditional 16-bit processor using 16-bit registers. This possible because 16-bit Thumb instructions operate same 32-bit register 32-bit instructions. Thumb code smaller than equivalent code, while providing 160% performance equivalent processor connected 16bit memory system. Figure Block Diagram
EEPROM User Memory
Program Memory
Java Accelerator
AdvX CryptoAccelerator
Secure Control
Reset Circuit
DES/3DES
Firewall
On-chip Security (SPA, DPA,
SC100 Core
Checksum Accelerator
7816 Controller
7816 Port
I/O0
Thumb Instruction Decompressor
7816 Port
I/O1
Controller
Pipeline
MOSI MISO
Timer
1575CS-SMIC-09/03
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Atmel Corporation 2003. Atmel Corporation makes warranty products, other than those expressly contained Company's standard warranty which detailed Atmel's Terms Conditions located Company's site. Company assumes responsibility errors which appear this document, reserves right change devices specifications detailed herein time without notice, does make commitment update information contained herein. licenses patents other intellectual property Atmel granted Company connection with sale Atmel products, expressly implication. Atmel's products authorized critical components life support devices systems. ATMEL registered trademark Atmel; AdvX trademark Atmel. Thumb Powered registered trademarks Ltd. SC100and SecurCore trademarks Ltd. Other terms product names trademarks others.
Printed recycled paper.
1575CS-SMIC-09/03
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