Powerful Instructions (Most Executed Single Clock Cycle) Low-power Idl

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Powerful Instructions (Most Executed Single Clock Cycle) Low-power Idl

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High-performance, Low-power secureAVREnhanced RISC Architecture
Powerful Instructions (Most Executed Single Clock Cycle) Low-power Idle Power-down Modes Bond Locations Conforming 7816-2 Protection 6000V Operating Range: from 2.7V 5.5V Compliant with GSM, 3GPP 2000 Specifications; Industry Compatible Available Wafers, Modules Industry-standard Packages
Memory
Bytes Program Memory Bytes EEPROM, Including Bytes 384-byte Bit-addressable Bytes
128-byte Program/Erase Program, Erase Typically More than 500,000 Write/Erase Cycles Temperature 25oC Years Data Retention EEPROM Erase Only Mode Write EEPROM With Without Autoerase Bytes
Secure Microcontroller Smart Cards
AT90SC9636R
Summary
Peripherals
7816 Controller
kbps Compliant with Protocols Port Programmable Internal Oscillator ROM) 16-bit Timers Random Number Generator (RNG) 2-level, 7-vector Interrupt Controller Hardware Triple Resistant Checksum Accelerator Engine (Compliant with ISO/IEC 3309)
Security
Dedicated Hardware Protection Against SPA/DPA Attacks Advanced Protection Against Physical Attack Environmental Protection Systems Voltage Monitor Frequency Monitor Light Protection Secure Memory Management/Access Protection (Supervisor Mode)
Development Tools
Voyager Emulation Platform (ATV2 Advanced) Support Software Development Systems C-Spy Debugger Atmel's Studio Version 4.07 Above Software Libraries Application Notes
Rev. 1589AS-SMIC-06/03
Note: This summary document. complete document available under NDA. more information, please contact your local Atmel sales office.
Description
AT90SC9636R low-power, high-performance, 8/16-bit microcontroller with program memory, EEPROM data memory, based secureAVR enhanced RISC architecture. executing powerful instructions single clock cycle, AT90SC9636R achieves throughputs close MIPS MHz. Harvard architecture includes general-purpose working registers directly connected ALU, allowing independent registers accessed single instruction executed clock cycle. AT90SC9636R uses architecture, secureAVR that allows linear addressing bytes code bytes data well number functional security features. ability EEPROM code space allows parts program memory reprogrammed in-system. This technology combined with versatile 8/16-bit monolithic chip provides highly flexible cost-effective solution many smart card applications. Additional security features include power frequency protection logic, logical scrambling program data addresses, Power Analysis countermeasures memory accesses controlled supervisor mode. block diagram AT90SC9636R shown Figure Figure AT90SC9636R secureAVR Enhanced RISC Architecture
Data 8-bit EEPROM User Memory Program Memory Instruction Register Instruction Decoder Control Lines Status Register Timer Reset Circuit Counter Measures Checksum Accelerator General Purpose Registers
Access Control
Secure Control
Access Control
Data Memory Interrupt Unit 7816 Controller 7816 Port
IN/OUT0
AT90SC9636R
1589AS-SMIC-10Jun03
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Atmel Corporation 2003. Atmel Corporation makes warranty products, other than those expressly contained Company's standard warranty which detailed Atmel's Terms Conditions located Company's site. Company assumes responsibility errors which appear this document, reserves right change devices specifications detailed herein time without notice, does make commitment update information contained herein. licenses patents other intellectual property Atmel granted Company connection with sale Atmel products, expressly implication. Atmel's products authorized critical components life support devices systems. ATMEL registered trademark Atmel; AVRis trademark Atmel. C-Spy registered trademark Systems Other terms product names trademark others. Printed recycled paper.
1589AS-SMIC-10Jun03

Powerful Instructions (Most Executed Single Clock Cycle) Low-power Idl

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