Powerful Instructions (Most Executed Single Clock Cycle) Low-power Idl

The Datasheet Archive - 100 Million Datasheets from 7500 Manufacturers.

Powerful Instructions (Most Executed Single Clock Cycle) Low-power Idl

Datasheet Thumbnail

Top Searches for this datasheet

High-performance, Low-power AVR® (AVR3 Core) Enhanced RISC Architecture
Powerful Instructions (Most Executed Single Clock Cycle) Low-power Idle Power-down Modes Bond Locations Conforming 7816-2 Protection 6000V Operating Ranges: Mode: 2.7V 5.5V; Industry Compliant Mode: 3.6V 5.5V; Compliant with Specification V1.1 Available Wafers, Modules Industry-standard Packages
Secure Microcontroller
AT90SC6464C-USB Summary
Memory
Bytes EEPROM, Including 64-byte Area 64-byte Bit-addressable Area
128-byte Program/Erase Program, Erase Typically More than 500,000 Write/Erase Cycles Years Data Retention Bytes Flash Program Memory 128-byte Page Programming Minimum 10,000 Write/Erase Cycles Years Data Retention Bytes
Peripherals
Ports (Configurable Support Communication Protocols Including 7816-3
2-wire Interfaces)
Interface Endpoints)
V1.1 Full-speed Mbps) Certified, Suspend/Resume Modes Supported Configurable Endpoints Addition Endpoint Endpoints with Double-buffering Capability (Ping-pong Mode) Dynamic Pull-up Attachment Controller Automatic USB/ISO Interface Detection Circuitry 16-bit Timers Random Number Generator (FIPS 140-1) 2-level, 8-vector Interrupt Controller Hardware Triple Resistant Checksum Accelerator Crypto-coprocessor Pre-programmed Functions Cryptography Authentication Including RSA, DSA, Generation,
Security
Dedicated Hardware Protection Against SPA/DPA Attacks Advanced Protection Against Physical Attack Environmental Protection Systems Voltage Frequency Monitors Secure Memory Management/Access Protection (Supervisor Mode)
Development Tools
Hardware Development Support Voyager Emulation Platform (ATV1)
Rev. 1559BS-8/02
Note: This summary document. complete document available under NDA. more information, please contact your local Atmel sales office.
Description
AT90SC6464C-USB low-power, high-performance, 8-bit microcontroller, based AVR3 enhanced RISC architecture, featuring Flash program memory, EEPROM data memory 16-bit crypto-coprocessor dedicated performing fast encryption authentication functions. AVR3 core allows linear addressing bytes code bytes data, provides number functional security features. This core executes powerful instructions single clock cycle, allows AT90SC6464C-USB achieve throughputs close MIPS MHz. Harvard architecture includes generalpurpose working registers directly connected ALU, allowing independent registers accessed single instruction executed clock cycle. AT90SC6464C-USB includes 128K bytes Atmel's high density, nonvolatile memory. on-chip downloadable Flash allows program memory reprogrammed in-system. This technology combined with versatile 8-bit monolithic chip provides highly flexible cost-effective solution many smart card applications. Additional security features include power frequency protection logic, logical scrambling program data addresses, Power Analysis countermeasures memory accesses controlled supervisor mode.
Configuration
AT90SC6464C-USB pinout conforms 7816-2 Full-speed V1.1 Interface specifications (the interface requires addition external clock signal crystal). second port also provided,.
7816-2 Interface (VBUS) IN/OUT0 (CLKEN) IN/OUT1 USBDM USBDP XOUT Note: Ground (reference voltage) Power supply input serial data Second serial data Clock signal input internal clock operating circuit Reset signal input state stops core) Interface with External Clock Ground (reference voltage) Power supply input (bus-powered device) Active signal disable/enable clock signal source Second serial data Clock signal input internal clock operating circuit MHz) Reset signal input state stops core) differential data differential data Interface with Crystal Ground (reference voltage) Power supply input (bus-powered device) serial data Second serial data Reset signal input state stops core) differential data differential data Crystal signal input drive internal clock operating circuit Crystal signal output drive internal clock operating circuit
convention corresponds Interface protocol. cases, however, remains active low.
Architectural Overview
AT90SC6464C-USB based (core enhanced RISC architecture (see Figure fast-access register file contains 8-bit general-purpose working registers, each which accessed single clock cycle. Furthermore, high-performance (Arithmetic Logic Unit) operates directly generalpurpose working registers. This allows processor execute complete operation single clock cycle-two operands output from register file, operation executed, result stored back register file, same clock cycle. operations divided into three main categories: arithmetic, logical bit-functions.
AT90SC6464C-USB
1559BS-8/02
AT90SC6464C-USB
general-purpose registers used three 16-bit indirect address register pointers addressing data space allowing efficient address calculations. AT90SC6464C-USB more than bytes data space address, registers RAMPX, RAMPY RAMPZ concatenated with registers respectively indirect addressing. RAMPD concatenated with part instruction word enable direct addressing bytes data (using STS). EIND concatenated with register enable extended indirect jumps calls words code (using EIJMP EICALL). Figure AT90SC6464C-USB Enhanced RISC Architecture
Data 8-bit EEPROM User Memory FLASH Program Memory Instruction Register Instruction Decoder Control Lines Status Register 7816 Port 7816 Port Timer Timer Counter measures Checksum Accelerator
IN/OUT0 (CLKEN)
Module
USBDM USBDP
Access Control
Secure Control CryptoCoprocessor
(VBUS) XOUT
General Purpose Registers
Access Control
Data Memory Interrupt Unit
IN/OUT1
Reset Circuit
performs arithmetic logical operations contents single registers, pairs registers between registers constant values. Conventional memory addressing modes used access register file, these registers assigned lowermost data space addresses. memory space contains addresses peripheral functions such control registers, timer/counters, internal external interrupts, serial pins, other functions. memory space accessed directly, data space locations. hundred sixty additional peripherals registers available. AVR3 core uses Harvard architecture, with separate address spaces program memory data memory. Different addresses used same memory block used program data. FLASH program memory accessed with single level pipelining; while instruction being executed, next instruction pre-fetched from program memory. This mechanism allows each instruction executed single clock cycle. EEPROM includes bytes bit-addressable memory bytes (One Time Programmable) memory. 22-bit Program Counter (PC) AT90SC6464C-USB address words bytes) program memory. Most instructions have single 16-bit word format. Every program memory address contains 16-bit 32-bit instruction. bytes data accessed easily through five different addressing modes supported architecture.
1559BS-8/02
flexible interrupt controller control registers space with additional global interrupt enable status register. Each interrupts separate interrupt vector interrupt vector table beginning program memory. different interrupts prioritized according their programmed priority level. When interrupts with same priority detected same time, interrupt with lower source number serviced first.
Module Functional Description
Hardware Block
interface consists Serial Interface Engine (SIE) Universal Function Interface (UFI). performs clock/data separation, NRZI encoding decoding, stuffing, generation checking, serial-parallel data conversion. connects interface AVR. consists protocol engine provides four configurable data transfer endpoints, each with DPRAM memory area. data transfer type each endpoint configured software. table below indicates size each endpoint.
Endpoint number (Ping-pong) (Ping-pong) Note: Size bytes) Recommended data transfer type CONTROL (mandatory) BULK BULK BULK, INTERRUPT, CONTROL, ISOCHRONOUS
Ping-pong (double-buffering) mode special proprietary feature, transparent user, that allows software read data from bank while hardware fills another bank, thereby saving processing transaction time.
controller manages device addresses, monitors status transaction, manages DPRAMs communicates with through status control registers, registers.
Software Block
function controller must implemented firmware microcontroller. This software must comply with Chapter specifications V1.1. Enumerating executing functions should done using interrupts (polling possible more complicated manage).
Atmel Corporation 2001. Atmel Corporation makes warranty products, other than those expressly contained Company's standard warranty which detailed Atmel's Terms Conditions located Company's site. Company assumes responsibility errors which appear this document, reserves right change devices specifications detailed herein time without notice, does make commitment update information contained herein. licenses patents other intellectual property Atmel granted Company connection with sale Atmel products, expressly implication. Atmel's products authorized critical components life support devices systems. Corporate Headquarters, 2325 Orchard Parkway, Jose, 95131, (408) 441-0311, (408) 487-2600 Atmel Colorado Springs, 1150 Cheyenne Mtn. Blvd., Colorado Springs, 80906, (719) 576-3300, (719) 540-1759 Atmel Grenoble, Avenue Rochepleine, 123, 38521 Saint-Egreve Cedex, France, (33) 4-7658-3000, (33) 4-7658-3480 Atmel Heilbronn, Theresienstrasse 3535, D-74025 Heilbronn, Germany, (49) (49) Atmel Nantes, Chantrerie, 70602, 44306 Nantes Cedex France, (33) (33) Atmel Rousset, Zone Industrielle, 13106 Rousset Cedex, France, (33) 4-4253-6000, (33) 4-4253-6001 Atmel Smart Card ICs, Scottish Enterprise Technology Park, East Kilbride, Scotland 0QR, (44) 1355-357-000, (44) 1355-242-743
ATMEL registered trademarks Atmel Corporation. Other terms product names trademark others. Printed recycled paper.
1559BS-8/02

Powerful Instructions (Most Executed Single Clock Cycle) Low-power Idl

Top Searches for this datasheet

Other recent searches