Dual 6-bit Gsps Converter AT76CL610 Preliminary Specification App

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Dual 6-bit Gsps Converter AT76CL610 Preliminary Specification App

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Dual 6-bit Resolution Full-power Input Bandwidth Band Flatness (±0.5 from Gsps Sampling Rate SINAD (5.7 ENOB) SFDR Gsps, MHz, (SFSR -0.5dB 2-tone IMD: Gsps, MHz, 0.35 Typ, Channel-to-channel Input Offset Error: Max, Gain Matching (Channel-to-channel): ±0.25 Max, Phase Matching (Channel-to-channel): Max, Channel-to-channel Mean Difference Error: (rms) Channel-to-channel Difference Error: Error Rate (10-9) Gsps Very Input Capacitance: mVPP Differential Single Analog Inputs Differential Single-ended PECL-compatible Clock Inputs LVDS Output Compatibility (100) Data Output Demultiplexer Power Consumption: VCCA VCCD 3.15V/VCCO 2.25V Power Supply: 3.15V (Analog), 3.15V (Digital), 2.25V (Output) Available 80-lead TQFP Package Temperature Range: Industrial -20°C 85°C, Commercial 70°C
Dual 6-bit Gsps Converter AT76CL610 Preliminary Specification
Applications
Satellite Receiver Direct Down-conversion Test Instrumentation WLAN
more information,
Description
AT76CL610 monolithic dual 6-bit analog-to-digital converter, designed digitizing in-phase quadrature wide bandwidth analog signals very high sampling rates Gsps (giga-samples second). ability directly interface signals makes AT76CL610 ideal applications such direct satellite demodulation. AT76CL610 uses innovative architecture fabricated with advanced high-speed BiCMOS process. on-chip cores have closely matched full-power input bandwidth, providing excellent dynamic performance undersampling applications (high digitizing). samples from each converter de-multiplexed ratio output data stream LVDS-compliant.
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Rev. 2158A-BDC-04/03
Figure AT76CL610 Symbol
VCCA VCCD VCCO
VINI VINIB VINQ VINQB AT76CL610
DOAI0:DOAI5 DOAI0N:DOAI5N DOBI0:DOBI5 DOBI0N:DOBI5N DOAQ0:DOAQ5 DOAQ0N:DOAQ5N DOBQ0:DOBQ5 DOBQ0N:DOBQ5N DOIR, DOIRN CLKO CLKOB
CLKB
GNDA
GNDD
GNDO
Table Signal Description
Signal Name VCCA VCCD VCCO GNDA GNDD GNDO VINI, VINIB VINQ, VINQB CLK, CLKB CLKO, CLKOB DOAI0:DOAI5; DOAI0N:DOAI5N DOBI0:DOBI5; DOBI0N:DOBI5N DOAQ0:DOAQ5; DOAQ0N:DOAQ5N DOBQ0:DOBQ5; DOBQ0N:DOBQ5N DOIR, DOIRN Function Positive analog power supply Positive digital power supply Positive output power supply Analog ground Digital ground Output ground Differential analog inputs Differential analog inputs Differential clock inputs Differential clock outputs Differential output data port Channel Differential output data port Channel Combined output range data Direction
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AT76CL610
Table Digital Output Coding
Differential Single Analog Input +406 +406 +393 +206 +193 +6.25 -6.25 -206 -193 -393 -406 <-406 Voltage Level Positive full scale Positive full scale Positive full scale Positive scale Positive scale Bipolar zero Bipolar zero Negative scale Negative scale Negative full scale Negative full scale Negative full scale Digital Output Binary 111111 111111 111111 110000 101111 100000 011111 010000 001111 000000 000000 000000 Range
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Figure AT76CL610 Simplified Block Diagram
Clock Buffer CLKB
Divider
LVDS Clock Buffer
CLKO, CLKON
0.62 VCCA VINI VINIB DoirI 0.62 VCCA 0.62 VCCA DoirQ 6-bit LVDS DoirI DoirQ LVDS Range Buffer 6-bit LVDS DOAI, DOAIN DOBI, DOBIN
DOIR, DOIRN
VINQ VINQB 0.62 VCCA
DOAQ, DOAQN
DOBQ, DOBQN
Functional Description
AT76CL610 dual 6-bit, Gsps based advanced high-speed BiCMOS technology. Each 6-bit Flash-like core architecture. output data followed demultiplexer LVDS output buffer (100). common over-range combiner (DOIR DOIRI DOIRQ) provided external gain control adjustment. AT76CL610 works fully differential mode from analog inputs digital outputs. AT76CL610 features full-power input bandwidth MHz.
Application Scenario
Figure shows AT76CL610 integrated into typical application scenario digital signal reception demodulation.
AT76CL610
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AT76CL610
Figure Functional Application (Typical)
Satellite Noise Converter Bandpass Amplifier Parabolic Antenna 11.12 Synthesizer Bandpass Amplifier Pass Filter Tunable Band Filter Band Filter
Local Oscillator
Control Functions: Clock Carrier Recovery, Gain Adjustment. CLOCK Digital AT76CL610 Analog
In-phase Local Oscillator
Quadrature
DEMODULATION
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Electrical Characteristics
Table Absolute Maximum Ratings
Symbol VCCA VCCD Vcco DVCCA VCCO DVCCA VCCD DVCCD VCCO VINI VINIB VINQ VINQB VCLK VCLKB VCLK VCLKB TSTG TLEADS Notes: Parameter Analog positive supply voltage Digital positive supply voltage Output supply voltage Maximum difference between VCCA VCCO Maximum difference between VCCA VCCD Maximum difference between VCCD VCCO Differential analog input voltages Clock input voltage Maximum difference between VCLK VCLKB Maximum junction temperature Storage temperature Lead temperature (Soldering 10s) Value -0.3 VCCD +125 +150 +300 Unit
Absolute maximum ratings limiting values (referenced 0V), applied individually, while other parameters within specified operating conditions. Long exposure maximum ratings affect device reliability. Limiting values given accordance with Absolute Maximum Rating System (IEC 134). These stress ratings only operation device these other conditions above those given Electrical Characteristics sections specifications implied. Exposure limiting values extended periods affect device reliability.
Table Recommended Conditions
Symbol VCCA VCCD VCCO VINI VINIB VINQ VINQB VCLK VCLKB Parameter Analog supply voltage Digital supply voltage Output supply voltage Differential single analog input voltage (full scale) Clock input level differential Ambient temperature range 3.15 3.15 2.25 ("C" grade) ("V" grade) Unit mVPP mVPP
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AT76CL610
Operating Characteristics
following conditions apply electrical operating characteristics given Table test levels given Table page VCCA 3.15V, VCCD 3.15V, VCCO 2.25V, VINI VINIB VINQ VINQB mVPP -0.5 full scale differential input (digital outputs LVDS 100), clock duty cycle (typical) 25°C Table Electrical Operating Characteristics
Symbol Parameter Test Level Unit
Power Requirements VCCA VCCD VCCO ICCA ICCD ICCO PSRR Power supply voltage analog Power supply voltage digital Power supply voltage output digital (LVDS) Supply current analog Supply current digital Supply current output Nominal power dissipation Single channel power supply rejection ratio (VCCA) Resolution Analog Inputs VINI VINQ VINIB VINQB FPBW Full scale input voltage range (differential mode) 0.62 VCCA common mode voltage Full scale input voltage range (single mode) 0.62 VCCA common mode voltage Analog input capacitance Input resistance Full-power input bandwidth 3.15 3.15 2.25 bits
Clock Input Logic compatibility clock inputs -VILh Differential logic level Power level into termination Clock input power level CCLK Clock input capacitance PECL/ECL/LVDS into
Digital Outputs Logic compatibility digital outputs (depending value VCCO) Differential output voltages swings (assuming VCCO 2.25V VCCD 3.15V) Output Levels (Assuming VCCO 2.25V VCCD 3.15V) Differentially Terminated Logic voltage III, LVDS
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Table Electrical Operating Characteristics (Continued)
Symbol Parameter Logic voltage Output offset voltage (assuming VCCO 2.25V VCCD 3.15V) differentially terminated Change between Change between Output current (shorted output) Output current (grounded output) Output level drift with temperature Differential output amplitude drift with temperature Accuracy Single-ended clock duty cycle (CLK, CLKB); binary output data format. (typical) 25°C. Differential non-linearity Integral non-linearity missing codes Output offset code (single channel Input offset voltage (single channel Gain error drift against temperature Gain error drift against analog supply Input offset matching channel (static) Gain matching channel (static) Transient Performance error rate Gsps, Overvoltage recovery time 10-9 Error/ Sample 0.25 0.35 0.35 0.16 Test Level 1125 1200 1.47 1275 Allowed mV/°C mV/°C Unit
Guaranteed over specified temperature range 31.5 0.62 VCCA 0.25 mV/°C mV/V°
Performance Differential input clock mode; clock duty cycle (CLK, CLKB); 25°C, unless otherwise specified. Gsps, (single-ended input) SINAD Gsps, Gsps, Gsps, (single-ended input) ENOB Gsps, Gsps, 5.75 5.70 bits bits bits
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AT76CL610
Table Electrical Operating Characteristics (Continued)
Symbol Parameter Gsps, (single-ended input) Gsps, Gsps, Gsps, (single-ended input) SFDR Gsps, Gsps, Two-tone inter-modulation distortion (single channel) FIN1 MHz, FIN2 Gsps Gain flatness: ±0.5 Gain matching (Channel MHz, Phase matching (channel MHz, Crosstalk channel versus channel MHz, 0.25 <<52 Test Level Unit
Switching Performance Characteristics Figure page Jitter Tdclk Maximum clock frequency Minimum clock frequency Minimum clock pulse width (high) Minimum clock pulse width (low) Aperture delay Aperture uncertainty Clock output delay between input clock output clock (50%) Data output delay between input clock data Data output skew TR/TF Output rise/fall time data ready (10% 90%) with load Data output delay with data ready Data pipeline delay 0.400 0.400 0.500 0.500 +350 1.03 1.28 port port Gsps Msps ps(rms) clock cycles
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Figure Timing Diagram
Data Analog Input TDCLK Data Data Data
Input Clock
Output
Output
Data Ready Output Clock
TR/TF
TR/TF
Test Levels
Only minimum maximum values guaranteed (typical values issued from characterization results). Table Test Levels
Note: 100% wafer tested +25°C(1) 100% production tested +25°C(1) (for packaged device) Parameter guaranteed design Characterization testing: thermal steady-state conditions specified temperature) Parameter typical value only Unless otherwise specified, tests pulsed tests: therefore where junction, case ambient temperature respectively.
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AT76CL610
Equivalent Input/Output Schematics
Figure Simplified Input Model Signal
VCCA
VINI 0.62 VCCA 0.62 VCCA
VINIB
CNDA
Figure Simplified LVDS Output Model
VCCO
DOAI0:DOAI5 DOBI0:DOBI5 DOAI0N:DOAI5N DOBI0N:DOBI5N
GNDO
Figure Simplified Input Model Clock
VCCD
VCCA/2 CLKB
GNDD
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Applying AT76CL610
Power Supplies Decoupling, Bypassing Grounding
Here recommended bypassing, decoupling grounding schemes Dual 6-bit Gsps power supplies.
Figure VCCD VCCA Bypassing Grounding Scheme
Board +3.15V VCCA Board VCCD
Figure VCCO Bypassing Grounding Scheme
Board +2.25V VCCO
Board
Figure Power Supplies Decoupling Scheme
VCCA
VCCA
GNDA GNDA
VCCO
VCCO
AT76CL610 VCCD GNDD VCCD GNDO
GNDO
GNDD
Note:
bypassing capacitors should placed close possible board connectors, whereas decoupling capacitors (100 should placed close possible device.
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AT76CL610
Analog Inputs
analog inputs entered only differential mode. decoupling capacitance allows removal input common mode voltage 0.62 VCCA. terminal load located on-board. analog input resistance AT76CL610 equal Figure Differential Generator Dual 6-bit Configuration
Generator Vout Evaluation Board VIN_I VIN_Q Generator VoutB AT76CL610
VIN_IB VIN_QB
Note:
user should generator with differential output signal external splitter create differential signal.
Figure Generator Single-ended Differential Input
Evaluation Board Generator Vout TP-101 AT76CL610 VINI
VINIB
Clock Inputs
clock inputs entered differential single-ended mode. Moreover, possible clock input common mode coupling capacitance used remove input common mode voltage. necessary have on-board terminal load exists inside AT76CL610. generator used single mode signal. CLKBB must terminated load.
2158A-BDC-04/03
Figure Single-ended Configuration
Generator Evaluation Board
AT76CL610
Load Termination CLKB
generator with differential output signal external splitter also used order create differential signal. Figure Input Differential Configuration
Generator Vout Evaluation Board
AT76CL610 Generator VoutB CLKB
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AT76CL610
Package Description
80-lead TQFP Description
Table AT76CL610 80-lead TQFP Description
Symbol GNDA, GNDD, GNDO VCCA VCCD VCCO VINI VINIB VINQ VINQB CLKB DOAI0:DOAI5 DOAI0N:DOAI5N DOBI0:DOBI5 DOBI0N:DOBI5N DOAQ0:DOAQ5 DOAQ0N:DOAQ5N DOBQ0:DOBQ5 DOBQ0N:DOBQ5N DOIR DOIRN CLKO CLKOB Number Function Ground pins. connected external ground plane. Analog positive supply: 3.15V typ. +3.15V digital supply +2.25V output supply In-phase analog input signal sample hold differential preamplifier channel Inverted phase analog input signal (VINI) In-phase analog input signal sample hold differential preamplifier channel Inverted phase analog input signal (VINQ) In-phase clock input signal. analog input sampled held rising edge signal. Inverted phase clock input signal (CLK) In-phase digital outputs first phase demultiplexer DOAI0 LSB. D0AI5 MSB. Channel In-phase digital outputs first phase demultiplexer DOAI0N LSB. D0AI5N MSB. Channel In-phase digital outputs second phase demultiplexer DOBI0 LSB. D0BI5 MSB. Channel In-phase digital outputs second phase demultiplexer DOBI0N LSB. D0BI5N MSB. Channel In-phase digital outputs first phase demultiplexer DOAI0 LSB. D0AI5 MSB. Channel In-phase digital outputs first phase demultiplexer DOAI0N LSB. D0AI5N MSB. Channel In-phase digital outputs second phase demultiplexer DOBQ0 LSB. D0BQ5 MSB. Channel In-phase digital outputs second phase demultiplexer DOBQ0N LSB. D0BQ5N MSB. Channel Combined in-phase out-of-range first phase demultiplexer. Out-of-range high leading edge code code Combined in-phase out-of-range first phase demultiplexer Output clock in-phase (+),1/2 input clock frequency Output clock in-phase (-),1/2 input clock frequency connected
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Figure 80-lead TQFP Pinout
DOAQ5N DOBQ5N DOAQ4N DOBQ4N DOAQ3N DOBQ3N DOAQ2N DOBQ2N DOAQ1 DOAQ1N DOBQ1 DOBQ1N DOAQ0 DOAQ0N DOBQ0 TQFP80 DOBQ0N CLKO CLKOB ATMEL Dual 6-bit DOIRN DOIR DOBI0N DOBI0 DOAI0N DOAI0 DOBI1N DOBI1 DOAI1N DOAI1 DOAI5 DOAI5N DOBI5 DOBI5N DOAI4 DOAI4N DOBI4 DOBI4N VCCO GNDO DOAI3 DOAI3N DOBI3 DOBI3N VCCO GNDO DOAI2 DOAI2N DOBI2 DOBI2N
DOAQ5
DOBQ5
DOAQ4
DOBQ4
DOAQ3
DOBQ3
DOAQ2
GNDD VCCD GNDD GNDA VINQB VINQ GNDA VCCA
CLKB VCCA GNDA VINI VINIB GNDA GNDD VCCD GNDD
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DOBQ2
GNDO
GNDD
VCCO
VCCD
AT76CL610
Package Dimensions
Figure 80-lead TQFP Package Dimensions
Thickness Body +2.00 Footprint Dimensions Tolerances Max. 1.20 0.05 Min./0.15 Max. ±0.50 1.00 ±0.20 14.00 ±0.05 12.00 ±0.20 14.00 ±0.05 12.00 +0.15/-0.10 0.60 Basic 0.50 ±0.05 0.22 Max. 0.08 Max. 0.08 Notes: dimensions millimeters. Dimensions shown nominal with tolerances indicated. L/F: Eftec copper, 0.127 (0.005") thick. Foot length: measured gauge plane, 0.25 above seating plane.
TYP.
TYP.
0.20 RAD. NOM.
0.20 RAD. NOM.
Gauge plane Seating plane 0.25
Stand Lead coplanarity
1.00
Table 80-lead TQFP Package Characteristics
Package Type 80-lead TQFP (°C/W) 39.0
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Definition Terms
Table Definition Terms
error rate Probability exceeding specified error threshold sample. error code code that differs more than LSBs from correct code. Analog input frequency which fundamental component digitally reconstructed output fallen with respect frequency value (determined analysis) input full scale. Ratio expressed signal amplitude, below full scale, other spectral components, including harmonics except Ratio expressed first five harmonic components, value measured fundamental spectral component. Ratio expressed signal amplitude, below full scale, value next highest spectral component (peak spurious spectral component). SFDR parameter selecting converter used frequency domain application (radar systems, digital receiver, network analyzer.). reported (i.e., degrades signal levels lowered), dBFS (i.e., always related back converter full scale).
FPBW
Full-power input bandwidth Signal-to-noise distortion ratio Total harmonic distortion
SINAD
SFDR
Spurious free dynamic range
ENOB
Effective number bits
SINAD 1.76 A/V/2 ENOB -6.02
where actual input amplitude full scale range under test differential non-linearity output code difference between measured step size code ideal step size. expressed LSBs. maximum value (I). error specification less than guarantees that there missing output codes that transfer function monotonic. Measured with histogram method. integral non-linearity output code difference between measured input voltage which transition occurs ideal value this transition. expressed LSBs, maximum value |INL (I)|. Measured with histogram method. Delay between rising edge differential clock inputs (CLK, CLKB) (zero crossing point), time which (VIN, VINB) sampled. Sample-to-sample variation aperture delay. voltage error jitter depends slew rate signal sampling point. Time recover 0.2% accuracy output, after 150% full scale step applied input reduced mid-scale. Delay from falling edge differential clock inputs (CLK, CLKB) (zero crossing point) next point change differential output data (zero crossing) with specified load. Time delay from data transition ready data. Number clock cycles between sampling edge input data associated output data being made available (not taking account TDO). Time delay output data signals rise from delta between level high level. Time delay output data signals fall from delta between level high level.
Differential non-linearity
Integral non-linearity
JITTER
Aperture delay Aperture uncertainty Overvoltage recovery time
Digital data output delay Time delay from clock ready data Pipeline delay Rise time Fall time
AT76CL610
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AT76CL610
Table Definition Terms (Continued)
PSRR OFFI,Q Power supply rejection ratio Offset output code Inter-modulation distortion Ratio input offset variation change power supply voltage. Mean output code with input signal applied. two-tone intermodulation distortion (IMD) rejection ratio either input tone worst third order intermodulation products. input tone levels full scale.
Ordering Information
Table Ordering Information
Part Number AT76CL610-10AX AT76CL610-10AC AT76CL610-10AI AT76CL610-EB Package TQFP TQFP TQFP TQFP Temperature Range Ambient grade 70°C grade -20°C Ambient Screening Prototype Standard Standard Prototype Evaluation Comments Prototype
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Datasheet Status Description
Table Datasheet Status
Datasheet Status Objective specification This datasheet contains target goal specifications discussion with customer application validation. This datasheet contains target goal specifications product development. This datasheet contains preliminary data. Additional data published later could include simulation results. This datasheet contains characterization results. This datasheet contains final product specifications. Validity Before design phase
Target specification Preliminary specification -site Preliminary specification -site Product specification Limiting Values
Valid during design phase
Valid before characterization phase Valid before industrialization phase Valid production purposes
Limiting values given accordance with Absolute Maximum Rating System (IEC 134). Stress above more limiting values cause permanent damage device. These stress ratings only operation device these other conditions above those given Characteristics sections specification implied. Exposure limiting values extended periods affect device reliability. Application Information Where application information given, advisory does form part specification.
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AT76CL610
2158A-BDC-04/03
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2158A-BDC-04/03

Dual 6-bit Gsps Converter AT76CL610 Preliminary Specification App

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