Lattice's ispGAL®22V10A device package provides several added capabili
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Using ispGAL22V10A Package
Lattice's ispGAL®22V10A device package provides several added capabilities standard 22V10 architecture. (Quad Flat pack, lead) package, also known (Micro Lead Frame) package, near chip scale plastic encapsulated package that provides small footprint well better thermal, better speed more robust handling characteristics. This application note describes handle package, including information selecting attributes such slew rate control, open-drain input threshold through Lattice's ispLEVERdesign tool.
Package
high speed small size ispGAL22V10A, Lattice supplies this device 32-pin package. This package four more pins than standard 22V10 28-lead PLCC package. Even with additional four pins, package dramatically smaller than PLCC package shown Figure Refer Package Diagrams document Lattice site www.latticesemi.com detailed description package. Figure ispGAL22V10 Relative Package Sizes 32-pin Dimensions
24-pin 32-pin 32-pin
28-pin PLCC
22V10 packages (approximate actual size)
four additional pins package utilized VCCO GNDO pins provide separate power ground output pins from core logic. separate VCCO used supply different output voltage reference from core VCC. VCCO options package 1.8V, 2.5V 3.3V LVMOS output standards. also features paddle bottom package that forms thermal resistance path from die. Although necessary with low-power ispGAL22V10A device, this paddle soldered thermal printed circuit board improved heat dissipation. References section this document lists socket manufacturers application note assembly recommendations from Amkor Technology.
www.latticesemi.com
an8074_01
Lattice Semiconductor
Using ispGAL22V10A Package
ispLEVER Software Attributes ispGAL22V10A Device
ispLEVER version later supports ispGAL22V10A device option with following attributes.
Pullup/Buskeeper
This attribute globally Attribute options are: Down Pulldown Pullup Hold Hold Latch turning maintenance option This attribute only using ABEL. Syntax setting Pullup/Buskeeper attribute using ABEL: LATTICE LATTICE LATTICE LATTICE property property property property `PULL `PULL `PULL `PULL down'; up'; hold'; off';
Input Threshold
This attribute individual Input pin. Attribute options 2.5/3.3V LVCMOS 1.8V LVCMOS. This attribute using VHDL, Verilog ABEL. Syntax setting Input Threshold attribute using ABEL: LAT_IOTYPES (PinName, LVCMOS33);"2.5/3.3V LVCMOS LAT_IOTYPES (PinName, LVCMOS25);"2.5/3.3V LVCMOS LAT_IOTYPES (PinName, LVCMOS18);"1.8V LVCMOS Syntax setting Input Threshold attribute using VHDL: ATTRIBUTE IO_TYPES PinName: ATTRIBUTE IO_TYPES PinName: ATTRIBUTE IO_TYPES PinName: SIGNAL "LVCMOS33 ,-"; SIGNAL "LVCMOS25 ,-"; SIGNAL "LVCMOS18 ,-";
Syntax setting Input Threshold attribute using Verilog: Exemplar: //exemplar attribute PinName IO_TYPES LVCMOS33,-; //exemplar attribute PinName IO_TYPES LVCMOS25,-; //exemplar attribute PinName IO_TYPES LVCMOS18,-; Synplicity: output PinName synthesis IO_TYPES="LVCMOS33,-"*/; output PinName synthesis IO_TYPES="LVCMOS25,-"*/; output PinName synthesis IO_TYPES="LVCMOS18,-"*/;
SlewRate
This attribute individual pin. Attribute options Slow Fast. This attribute using VHDL, Verilog ABEL.
Lattice Semiconductor
Syntax setting SlewRate attribute using ABEL:
Using ispGAL22V10A Package
LAT_SLEW (SLOW, PinName);"Slow Slew LAT_SLEW (FAST, PinName);"Fast Slew Syntax setting SlewRate attribute using VHDL: ATTRIBUTE SLEW PinName: SIGNAL "SLOW"; ATTRIBUTE SLEW PinName: SIGNAL "FAST"; Syntax setting SlewRate attribute using Verilog: Exemplar: output PinName; //exemplar attribute PinName SLEW SLOW output PinName; //exemplar attribute PinName SLEW FAST Synplicity: output PinName synthesis SLEW="SLOW" output PinName synthesis SLEW="FAST"
Open Drain
This attribute individual pin. Attribute options Open Drain. this attribute specified default standard LVCMOS output. This attribute using VHDL, Verilog ABEL. Syntax setting Open Drain attribute using ABEL: LAT_IOTYPES (PinName, LVCMOS33_OD);"2.5/3.3V LVCMOS Opendrain LAT_IOTYPES (PinName, LVCMOS25_OD);"2.5/3.3V LVCMOS Opendrain LAT_IOTYPES (PinName, LVCMOS18_OD);"1.8V LVCMOS Opendrain Syntax setting Open Drain attribute using VHDL: ATTRIBUTE IO_TYPES PinName: ATTRIBUTE IO_TYPES PinName: ATTRIBUTE IO_TYPES PinName: SIGNAL "LVCMOS33_OD ,-"; SIGNAL "LVCMOS25_OD ,-"; SIGNAL "LVCMOS18_OD ,-";
Syntax setting Input Threshold attribute using Verilog: Exemplar: //exemplar attribute PinName IO_TYPES LVCMOS33_OD,-; //exemplar attribute PinName IO_TYPES LVCMOS25_OD,-; //exemplar attribute PinName IO_TYPES LVCMOS18_OD,-; Synplicity: output PinName synthesis IO_TYPES="LVCMOS33_OD,-"*/; output PinName synthesis IO_TYPES="LVCMOS25_OD,-"*/; output PinName synthesis IO_TYPES="LVCMOS18_OD,-"*/;
Lattice Semiconductor
Using ispGAL22V10A Package
References
Socket Manufacturers
Adapters.com: www.adapters.com Aries Electronics, Inc.: www.arieselec.com Emulation Technology Inc.: www.1800adapter.com Gryphics Inc.: www.gryphics.com Loranger International Corporation: www.loranger.com Plastronics: www.locknest.com
Application Note
Application Notes Surface Mount Assembly Amkor's MicroLeadFrame (MLF) Packages, available from Amkor Technology www.amkor.com.
Technical Support Assistance
Hotline: 1-800-LATTICE (Domestic) 1-408-826-6002 (International) e-mail: techsupport@latticesemi.com
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