Crossbar switches widely used today variety applications including net

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Crossbar switches widely used today variety applications including net

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Crossbar Switch Implementation Using Lattice ispLSI 5384VE Device
Crossbar switches widely used today variety applications including network switching, parallel computing various telecommunications applications. There off-the-shelf devices available that implement standard crossbar configurations. using CPLDs implement crossbar switches, design engineers have flexibility customize switch suit their specific design goals, well obtain switch configurations available with off-the-shelf parts. Additionally, In-System Programmable (ISPTM) devices allows switch re-configured design modifications become necessary. This document addresses implementation Non-blocking Crossbar switch Lattice ispLSI 5384VE Complex Programmable Logic Device (CPLD) architecture. design modifications implementing crossbar switch also given.
Figure 8-Port Unidirectional Switch
Connection
Inputs
Outputs
Crossbar Switches
crossbar switch, also known crosspoint switch, defined switch with input lines output lines port switch). switch intersections, called crosspoints, where input line output line electrically connected (see Figure seen from Figure number crosspoints grows square number lines into switch. assume that switch port does connect itself, number crosspoints needed given n(n-1)/2. n=32, there crosspoint connections. Splitting crossbar switch into several smaller switches interconnecting them dramatically reduce number crosspoints. This technique called space division switching. There penalty inherent this technique known blocking. Blocking occur when switch inputs attempt access same intermedi-
Figure Space Division Switch
Crossbars Crossbars
Crossbars (N/n)
(N/n)
Inputs
Outputs
an8035_05
February 2002
Crossbar Switch Implementation Using Lattice ispLSI 5384VE Device
switch channel. Figure illustrates space division switching. seen from Figure only half number switch inputs transmit given time. total number crosspoints needed switch Figure calculated. first stage, there crossbars with crosspoints total second stage there crossbars with (N/n)2 crosspoints. third stage same number crosspoints first. Adding three stages gives: Number crosspoints k(N/n)2 inputs, N=32, k=4, n=8. This gives crosspoints, which percent reduction number crosspoints needed non-partitioned crossbar switch. percent reduction number crosspoints proportional Digital Crosspoint Switch, which used serial digital video routing, telecom/datacom switching, ASONET. block diagram switch shown Figure switch inputs that connect outputs switch matrix. switch matrix constructed with thirty-two 32-input multiplexers. Each output supports individual tristate control. select lines (switch interconnects) tristate control configured using double buffered configuration registers. LOAD Registers loaded each port individually asserting LOAD signals. Output Address lines decoded select port's LOAD register, input address lines latched along with signal. latched input address lines drive port's select lines, drives port's tristate control. After LOAD registers have been configured, CNFG signals asserted, simultaneously configuring ports. This double buffering scheme prevents data from being lost while switch interconnects updated. reset modes supported. Broadcast reset results switch out-
Crossbar Switch Architecture
This ispLSI 5384VE port) crossbar switch design similar National Semiconductor CLC018
Figure Crossbar Switch Block Diagram
Inputs
Switch Matrix
Outputs
CNFG Configuration Registers
LOAD
Load Registers
Decoder
Output Address
Input Address
Crossbar Switch Implementation Using Lattice ispLSI 5384VE Device
Figure Crossbar Switch Implementation
Switch Inputs DI0-DI31
Lattice ispLSI 5384VE
Switch Outputs DO0-DO15
Lattice ispLSI 5384VE
DO16-DO31
Switch Control Lines
puts being select port Broadcast initiated asserting simultaneously. Tristate reset results outputs being disabled. Tristate reset initiated when asserted along with
Implementation
flexibility ispLSI 5384VE does limit maximum number ports Crossbar Switch implemented using four ispLSI 5384VE devices, single level logic. This accomplished following manner. Although there inputs into each GLB, maximum number product terms allowed output would take levels directly implement MUX. However, because ispLSI 5384VE supports tristate control I/Os, constructed single level. This accomplished externally tying outputs MUXes together using tristate control I/Os select lines (Figure inverting tristate control between outputs, only drive output given time, thus avoiding possibility contention.
Implementation
This design ideally suited Lattice ispLSI 5384VE device large number inputs required each MUX. switch, 32-input MUXes required. Lattice ispLSI 5384VE inputs into each Generic Logic Block (GLB), which allows MUXes implemented single level logic. Because this design uses double buffered switch configuration scheme, significant amount device resources must devoted switch control. Each port requires configuration registers. ports, this totals macrocells, including required decoding logic. Because this, ispLSI 5384VE CPLDs required implement crossbar switch (Figure However, entire implementation still takes only level logic. This implementation requires macrocells device, utilization, leaving room additional logic. switch design coded VHDL allowing number ports control logic reconfigured simply making modifications VHDL source code.
Conclusion
Clearly, Lattice ispLSI 5384VE superior choice implementing crossbar switches Fast Wide (BFW) structure. other CPLD boast one-level crossbar switch implementation with inputs outputs. This achieved ispLSI 5384VE
Crossbar Switch Implementation Using Lattice ispLSI 5384VE Device
Figure 64-Input
Input
Input Input
Output
Input
Select Select
large number inputs (68/GLB) product terms (160/GLB). using ispLSI 5384VE coding design VHDL, system designer limited standard feature available with offthe-shelf solutions. Because this implementation requires only device utilization, there sufficient resources left available implement other types standard logic control functions.
Source File
source code this design example downloaded from Lattice site www.latticesemi.com.
Technical Support Assistance
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