3.3V In-System Programmable SuperBIG, SuperWIDE High Density PLDs

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3.3V In-System Programmable SuperBIG, SuperWIDE High Density PLDs

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ispMACH 5000VG Family
3.3V In-System Programmable SuperBIG, SuperWIDE High Density PLDs
December 2001
Data Sheet
Features
High Density
1,024 macrocells I/Os
Ease Design
Product term sharing Extensive clocking capability
Easy System Integration
3.3V power supply socketing Input pull-up, pull-down bus-keeper Open drain capability Slew rate control Macrocell-based power management IEEE 1149.1 boundary scan testable In-system programmable IEEE 1532 compliant interface
sysCLOCKPLL Timing Control
Multiply divide factors between Clock shifting capability 3.5ns 500ps steps Multiple output frequencies External feedback capability board-level clock deskew LVDS/LVPECL clock input capability
High Speed Logic Implementation
SuperWIDE 68-input logic block product terms output Hierarchical routing structure provides fast interconnect
ispMACH 5000VG Introduction
ispMACH 5000VG represents third generation Lattice's SuperWIDE CPLD architecture. Through their wide 68-input blocks, these devices give significantly improved speed performance typical designs over architectures with fewer inputs. ispMACH 5000VG takes unique benefits SuperWIDE architecture extends higher densities referred SuperBIG, using combination innovative product term architecture twotiered hierarchical routing architecture. Additionally, sysCLOCK sysIO capabilities have been added maximize system-level performance integration.
sysIOCapability
LVCMOS 1.8, LVTTL SSTL SSTL 3.3, HSTL III) PCI-X, GTL+ AGP-1X tolerance Programmable drive strength
Table ispMACH 5000VG Family Selection Guide
ispMACH 5768VG Macrocells User Options (ns) Set-up with Hold (ns) (ns) fMAX (MHz) Supply Voltage Package 196/304 3.3V 256-ball fpBGA 484-ball fpBGA ispMACH 51024VG 1,024 304/384 3.3V 484-ball fpBGA 676-ball fpBGA
www.latticesemi.com
5kvg_09
Lattice Semiconductor
Figure Functional Block Diagram
RESETB GOE1 GOE2
ispMACH 5000VG Family Data Sheet
Bank
Bank
VCCO0 VREF0 GCLK0
VCCO3 VREF3 GCLK3
VCCP0 GNDP0
PLL0
Global Routing Pool
PLL1
VCCP1 GNDP1
GCLK1 VREF1 VCCO1
GCLK2 VREF2 VCCO2
Bank
Bank VCCJ
Overview
ispMACH 5000VG devices consist multiple SuperWIDE 68-input, 32-macrocell Generic Logic Blocks (GLBs) interconnected tiered routing system. Figure shows functional block diagram ispMACH 5000VG. Groups four GLBs, referred segments, interconnected Segment Routing Pool (SRP). Segments interconnected Global Routing Pool (GRP.) Together GLBs routing pools allow designers create large designs single device without compromising performance. Each inputs coming from contains product terms. These product terms form groups five product term clusters, which feed sharing array macrocell directly. ispMACH 5000VG allows product terms connected single macrocell product term expanders Sharing Array. macrocell designed provide flexible clocking control functionality with capability select between global, product term block-level resources. outputs macrocells back into switch matrices and, required, sysIO cell. I/Os ispMACH 5000VG family sysIOs, which split into four banks. Each bank separate power supply reference voltage. sysIO cells allow operation with wide range today's emerging interface standards. Within bank, inputs variety standards, providing reference voltage requirements chosen standards compatible. Within bank, outputs differing standards, providing power supply voltage reference voltage requirements chosen standard compatible. Support this wide range standards allows designers achieve significantly higher board-level performance compared more traditional LVCMOS standards.
Lattice Semiconductor
ispMACH 5000VG Family Data Sheet
ispMACH5000VG devices also contain sysCLOCK Phase Locked Loops (PLLs) that provide designers with increased clocking flexibility. PLLs used synthesize clocks on-chip elsewhere within system. They also used deskew clocks, again both chip system levels. variable delay line capability further improves this allows designers retard advance clock order tune set-up clock-to-out times optimal results. ispMACH 5000VG Family Selection Guide (Table details attributes packages ispMACH 5000VG devices.
ispMACH 5000VG Architecture
ispMACH 5000VG Family In-System Programmable High Density Logic Devices based segments containing four Generic Logic Blocks (GLBs) hierarchical routing pool (GRP) structure interconnecting segments. segment routing pool (SRP) connects each segment allowing maximum flexibility speed. Outputs from GLBs drive Segment Routing Pool (SRP) Global Routing Pool (GRP). Enhanced switching resources provided allow signals Segment Routing Pool drive GLBs segment. Optimal switching provided allow signals Global Routing Pool routed SRPs. This mechanism allows fast, efficient connections across entire device.
Segment
Each segment contains four GLBs segment routing pool (SRP). Each internal feedback outputs external feedback outputs, total outputs from each feeding SRP. contains signals, from each from GRP, with full routing capability. This routing scheme maximizes flexibility speed device without sacrificing routing. Figure Segment
Clocks
Clocks
Clocks
Segment Routing Pool (SRP)
Clocks
From
Generic Logic Block
Each contains macrocells fully populated, programmable AND-array with logic product terms three control product terms. inputs from Segment Routing Pool, which available both true complement form every product term. three control product terms used shared reset, clock output enable functions. Figure shows structure from macrocell perspective. This referred macrocell slice. There macrocell slices GLB.
AND-Array
programmable AND-Array consists inputs output product terms. inputs from used form lines AND-Array (true complement inputs). Each line array connected output product terms wired AND. Each logic product terms feed DualOR Array with remaining three control product terms feeding Shared Clock, Shared Reset Shared Every five product terms from logic product terms forms product term cluster start3
Lattice Semiconductor
Figure Macrocell Slice
ispMACH 5000VG Family Data Sheet
From Block From Cell PTSA Bypass Output Block PTSA Clock
Shared Clock BCLK0 BCLK1 BCLK2 BCLK3
From
Speed/ Power
Preset Reset Shared Reset Global Reset
Array
Dual-OR Array
Macrocell
Figure AND-Array
In[0] In[66] In[67]
Cluster
PT155 PT156 PT157 Cluster PT158 PT159 PT160 Shared clock PT161 Shared reset PT162 Shared Note: Indicates programmable fuse.
with PT0. There product term cluster every macrocell GLB. addition three control product terms, first, third, fourth fifth product terms each cluster used PTOE (output macrocells only), Clock, Preset Reset, respectively. Figure graphical representation AND-Array.
Lattice Semiconductor Enhanced Dual-OR Array
ispMACH 5000VG Family Data Sheet
facilitate logic functions requiring very large number product terms, ispMACH 5000VG architecture been enhanced with innovative product term expander capability. This capability embedded Dual-OR Array. Dual-OR Array consists gates. There gates macrocell GLB. These gates referred Expandable PTSA gate PTSA-Bypass gate. PTSA-Bypass gate receives five inputs from combination product terms associated with product term cluster. PTSA-Bypass gate feeds macrocell directly fast narrow logic. Expandable PTSA gate receives five inputs from combination product terms associated with product term cluster. also receives additional input from Expanded PTSA gate macrocell, where number macrocell associated with current gate. Expandable PTSA gate feeds PTSA sharing with other product terms Expandable PTSA gate. This allows cascading multiple gates wide functions. There small timing adder each level expansion. Figure graphical representation Enhanced Dual-OR Array. Figure Enhanced Dual-OR Array
From
Block
From From PTSA Bypass
Macrocell
From Clock
PTSA Macrocell
From
Preset Macrocell
From Reset Macrocell
Lattice Semiconductor Product Term Sharing Array
ispMACH 5000VG Family Data Sheet
Product Term Sharing Array (PTSA) consists inputs from Dual-OR Array (Expandable PTSA outputs directly macrocells. Each output term combination seven Expandable PTSA terms connected that output. Every macrocell connected N-3, N-2, N-1, N+1, PTSA terms programmable connection. This wraps around logic, Macrocell gets logic from Expandable PTSA used conjunction with PTSA allows wide functions implemented easily efficiently. Without using Expandable PTSA capability, greatest number product terms that included single function with pass delay Figure shows graphical representation PTSA. Figure Product Term Sharing Array
PTSA PTSA PTSA PTSA Macrocell Macrocell Macrocell
PTSA PTSA PTSA Macrocell Macrocell Macrocell
Macrocell
registered macrocells driven outputs from PTSA PTSA bypass. Each macrocell contains programmable gate, programmable register/latch flip-flop necessary clocks control logic allow combinatorial registered operation. macrocells each have outputs, which SRP, cell. This dual concurrent output capability from macrocell gives efficient hardware resources. output registered function example, while other output unrelated combinatorial function. direct register input from cell facilitates efficient macrocell construct high-speed input registers. Macrocell registers clocked from several global product term clocks available device. global product term clock enable also provided, eliminating need gate clock macrocell registers directly. Reset preset macrocell register provided from both global product term signals. macrocell register programmed operate D-type register D-type latch. Figure graphical representation ispMACH 5000VG macrocell.
Lattice Semiconductor
Figure Macrocell
ispMACH 5000VG Family Data Sheet
From Cell PTSA Bypass Output Block From PTSA Clock
Shared Clock BCLK0 BCLK1 BCLK2 BCLK3
Preset Reset Shared Reset Global Reset
Cell
cell ispMACH 5000VG device provides high degree flexibility. includes sysIO feature enhanced output enable optimal performance both off-chip. sysIO feature allows cells configured different standards, drive strengths slew rates. enhanced output enable provides different output enable choices cell. cell contains output enable (OE) MUX, programmable tri-state output buffer, programmable input buffer, programmable pull-up resistor, programmable pull-down resistor programmable bus-keeper latch. cell receives input from associated macrocell. cell feedback line associated macrocell direct path SRP. output enable (OE) selects signal cell. inputs four Shared PTOE signals, PTOE signals. also ability choose either true inverse each these signals. output goes through logical with signal allow easy tri-stating outputs testing purposes. four shared PTOE signals derived from PT163 each segment. PTOE signal derived from first product term each macrocell cluster, which directly routed MUX. Therefore, every cell have different signal. Figure graphical representation cell.
Lattice Semiconductor
Figure Cell
Shared (Segment) PTOE Shared (Segment) PTOE Shared (Segment) PTOE Shared (Segment) PTOE PTOE GOE0 GOE1 Data Output from Macrocell
ispMACH 5000VG Family Data Sheet
VCCO this bank VCCO other I/Os bank
Output Buffer (VCCO independent open drain outputs) CMOS/TTL Input Buffer (VREF independent)
Data Input Routing
Data Input Macrocell
VREF dependent Input Buffer
VREF other I/Os bank
sysIO Capability
ispMACH 5000VG devices divided into four sysIO banks, where each bank capable supporting different standards. Each sysIO bank supply voltage (VCCO) reference voltage (VREF) resources allowing each bank complete independence from others. Each within bank individually configurable based VCCO VREF settings. Table lists sysIO standards with typical values VCCO, VREF VTT. Table ispMACH 5000VG Supported Standards
sysIO Standard LVTTL LVCMOS-3.3 LVCMOS-2.5 LVCMOS-1.8 PCI-X AGP-1X SSTL3, Class SSTL2, Class HSTL, Class HSTL, Class GTL+ LVPECL, Differential1 LVDS1 VCCO 3.3V 3.3V 2.5V 1.8V 3.3V 3.3V 3.3V 3.3V 2.5V 3.3V 2.5V 1.5V 1.5V VREF 1.5V 1.25V 1.5V 1.25V 0.75V 0.9V 1.0V 1.5V 1.25V 1.5V 1.25V 0.75V 1.5V 1.5V
LVDS LVPECL only supported dedicated clock pins.
Lattice Semiconductor
ispMACH 5000VG Family Data Sheet
Global clock pins have additional capabilities that allow higher performance applications. global clock pins paired together create single global clock that interface with certain differential signals. JTAG pins ispMACH 5000VG device only pins that have sysIO capabilities. These pins only support LVTTL LVCMOS standards. There three classes interface standards that implemented ispMACH 5000VG devices. first unterminated, single-ended interface. includes 3.3V LVTTL standard along with 1.8V, 2.5V 3.3V LVCMOS interface standards. Additionally, 3.3, PCI-X AGP-1X subsets this type interface. second type interface implemented terminated, single-ended interface standard. This group interfaces includes different versions SSTL HSTL interfaces along with GTL+. Usage these particular interfaces requires additional VREF signal. system level, termination voltage, VTT, also required. Typically, output will terminated receiving transmission line driving. final types interfaces implemented differential standards LVDS LVPECL. These interfaces implemented clock pins only. When using differential standards, pair global clock pins (GCLK0 GCLK1 GCLK3 GCLK2) combined create single clock signal. more information sysIO capability, please refer Technical Note TN1000: ispMACH 5000VG sysIO Design Usage Guidelines
Clock Distribution
ispMACH 5000VG family four dedicated clock input pins: GCLK0-GCLK3. GLCK0 GCLK3 routed through circuit routed directly internal clock nets. internal clock nets (CLK0-CLK3) directly related dedicated clock pins (see Secondary Clock Divider exception when using sysCLOCK circuit). These feed clock multiplexes which generate clock signals (BCLK0-BCLK3). clock multiplexer allows variety true complementary versions clocks used within GLB. Each block clock true inverse associated global clock inverse adjacent global clock. Figure shows clock distribution network. Figure Clock Distribution Network
I/O/CLK_OUT0
GCLK0 VREF0 PLL0 SEC_OUT0 CLK_OUT0
CLK0
Clock BCLK0 Macrocells
CLK1 GCLK1 VREF1 sysCLOCK PLLs VREF2 GCLK2 CLK2 SEC_OUT1 PLL1 VREF3 GCLK3 CLK_OUT1 CLK3
Clock BCLK1 Macrocells
Global Clock Routing
Clock Routing
Clock BCLK2 Macrocells
Clock BCLK3 Macrocells
I/O/CLK_OUT1
Lattice Semiconductor sysCLOCK
ispMACH 5000VG Family Data Sheet
sysCLOCK circuitry consists Phase-Lock Loops (PLLs) various dividers, reset feedback signals associated with PLLs. This feature gives user ability synthesize clock frequencies generate multiple clock signals routing within device. Furthermore, generate clock signals that deskewed either board level device level. ispMACH 5000VG devices provide circuits. PLL0 receives clock inputs from GCLK provides outputs (CLK when using secondary clock). PLL1 operates with signals from GCLK (CLK when using secondary clock). outputs (CLK_OUT) routed dedicated dedicated pad. Further buffers these dedicated pads regular buffers that select either macrocell CLK_OUT (CLK_OUT0/CLK_OUT1) signal. CLK_OUT nets routed through GRP. Additionally, there sets signals used external control. Each PLL_RST, PLL_FBK PLL_LOCK signals. Figure shows ispMACH 5000VG block diagram. Figure Block Diagram
Input Clock Divider Programable Delay
PLL_RST
CLK_IN
Phase Detector
Post-scalar Divider
CLK_OUT
Clock
PLL_LOCK
Feedback Loop Divider
PLL_FBK
Secondary Clock Divider
SEC_OUT
Clock
order facilitate multiply divide capabilities PLL, each dividers associated with divider used divide clock signal, while divider used multiply clock signal. divider only used when secondary clock output needed. This divider divides primary clock output feeds separate global clock net. divider used provide lower frequency output clocks, while maintaining stable, high frequency output from PLL's circuit. also delay feature that allows output clock advanced delayed improve set-up clock-to-out times better performance. This operates inserting delay input feedback lines 0.5ns increments from 3.5ns. more information PLL, please refer Technical Note TN1003: ispMACH 5000VG Usage Guidelines
Power Management
ispMACH 5000VG devices provide unique power management controls. devices have power settings, high power power, node basis. power consumption approximately high power consumption with timing delay adder (tLP) routing delay power node. Each node configured either high power power. However, care should taken when sharing product terms between nodes with different power settings. ispMACH 5000VG devices also have power-off feature unused product terms. default, product term that used configured such. This allows device operate minimal power consumption without affecting timing design. more information power management, please refer Technical Note TN1002: Power Estimation ispMACH 5000VG Devices.
Lattice Semiconductor
ispMACH 5000VG Family Data Sheet
IEEE 1149.1-Compliant Boundary Scan Testability
ispMACH 5000VG devices have boundary scan cells compliant IEEE 1149.1 standard. This allows functional testing circuit board which device mounted through serial scan path that access critical logic notes. Internal registers linked internally, allowing test data shifted loaded directly onto test nodes, test node data captured shifted verification. addition, these devices linked into board-level serial scan path more board-level testing. test access port supply voltage operate with LVCMOS3.3, 1.8V standards.
sysIO Quick Configuration
facilitate most efficient board test, physical nature cells must before running continuity tests. these tests fast, nature, overhead time that required configuration I/Os' physical nature should minimal that board test time minimized. ispMACH 5000VG family devices allows this offering user ability quickly configure physical nature sysIO cells. This quick configuration takes milliseconds complete, whereas takes seconds entire device programmed. Lattice's ispVMSystem programming software either perform quick configuration through parallel port, generate test vectors necessary third-party test system.
IEEE 1532-Compliant In-System Programming
In-system programming devices provides number significant benefits including rapid prototyping, lower inventory levels, higher quality ability make in-field modifications. ispMACH 5000VG devices provide In-System Programming (ISPTM) capability through their Boundary Scan Test Access Port. This capability been implemented manner that ensures that port remains compliant IEEE 1532 standard. using IEEE 1532 communication interface through which achieved, customers benefit standard, welldefined interface. ispMACH 5000VG devices programmed across commercial temperature voltage range. PC-based Lattice software facilitates in-system programming ispMACH 5000VG devices. software takes JEDEC file output produced design implementation software, along with information about scan chain, creates vectors used drive scan chain. software these vectors drive scan chain parallel port Alternatively, software output files formats understood common automated test equipment. This equipment then used program ispMACH 5000VG devices during testing circuit board.
Security
programmable security provided ispMACH 5000VG devices deterrent unauthorized copying array configuration patterns. Once programmed, this prevents readback programmed pattern device programmer, securing proprietary design from competitors. security also prevents programming verification. entire device must erased order erase security bit.
Socketing
ispMACH 5000VG devices well suited those applications that require socketing capability. socketing device requires that device, when powered down, tolerate active signals I/Os inputs without being damaged. Additionally, requires that effects powered-down device minimal active signals.
Density Migration
ispMACH 5000 family been designed ensure that different density devices same package have same pin-out. Furthermore, architecture ensures high success rate when performing design migration from lower density parts higher density parts. many cases, possible shift lower utilization design targeted high density device lower density device. However, exact details final resource utilization will impact likely success each case.
Lattice Semiconductor
ispMACH 5000VG Family Data Sheet
Absolute Maximum Ratings1,
Supply Voltage (VCC) -0.5 5.4V Supply Voltage (VCCP) -0.5 5.4V Output Supply Voltage (VCCO) -0.5 5.4V Input Voltage Applied4 -0.5 5.6V Tri-state Output Voltage Applied. -0.5 5.6V Storage Temperature 150°C Junction Temperature (Tj) with Power Applied 130°C
Stress above those listed under "Absolute Maximum Ratings" cause permanent damage device. Functional operation device these other conditions above those indicated operational sections this specification implied. Compliance with Lattice Thermal Management document required. voltages referenced GND. Overshoot Undershoot (VIH (MAX)+2) volts permitted duration 20ns.
Recommended Operating Conditions
Symbol VCCP VCCJ (Commercial) (Industrial) Supply Voltage Supply Voltage block Supply Voltage IEEE1149.1 Test Access Port Junction Commercial Operation Junction Industrial Operation Parameter 1.65 Units
Note: VCCJ must appropriate range compatible with desired LVCMOS standard.
Erase Reprogram Specifications
Parameter Erase/Reprogram Cycle 1000 Units Cycles
Socketing Characteristics1,2,3
Symbol Parameter Input Leakage Current Condition (MAX) (MAX) 5.5V +/-100 +/-100 Units
Insensitive sequence VCCO. However, assumes monotonic rise fall rates VCCO. LVTTL, LVCMOS only (MAX), VCCO VCCO (MAX)
Lattice Semiconductor
ispMACH 5000VG Family Data Sheet
Electrical Characteristics
Over Recommended Operating Conditions
Symbol IIL, IPU2
Parameter Input Leakage Current Weak Pull-up Resistor Current
Condition (MAX) VCCO VCCO VCCO VCCO
VCCO (MAX) VCCO VCCO
+/-10 -150 -150 -150 -150 (MIN)
Units
Weak Pull-down Resistor Current (MAX) (MAX) Hold Sustaining Current Hold High Sustaining Current Hold Overdrive Current Hold High Overdrive Current Operating Power Supply Current Hold Trip Points Capacitance3 Clock Capacitance3 Global Input Capacitance3 3.3V, (MAX) VCCO 3.3V, 2.5, 1.8, 3.3V, (MAX) VCCO 3.3V, 2.5, 1.8, 3.3V, (MAX) VCCO 3.3V, 2.5, 1.8, (MAX) VCCO (MAX) (MAX) 3.3V
IBHLS2 IBHHS2 IBHLO2 IBHHO VBHT
ICC3,
Input leakage current measured with configured input with output driver tri-stated. measured with output driver active. maintenance circuits disabled. Only available LVCMOS LVTTL standards. 25°C, 1.0MHz. Device configured with 16-bit counters. varies with specific device configuration operating frequency.
Lattice Semiconductor
ispMACH 5000VG Family Data Sheet
sysIO Recommended Operating Conditions2
VCCO Standard LVCMOS LVCMOS LVCMOS LVTTL PCI-X AGP-1X SSTL SSTL HSTL GTL+
VREF 1.95 3.45 1.15 1.35 1.35 0.68 0.882 1.35 1.65 1.65 1.122
1.65 3.15
Software default setting. Typical values VCCO VREF average values.
Lattice Semiconductor
ispMACH 5000VG Family Data Sheet
sysIO Electrical Characteristics
Over Recommended Operating Conditions
Standard LVCMOS 3.31 LVCMOS -0.3 -0.3 LVTTL -0.3 LVCMOS PCI-X AGP-1X SSTL3 class SSTL3 class SSTL2 class SSTL2 class HSTL class HSTL class GTL+ -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 0.35VCCO 0.3VCCO 0.35VCCO 0.3VCCO VREF-0.2 VREF-0.2 VREF-0.18 VREF-0.18 VREF-0.2 VREF-0.2 VREF-0.1 VREF-0.1 VREF-0.2 0.65VCCO 0.5VCCO 0.5VCCO 0.5VCCO VREF+0.2 VREF+0.2 VREF+0.18 VREF+0.18 VREF+0.2 VREF+0.2 VREF+0.1 VREF+0.1 VREF+0.2 0.1VCCO 0.1VCCO 0.1VCCO 0.54 0.35 VREF-0.4 VREF-0.4 VCCO VCCO VCCO VCCO VCCO-0.4 VCCO 0.9VCCO 0.9VCCO 0.9VCCO VCCO-1.1 VCCO-0.9 VCCO-0.62 VCCO-0.43 VREF+0.4 VREF+0.4 VCCO-0.4 VCCO-0.4 IOL2 (mA) 5.33, 5.33, 5.33, 15.2 IOH2 (mA) -16, -12, -5.33, -0.1 -0.1 -16, -12, -5.33, -0.1 -12, -5.33, -0.1 -0.5 -0.5 -0.5 -7.6 -15.2
LVCMOS
-0.3
Software default setting average current drawn I/Os between adjacent bank connections, between last bank bank, shown logic signals connection table, shall exceed 96mA.
sysIO Differential Input Electrical Characteristics Operating Conditions
Symbol VINP VINM VTHD Parameter LVDS Input voltage LVDS Differential input threshold LVPECL Input Voltage LVPECL Input Voltage High 3.3V 3.6V 3.3V Test Conditions 3.6V ±100mV VCC-1.81 1.49V VCC-1.17 2.14V VCC-1.48 1.83V VCC-0.88 2.42V
Lattice Semiconductor
ispMACH 5000VG Family Data Sheet
ispMACH 5768VG External Switching Characteristics
Over Recommended Operating Conditions
Parameter tPD_PTSA tPD_GLOBAL tS_PTSA tSIR tH_PTSA tHIR tLPTOE/DIS tSPTOE/DIS tGOE/DIS tWIR tSKEW fMAX
0.25 2.75 2.75 2.75 117.0 90.9 181.0 9.75 9.75 11.25 0.35
10.0 11.5 13.0 10.0 11.5 17.5 8.85 0.45
12.0 13.5 16.0 10.9 13.4 20.4 10.0 0.55 Units
Description
1,2,3
178.6 135.1 312.5
Data propagation delay, 5-PT bypass Data propagation delay, intrasegment path Data propagation delay, intersegment path register setup time before clock, 5-PT bypass register setup time before clock register setup time before clock, input register path register hold time before clock, 5-PT bypass register hold time before clock register hold time before clock, input reg. path register clock-to-output delay External reset output delay External reset pulse duration Input output local product term output enable/disable Input output segment product term output enable/disable Global input output enable/disable Global clock width, high Global gate width (for transparent) high (for high transparent) Input register clock width, high Clock-to-out skew, block level Clock-to-out skew, segment level Clock frequency with internal feedback Clock frequency with external feedback, (tS_PTSA tCO) Clock frequency Toggle
10.0 73.0 58.8 116.0
87.0 69.0 138.0
fMAX (Ext.) fMAX (Tog.)
Timing v.1.20 Timing numbers based default LVCMOS Buffers. timing adjusters provided calculate timing other standards. Measured using standard switching circuit, assuming segment global routing loading worst case PTSA loading output switching. Pulse widths clock widths less than minimum will cause unknown behavior. Standard 16-bit counter using feedback.
Lattice Semiconductor
ispMACH 5000VG Family Data Sheet
ispMACH 51024VG External Switching Characteristics
Over Recommended Operating Conditions
Parameter tPD_PTSA tPD_GLOBAL tS_PTSA tSIR tH_PTSA tHIR tLPTOE/DIS tSPTOE/DIS tGOE/DIS tWIR tSKEW fMAX
0.25 2.75 2.75 2.75 117.0 90.9 181.0 9.75 9.75 11.25 0.35
10.0 11.5 13.0 10.0 11.5 17.5 8.85 0.45
12.0 13.5 16.0 10.9 13.4 20.4 10.0 0.55 Units
Description
1,2,3
178.6 135.1 312.5
Data propagation delay, 5-PT bypass Data propagation delay, intrasegment path Data propagation delay, intersegment path register setup time before clock, 5-PT bypass register setup time before clock register setup time before clock, input register path register hold time before clock, 5-PT bypass register hold time before clock register hold time before clock, input reg. path register clock-to-output delay External reset output delay External reset pulse duration Input output local product term output enable/disable Input output segment product term output enable/disable Global input output enable/disable Global clock width, high Global gate width (for transparent) high (for high transparent) Input register clock width, high Clock-to-out skew, block level Clock-to-out skew, segment level Clock frequency with internal feedback Clock frequency with external feedback, (tS_PTSA tCO) Clock frequency Toggle
10.0 73.0 58.8 116.0
87.0 69.0 138.0
fMAX (Ext.) fMAX (Tog.)
Timing v.1.10 Timing numbers based default LVCMOS Buffers. timing adjusters provided calculate timing other standards. Measured using standard switching circuit, assuming segment global routing loading worst case PTSA loading output switching. Pulse widths clock widths less than minimum will cause unknown behavior. Standard 16-bit counter using feedback.
Lattice Semiconductor
ispMACH 5000VG Family Data Sheet
Timing Model
task determining timing through ispMACH 5000VG family, like CPLD, relatively simple. timing model provided Figure shows specific delay paths. Once implementation given function determined either conceptually from software report file, delay path function easily determined from timing model. Lattice design tools report timing delays based same timing model particular design. Note that internal timing parameters given reference only, tested. external timing parameters tested guaranteed every device. more information timing model usage, please refer Technical Note TN1001: ispMACH 5000VG Timing Model Design Usage Guidelines. Figure ispMACH 5000VG Timing Model
From Feedback tROUTE tGRP tBLK tINREG
tPDb tPDi tPTSA tEXP tFBK tBUF tIOO tDIS
Feedback
tIOI
Data
SCLK
tGCLK_IN tIOI
tGCLK tPLL_DELAY
tPTCLK tBCLK
C.E.
tPLL_SEC_DELAY
tPTSR tBSR
tRST tIOI tSPTOE tPTOE
tGOE tIOI
Italicized items optional delay adders
Lattice Semiconductor
ispMACH 5000VG Family Data Sheet
ispMACH 5768VG Internal Timing Parameters
Over Recommended Operating Conditions
Parameter In/Out Delays tGCLK_IN tGOE tBUF tDIS tRSTb Routing Delays tROUTE tPTSA tPDB tPDi tINREG tFBK tGCLK tPLL_DELAY Delay through Product Term Sharing Array Delay 5-PT Bypass Propagation Delay Macrocell Propagation Delay Input Buffer Macrocell Register Delay Internal Feedback Delay Global Clock Tree Delay Programmable Delay Increment 0.65 0.65 0.00 1.15 1.15 0.00 2.60 0.60 2.80 2.80 0.00 2.80 0.40 0.40 1.00 3.00 0.00 0.85 0.50 0.60 1.50 1.75 1.75 2.40 0.75 1.00 3.10 3.00 0.65 0.65 0.00 1.15 1.15 0.00 3.90 0.90 4.20 4.20 0.00 4.20 1.85 0.85 0.50 3.05 0.00 0.70 0.50 0.60 2.25 1.85 2.50 3.50 1.00 1.50 4.65 4.50 1.05 1.05 0.00 1.55 1.55 0.00 5.05 1.20 5.50 5.50 0.00 5.65 2.35 1.35 0.50 3.50 0.00 0.55 0.50 0.60 3.00 2.45 3.50 4.00 1.25 2.00 6.00 6.00 1.25 1.25 0.00 1.75 1.75 0.00 5.95 1.45 6.60 6.60 0.00 6.90 2.50 1.80 0.80 4.40 0.00 0.65 0.50 0.60 4.00 3.05 4.50 4.50 1.50 2.50 7.00 7.00 Input Buffer Delay Global Clock Input Buffer Delay Global Delay Delay through Output Buffer Output Enable Time Output Disable Time Global RESETbar Delay 0.65 0.65 4.05 1.15 2.15 2.15 4.60 0.95 0.95 5.00 1.50 2.50 2.50 6.50 1.25 1.25 6.00 1.75 2.85 2.85 7.00 1.40 1.40 7.00 1.90 3.00 3.00 7.50 Description Units
Additional Delay When Using Secondary tPLL_SEC_DELAY Output tGRP tS_PT tST_PT tCOi tCES tCEH tSL_PT tGOi tPDLi tSRi tSRR Control Delays tBCLK tPTCLK Clock Delay Macrocell Clock Delay Global Routing Pool Delay D-Register Setup Time D-Register Setup Time with Clock D-Register Hold Time T-Register Setup Time T-Register Setup Time with Clock T-Register Hold Time Register Clock Output/Feedback Time Clock Enable Setup Time Clock Enable Hold Time Latch Setup Time Latch Setup Time with Clock Latch Hold Time Latch Gate Output/Feedback Time Propagation Delay through Transparent Latch Output/Feedback Asynchronous Reset Output/Feedback Delay Asynchronous Reset Recovery Delay Register/Latch Delays
Lattice Semiconductor
ispMACH 5000VG Family Data Sheet
ispMACH 5768VG Internal Timing Parameters (Continued)
Over Recommended Operating Conditions
Parameter tBSR tPTSR tSPTOE tPTOE Description Block Set/Reset Delay Macrocell Set/Reset Delay Segment Delay Macrocell Delay 2.00 2.00 2.40 1.40 3.00 3.00 3.60 2.10 4.00 4.00 7.75 1.75 4.80 4.80 9.10 2.10 Units
Notes: Timing v.1.20 Internal Timing Parameters tested reference only. Refer Timing Model this data sheet further details. tPLL_DELAY unit increment which clock signal incremented. adjust clock signal 3.5ns either direction units 0.5ns each step.
ispMACH 51024VG Internal Timing Parameters
Over Recommended Operating Conditions
Parameter In/Out Delays tGCLK_IN tGOE tBUF tDIS tRSTb Routing Delays tROUTE tPTSA tPDB tPDi tINREG tFBK tGCLK tPLL_DELAY Delay through Product Term Sharing Array Delay 5-PT Bypass Propagation Delay Macrocell Propagation Delay Input Buffer Macrocell Register Delay Internal Feedback Delay Global Clock Tree Delay Programmable Delay Increment 0.65 0.65 0.00 1.15 1.15 0.00 2.80 0.40 0.40 1.00 3.00 0.00 0.85 0.50 0.60 1.50 1.75 0.65 0.65 0.00 1.15 1.15 0.00 4.20 1.85 0.85 0.50 3.05 0.00 0.70 0.50 0.60 2.25 1.85 1.05 1.05 0.00 1.55 1.55 0.00 5.65 2.35 1.35 0.50 3.50 0.00 0.55 0.50 0.60 3.00 2.45 1.25 1.25 0.00 1.75 1.75 0.00 6.90 2.50 1.80 0.80 4.40 0.00 0.65 0.50 0.60 4.00 3.05 Input Buffer Delay Global Clock Input Buffer Delay Global Delay Delay through Output Buffer Output Enable Time Output Disable Time Global RESETbar Delay 0.65 0.65 4.05 1.15 2.15 2.15 4.60 0.95 0.95 5.00 1.50 2.50 2.50 6.50 1.25 1.25 6.00 1.75 2.85 2.85 7.00 1.40 1.40 7.00 1.90 3.00 3.00 7.50 Description Units
Additional Delay When Using Secondary tPLL_SEC_DELAY Output tGRP tS_PT tST_PT tCOi Global Routing Pool Delay D-Register Setup Time D-Register Setup Time with Clock D-Register Hold Time T-Register Setup Time T-Register Setup Time with Clock T-Register Hold Time Register Clock Output/Feedback Time Register/Latch Delays
Lattice Semiconductor
ispMACH 5000VG Family Data Sheet
ispMACH 51024VG Internal Timing Parameters (Continued)
Over Recommended Operating Conditions
Parameter tCES tCEH tSL_PT tGOi tPDLi tSRi tSRR Control Delays tBCLK tPTCLK tBSR tPTSR tSPTOE tPTOE Clock Delay Macrocell Clock Delay Block Set/Reset Delay Macrocell Set/Reset Delay Segment Delay Macrocell Delay 3.10 3.00 2.00 2.00 2.40 1.40 4.65 4.50 3.00 3.00 3.60 2.10 6.00 6.00 4.00 4.00 7.75 1.75 7.00 7.00 4.80 4.80 9.10 2.10 Description Clock Enable Setup Time Clock Enable Hold Time Latch Setup Time Latch Setup Time with Clock Latch Hold Time Latch Gate Output/Feedback Time Propagation Delay through Transparent Latch Output/Feedback Asynchronous Reset Output/Feedback Delay Asynchronous Reset Recovery Delay 2.60 0.60 2.80 2.80 0.00 1.75 2.40 0.75 1.00 3.90 0.90 4.20 4.20 0.00 2.50 3.50 1.00 1.50 5.05 1.20 5.50 5.50 0.00 3.50 4.00 1.25 2.00 5.95 1.45 6.60 6.60 0.00 4.50 4.50 1.50 2.50 Units
Notes: Timing v.1.10 Internal Timing Parameters tested reference only. Refer Timing Model this data sheet further details. tPLL_DELAY unit increment which clock signal incremented. adjust clock signal 3.5ns either direction units 0.5ns each step.
Lattice Semiconductor
ispMACH 5000VG Family Data Sheet
ispMACH 5768VG Timing Adders
Adder Type tBLA tEXP tIOI Input Adders LVCMOS18_in LVCMOS25_in LVCMOS33_in LVTTL PCI_in PCI_X_in AGP_1X_in SSTL3_I_in SSTL3_II_in SSTL2_I_in SSTL2_II_in CTT33_in CTT25_in HSTL_I_in HSTL_III_in GTL+_in LVDS_in LVPECL_in tIOO Output Adders LVCMOS18_4mA_out LVCMOS18_5mA_out LVCMOS18_8mA_out tBUF, tEN, tDIS tBUF, tEN, tDIS tBUF, tEN, tDIS Output configured 1.8V Buffer Output configured 1.8V 5.33mA Buffer Output configured 1.8V Buffer 3.00 2.50 1.85 3.00 2.50 1.85 3.00 2.50 1.85 3.00 2.50 1.85 tIN, tGCLK_IN, Using LVCMOS1.8 tRSTb, tGOE standard tIN, tGCLK_IN, Using LVCMOS2.5 tRSTb, tGOE standard tIN, tGCLK_IN, Using LVCMOS3.3 tRSTb, tGOE standard tIN, tGCLK_IN, Using LVTTL standard tRSTb, tGOE tIN, tGCLK_IN, Using standard tRSTb, tGOE tIN, tGCLK_IN, Using PCI_X tRSTb, tGOE standard tIN, tGCLK_IN, Using AGP-1X tRSTb, tGOE standard tIN, tGCLK_IN, Using SSTL3_I tRSTb, tGOE standard tIN, tGCLK_IN, Using SSTL3_II tRSTb, tGOE standard tIN, tGCLK_IN, Using SSTL2_I tRSTb, tGOE standard tIN, tGCLK_IN, Using SSTL2_II tRSTb, tGOE standard tIN, tGCLK_IN, Using CTT3.3 tRSTb, tGOE standard tIN, tGCLK_IN, Using CTT2.5 tRSTb, tGOE standard tIN, tGCLK_IN, Using HSTL_I tRSTb, tGOE standard tIN, tGCLK_IN, Using HSTL_III tRSTb, tGOE standard tIN, tGCLK_IN, Using GTL+ tRSTb, tGOE standard tGCLK_IN tGCLK_IN Using LVDS standard Using LVPECL standard 0.90 0.15 1.00 1.00 1.00 1.00 0.15 1.25 1.25 1.50 1.70 2.10 0.90 0.15 1.00 1.00 1.00 1.00 0.15 1.25 1.25 1.50 1.70 2.10 0.90 0.15 1.00 1.00 1.00 1.00 0.15 1.25 1.25 1.50 1.70 2.10 0.90 0.15 1.00 1.00 1.00 1.00 0.15 1.25 1.25 1.50 1.70 2.10 Base Parameter tROUTE tPTSA tROUTE Description Loading Adder Expander Adder Power Adder Units
Note: Open drain timing same corresponding LVCMOS timing.
Timing v.1.20
Lattice Semiconductor
ispMACH 5000VG Family Data Sheet
ispMACH 5768VG Timing Adders (Continued)
Adder Type LVCMOS18_12mA_out LVCMOS25_4mA_out LVCMOS25_5mA_out LVCMOS25_8mA_out LVCMOS25_12mA_out LVCMOS25_16mA_out LVCMOS33_4mA_out LVCMOS33_5mA_out LVCMOS33_8mA_out LVCMOS33_12mA_out LVCMOS33_16mA_out LVCMOS33_20mA_out LVTTL Slow Slew PCI_out PCI_X_out AGP_1X_out SSTL3_I_out SSTL3_II_out SSTL2_I_out SSTL2_II_out CTT33_out CTT25_out HSTL_I_out Base Parameter tBUF, tEN, tDIS tBUF, tEN, tDIS tBUF, tEN, tDIS tBUF, tEN, tDIS tBUF, tEN, tDIS tBUF, tEN, tDIS tBUF, tEN, tDIS tBUF, tEN, tDIS tBUF, tEN, tDIS tBUF, tEN, tDIS tBUF, tEN, tDIS tBUF, tEN, tDIS tBUF, tEN, tDIS tBUF, Description Output configured 1.8V 12mA Buffer Output configured 2.5V Buffer Output configured 2.5V 5.33mA Buffer Output configured 2.5V Buffer Output configured 2.5V 12mA Buffer Output configured 2.5V 16mA Buffer Output configured 3.3V Buffer Output configured 3.3V 5.33mA Buffer Output configured 3.3V Buffer Output configured 3.3V 12mA Buffer Output configured 3.3V 16mA Buffer Output configured 3.3V 20mA Buffer Output configured LVTTL Buffer Output configured slow slew rate 1.35 1.50 1.25 0.70 0.50 0.25 1.50 1.25 0.40 0.10 1.50 -0.25 -0.35 -0.25 0.25 -0.30 1.35 1.50 1.25 0.70 0.50 0.25 1.50 1.25 0.40 0.10 1.50 -0.25 -0.35 -0.25 0.25 -0.30 1.35 1.50 1.25 0.70 0.50 0.25 1.50 1.25 0.40 0.10 1.50 -0.25 -0.35 -0.25 0.25 -0.30 Units 1.35 1.50 1.25 0.70 0.50 0.25 1.50 1.25 0.40 0.10 1.50 -0.25 -0.35 -0.25 0.25 -0.30
tBUF, tEN, tDIS Using standard Using PCI-X tBUF, tEN, tDIS standard tBUF, tEN, tDIS tBUF, tEN, tDIS tBUF, tEN, tDIS tBUF, tEN, tDIS tBUF, tEN, tDIS tBUF, tEN, tDIS tBUF, tEN, tDIS tBUF, tEN, tDIS Using AGP-1X standard Using SSTL3_I standard Using SSTL3_II standard Using SSTL2_I standard Using SSTL2_II standard Using CCT3.3 standard Using CCT2.5 standard Using HSTL_I standard
Note: Open drain timing same corresponding LVCMOS timing.
Timing v.1.20
Lattice Semiconductor
ispMACH 5000VG Family Data Sheet
ispMACH 5768VG Timing Adders (Continued)
Adder Type HSTL_III_out GTL+_out Base Parameter tBUF, tEN, tDIS tBUF, tEN, tDIS Description Using HSTL_III standard Using GTL+ standard 0.00 0.30 0.00 0.30 0.00 0.30 Units 0.00 0.30
Note: Open drain timing same corresponding LVCMOS timing.
Timing v.1.20
ispMACH 51024VG Timing Adders
Adder Type tBLA tEXP tIOI Input Adders LVCMOS18_in LVCMOS25_in LVCMOS33_in LVTTL PCI_in PCI_X_in AGP_1X_in SSTL3_I_in SSTL3_II_in SSTL2_I_in SSTL2_II_in CTT33_in CTT25_in HSTL_I_in HSTL_III_in GTL+_in tIN, tGCLK_IN, Using LVCMOS1.8 tRSTb, tGOE standard tIN, tGCLK_IN, Using LVCMOS2.5 tRSTb, tGOE standard tIN, tGCLK_IN, Using LVCMOS3.3 tRSTb, tGOE standard tIN, tGCLK_IN, Using LVTTL standard tRSTb, tGOE tIN, tGCLK_IN, Using standard tRSTb, tGOE tIN, tGCLK_IN, Using PCI_X tRSTb, tGOE standard tIN, tGCLK_IN, Using AGP-1X tRSTb, tGOE standard tIN, tGCLK_IN, Using SSTL3_I tRSTb, tGOE standard tIN, tGCLK_IN, Using SSTL3_II tRSTb, tGOE standard tIN, tGCLK_IN, Using SSTL2_I tRSTb, tGOE standard tIN, tGCLK_IN, Using SSTL2_II tRSTb, tGOE standard tIN, tGCLK_IN, Using CTT3.3 tRSTb, tGOE standard tIN, tGCLK_IN, Using CTT2.5 tRSTb, tGOE standard tIN, tGCLK_IN, Using HSTL_I tRSTb, tGOE standard tIN, tGCLK_IN, Using HSTL_III tRSTb, tGOE standard tIN, tGCLK_IN, Using GTL+ tRSTb, tGOE standard 0.90 0.15 1.00 1.00 1.00 1.00 0.15 1.25 1.25 1.50 0.90 0.15 1.00 1.00 1.00 1.00 0.15 1.25 1.25 1.50 0.90 0.15 1.00 1.00 1.00 1.00 0.15 1.25 1.25 1.50 0.90 0.15 1.00 1.00 1.00 1.00 0.15 1.25 1.25 1.50 Base Parameter tROUTE tPTSA tROUTE Description Loading Adder Expander Adder Power Adder Units
Note: Open drain timing same corresponding LVCMOS timing.
Timing v.1.10
Lattice Semiconductor
ispMACH 5000VG Family Data Sheet
ispMACH 51024VG Timing Adders (Continued)
Adder Type LVDS_in LVPECL_in tIOO Output Adders LVCMOS18_4mA_out LVCMOS18_5mA_out LVCMOS18_8mA_out LVCMOS18_12mA_out LVCMOS25_4mA_out LVCMOS25_5mA_out LVCMOS25_8mA_out LVCMOS25_12mA_out LVCMOS25_16mA_out LVCMOS33_4mA_out LVCMOS33_5mA_out LVCMOS33_8mA_out LVCMOS33_12mA_out LVCMOS33_16mA_out LVCMOS33_20mA_out LVTTL Slow Slew PCI_out PCI_X_out AGP_1X_out SSTL3_I_out SSTL3_II_out tBUF, tEN, tDIS tBUF, tEN, tDIS tBUF, tEN, tDIS tBUF, tEN, tDIS tBUF, tEN, tDIS tBUF, tEN, tDIS tBUF, tEN, tDIS tBUF, tEN, tDIS tBUF, tEN, tDIS tBUF, tEN, tDIS tBUF, tEN, tDIS tBUF, tEN, tDIS tBUF, tEN, tDIS tBUF, tEN, tDIS tBUF, tEN, tDIS tBUF, tEN, tDIS tBUF, Output configured 1.8V Buffer Output configured 1.8V 5.33mA Buffer Output configured 1.8V Buffer Output configured 1.8V 12mA Buffer Output configured 2.5V Buffer Output configured 2.5V 5.33mA Buffer Output configured 2.5V Buffer Output configured 2.5V 12mA Buffer Output configured 2.5V 16mA Buffer Output configured 3.3V Buffer Output configured 3.3V 5.33mA Buffer Output configured 3.3V Buffer Output configured 3.3V 12mA Buffer Output configured 3.3V 16mA Buffer Output configured 3.3V 20mA Buffer Output configured LVTTL Buffer Output configured slow slew rate Using PCI-X standard Using AGP-1X standard Using SSTL3_I standard Using SSTL3_II standard 3.00 2.50 1.85 1.35 1.50 1.25 0.70 0.50 0.25 1.50 1.25 0.40 0.10 1.50 -0.25 -0.35 3.00 2.50 1.85 1.35 1.50 1.25 0.70 0.50 0.25 1.50 1.25 0.40 0.10 1.50 -0.25 -0.35 3.00 2.50 1.85 1.35 1.50 1.25 0.70 0.50 0.25 1.50 1.25 0.40 0.10 1.50 -0.25 -0.35 3.00 2.50 1.85 1.35 1.50 1.25 0.70 0.50 0.25 1.50 1.25 0.40 0.10 1.50 -0.25 -0.35 Base Parameter tGCLK_IN tGCLK_IN Description Using LVDS standard Using LVPECL standard 1.70 2.10 1.70 2.10 1.70 2.10 Units 1.70 2.10
tBUF, tEN, tDIS Using standard tBUF, tEN, tDIS tBUF, tEN, tDIS tBUF, tEN, tDIS tBUF, tEN, tDIS
Note: Open drain timing same corresponding LVCMOS timing.
Timing v.1.10
Lattice Semiconductor
ispMACH 5000VG Family Data Sheet
ispMACH 51024VG Timing Adders (Continued)
Adder Type SSTL2_I_out SSTL2_II_out CTT33_out CTT25_out HSTL_I_out HSTL_III_out GTL+_out Base Parameter tBUF, tEN, tDIS tBUF, tEN, tDIS tBUF, tEN, tDIS tBUF, tEN, tDIS tBUF, tEN, tDIS tBUF, tEN, tDIS tBUF, tEN, tDIS Description Using SSTL2_I standard Using SSTL2_II standard Using CCT3.3 standard Using CCT2.5 standard Using HSTL_I standard Using HSTL_III standard Using GTL+ standard -0.25 0.25 -0.30 0.00 0.30 -0.25 0.25 -0.30 0.00 0.30 -0.25 0.25 -0.30 0.00 0.30 Units -0.25 0.25 -0.30 0.00 0.30
Note: Open drain timing same corresponding LVCMOS timing.
Timing v.1.10
Lattice Semiconductor
ispMACH 5000VG Family Data Sheet
sysCLOCK Timing
Over Recommended Operating Conditions1
Symbol tR,tF tINSTB tPWH tPWL fMDIVIN fMDIVOUT fVDIVIN fVDIVOUT tOUTDUTY tJIT(CC) Parameter Input clock, rise fall time Input clock stability, period jitter (peak)1 Input clock, high time Input clock, time Divider input, frequency range Divider output, frequency range Divider input, frequency range Divider output, frequency range Output clock, duty cycle Conditions Clean Reference, 5MHz fMDIVOUT 80MHz Clean Reference, 80MHz fMDIVOUT 180MHz
0.35 2.45 11.0
0.65 4.55
Units
Output clock, cycle cycle jitter (peak)
tJIT()
Output clock, accumulated phase jitter (peak)
Clean Reference, 5MHz fMDIVOUT 80MHz Clean Reference, 80MHz fMDIVOUT 180MHz Internal feedback External feedback
tCLK_OUT_DLY Input clock CLK_OUT delay tLOCK tPLL_DELAY tRANGE tPLL_RSTR tPLL_RSTW Input clock external feedback delta Time acquire phase lock after input stable Delay increment Total output delay range Reset recovery time M-divider Minimum reset pulse width
This condition assures that output phase jitter (tJIT()) will remain within specification. Accumulated jitter measured over 10,000 waveform samples.
Boundary Scan Timing Specifications
Symbol tBTCP tBTCH tBTCL tBTSU tBTH tBRF tBTCO tBTOZ tBTVO tBVTCPSU tBTCPH tBTUCO tBTUOZ tBTUOV [BSCAN test] clock cycle [BSCAN test] pulse width high [BSCAN test] pulse width [BSCAN test] setup time [BSCAN test] hold time [BSCAN test] rise fall time controller falling edge clock valid output controller falling edge clock data output disable controller falling edge clock data output enable BSCAN test Capture register setup time BSCAN test Capture register hold time BSCAN test Update reg, falling edge clock valid output BSCAN test Update reg, falling edge clock output disable BSCAN test Update reg, falling edge clock output enable Parameter Min. Max. Units mV/ns
Lattice Semiconductor
ispMACH 5000VG Family Data Sheet
Power Consumption
ispMACH 5000VG Typical Power Frequency
ispMACH 5000VG Curves High Power Mode (mA) 5768VG High Power Mode (mA) 51024VG High Power Mode 5768VG Power Mode ispMACH 5000VG Curves Power Mode
51024VG Power Mode
fMAX (MHz)
fMAX (MHz)
Note: devices configured with maximum number 16-bit counters, PLL, typical current 3.3V,
Power Estimation Coefficients
Device ispMACH 5768VG ispMACH 51024VG 0.0014 0.0014 0.0014 0.0014 0.054 0.054 0.152 0.152 0.105 0.105 (mA) IDCO (mA)
Note: further information about these coefficients, refer Technical Note TN1002, Power Estimation ispMACH 5000VG Devices. average current product term high power/MHz average current product term power/MHz average current line/MHz average current PLL/MHz current product terms high power current product terms power Static current Static device current with product terms powered IDCO Static bank current estimates based typical conditions (Vcc 3.3V, room temperature) assumption load average exists. These values estimates only. Since value sensitive operating conditions program device, actual should verified.
Lattice Semiconductor
ispMACH 5000VG Family Data Sheet
Switching Test Conditions
Figure shows output test load that used testing. specific values resistance, capacitance, voltage, other test conditions shown Table Figure Output Test Load, LVTTL LVCMOS Standards VCCO Test Point
includes Test Fixture Probe Capacitance.
0213A/ispm5kvg
Table Test Fixture Required Components
Test Condition Default LVCMOS Other LVCMOS Settings, Default LVCMOS Default LVCMOS Default LVCMOS Default LVCMOS 35pF 35pF 35pF 35pF LVCMOS 1.5V LVCMOS VCCO/2 LVCMOS VCCO/2 1.5V 1.5V Timing Ref. 3.0V LVCMOS 3.0V LVCMOS 2.3V LVCMOS 1.65V 3.0V 3.0V 3.0V 3.0V VCCO
Output test conditions other interfaces determined respective standards. further details, please refer following technical note: ispMACH 5000VG sysIO Design Usage Guidelines (TN1000)
Lattice Semiconductor
ispMACH 5000VG Family Data Sheet
Signal Descriptions
Signal Names GOE0, GOE1 RESETB Description Input This Test Mode Select input, which used control 1149.1 state machine. Input This Test Clock input pin, used clock 1149.1 state machine. Input This 1149.1 Test Data pin, used load data. Output This 1149.1 Test Data used shift data out. Input Test Output Enable pin. tristates pins when logic driven. Input These pins Global Output Enable input pins. Dedicated Reset Input This resets registers devices. global polarity (active high input) this selectable. Input/Output These general purpose used logic array. segment reference (numeric), reference (alpha) macrocell reference (numeric). (1024) (768) 0-31 Ground connect These power supply pins logic core. Input These pins configured either dedicated input input. Input These pins dedicated input. Output These pins output pins. Input These pins resetting PLL, input clock divider. Input These reference supplies banks. Input These feedback inputs allow optional external feedback. These supplies PLLs.
xyzz (e.g. 0A16)
GCLK0, GCLK3 GCLK1, GCLK2 CLK_OUT0, CLK_OUT1 PLL_RST0, PLL_RST1 VREF0, VREF1, VREF2, VREF3 PLL_FBK0, PLL_FBK1 VCCP0, VCCP1
VCCO0, VCCO1, VCCO2, These supplies each bank. VCCO3 GNDP0, GNDP1 VCCJ These separate ground connections PLLs. This 1149.1 test access port.
Note: above, signal CLK_OUT0 connects PLL0, signal CLK_OUT1 connects PLL1.
Lattice Semiconductor
ispMACH 5000VG Family Data Sheet
ispMACH 5768VG Power Supply Connections1
Signal VCCO0 VCCO1 VCCO2 VCCO3 VCCP0 VCCP1 VCCJ VREF0 VREF1 VREF2 VREF3 K14, P10, C10, C14, 256-Ball fpBGA2 H11, J11, 484-Ball fpBGA2 B17, B21, C14, E18, F21, J20, P20, U21, Y14, AA17, AA2, AA21, P18, U18, V14, V17, B18, D16, E14, E17, E21, F18, G19, AA10 AA13
C12, E14, G10, A22, C20, D19, E16, H10, K10, M14, G10, G11, G12, G13, G14, G15, G16, G18, H10, H11, H12, H13, H14, H15, H16, J10, J11, J12, J13, J14, J15, J16, K10, K11, K12, K13, K14, K15, K16, L10, L11, L12, L13, L14, L15, M10, M11, M12, M13, M14, M15, M16, N10, N11, N12, N13, N14, N15, N16, P10, P11, P12, P13, P14, P15, P16, R10, R11, R12, R13, R14, R15, R16, T10, T11, T12, T13, T14, T15, T16, T19, W16, AB1, AB22
grounds must electrically connected board level. grounds internally connected within device. pins connected active signals, GND.
Lattice Semiconductor
ispMACH 5000VG Family Data Sheet
ispMACH 51024 Power Supply Connections1
Signal VCCO0 VCCO1 VCCO2 VCCO3 VCCP0 VCCP1 VCCJ VREF0 VREF1 VREF2 VREF3 484-Ball fpBGA2 B17, B21, C14, E18, F21, J20, P20, U21, Y14, AA17, AA2, AA21, P18, U18, V14, V17, B18, D16, E14, E17, E21, F18, G19, AA10 AA13 A22, C20, D19, E16, G10, G11, G12, G13, G14, G15, G16, G18, H10, H11, H12, H13, H14, H15, H16, J10, J11, J12, J13, J14, J15, J16, K10, K11, K12, K13, K14, K15, K16, L10, L11, L12, L13, L14, L15, M10, M11, M12, M13, M14, M15, M16, N10, N11, N12, N13, N14, N15, N16, P10, P11, P12, P13, P14, P15, P16, R10, R11, R12, R13, R14, R15, R16, T10, T11, T12, T13, T14, T15, T16, T19, W16, AB1, AB22 676-Ball fpBGA2 B29, D10, D12, D19, D21, D25, F27, K27, M27, W27, AA4, AA27, AE4, AE27, AG6, AG10, AG12, AG19, AG21,AG25, E11, F10, AA6, AB5, AD5, AE10, AF5, AF7, AF9, AF11 Y26, AA25, AB26, AD26, AE21, AF20, AF22, AF24, AF26 E20, E22, E24, E26, F21, G26, J26, K25, AK10 AJ21 A30, B2,C3, C28, D23, F11, F12, F19, F20, F22, F24, G25, H27, J25, L11, L12, L13, L14, L15, L16, L17, L18, L19, L20, L25, M11, M12, M13, M14, M15, M16, M17, M18, M19, M20, M25, N11, N12, N13, N14, N15, N16, N17, N18, N19, N20, P11, P12, P13, P14, P15, P16, P17, P18, P19, P20, R11, R12, R13, R14, R15, R16, R17, R18, R19, R20, T11, T12, T13, T14, T15, T16, T17, T18, T19, T20, U11, U12, U13, U14,U15, U16, U17, U18, U19, U20, V11, V12, V13, V14, V15, V16, V17, V18, V19, V20, W11, W12, W13, W14, W15, W16, W17, W18, W19, W20, W25, Y11, Y12, Y13, Y14, Y15, Y16, Y17, Y18, Y19, Y20, Y25, AB6, AB25, AC4, AC27, AD6, AD25, AE7, AE9, AE11, AE12, AE19, AE20, AE22, AE24, AG8, AG23, AH3, AH28, AK1, AK30 A14, A15, A16, A17, B14, B15, B16, B17, C13, C14, C15, C16, C17, C18, D13, D14, D15, D16, D17, D18, E13, E14, E15, E16, E17, E18, F13, F14, F15, F16, F17, F18, AE13, AE14, AE15, AE16, AE17, AE18, AF13, AF14, AF15, AF16, AF17, AF18, AG13, AG14, AG15, AG16, AG17, AG18, AH14, AH15, AH16, AH17, AH18, AJ14, AJ15, AJ16, AJ17, AJ18, AK14, AK15, AK16, AK17
grounds must electrically connected board level. grounds internally connected within device. pins connected active signals, GND.
Lattice Semiconductor
ispMACH 5000VG Family Data Sheet
ispMACH 5768VG Logic Signal Connections
Bank Signal 0C-30 0C-28 0C-26 0C-24 0C-22 0C-20 GNDIO0 0C-18 0C-16 0C-14/VREF0 0C-12 0C-10 0C-8 0C-6 0C-4 0C-2 0C-0 0D-30 0D-28 GNDIO0 0D-26 0D-24 0D-22 0D-20 0D-18 0D-16 0D-14 0D-12 0D-10 0D-8 0D-6 0D-4 GNDIO0 0D-2 0D-0 0A-0 0A-2 0A-4 0A-6 0A-8 0A-10 GNDIO0 0A-12 fpBGA fpBGA Bank Signal 0A-14 0A-16 0A-18 0A-20 0A-22 0A-24 0A-26 GNDIO0 0A-28 0A-30 0B-30 0B-28 0B-26 0B-24 0B-22 0B-20 0B-18 0B-16 0B-14 0B-12 GNDIO0 0B-10 0B-8 0B-6 0B-4 0B-2 0B-0 1A-0 1A-2 1A-4 1A-6 1A-8 1A-10 GNDIO0 1A-12 1A-14 1A-16 1A-18 1A-20 1A-22 1A-24 1A-26 1A-28 fpBGA fpBGA
Lattice Semiconductor
ispMACH 5000VG Family Data Sheet
ispMACH 5768VG Logic Signal Connections (Continued)
Bank Signal 1A-30 GNDIO0 1B-30/CLK_OUT0 1B-28 1B-26 1B-24 1B-22 1B-20 1B-18 1B-16 1B-14 1B-12 GNDIO0 1B-10 1B-8 1B-6/PLL_RST0 1B-4/PLL_FBK0 1B-2 1B-0 2B-0 2B-2 2B-4 2B-6 2B-8 2B-10 GNDIO1 2B-12 2B-14 2B-16 2B-18 2B-20 2B-22 2B-24 2B-26 2B-28 2B-30 2A-30 2A-28 GNDIO1 2A-26 2A-24 2A-22 2A-20 fpBGA fpBGA Bank Signal 2A-18 2A-16 2A-14 2A-12 GNDIO1 2A-10 2A-8 2A-6 2A-4 2A-2 2A-0 2D-0 2D-2 GNDIO1 2D-4 2D-6 2D-8 2D-10 2D-12 2D-14 2D-16 2D-18 2D-20 2D-22 2D-24 2D-26 GNDIO1 2D-28 2D-30 2C-0 2C-2 2C-4 2C-6 2C-8 2C-10 2C-12 2C-14/VREF1 2C-16 2C-18 GNDIO1 2C-20 2C-22 2C-24 fpBGA fpBGA AA10 AB10
Lattice Semiconductor
ispMACH 5000VG Family Data Sheet
ispMACH 5768VG Logic Signal Connections (Continued)
Bank Signal 2C-26 2C-28 2C-30 3C-30 3C-28 3C-26 3C-24 3C-22 3C-20 GNDIO2 3C-18 3C-16 3C-14 3C-12/VREF2 3C-10 3C-8 3C-6 3C-4 3C-2 3C-0 3D-30 3D-28 GNDIO2 3D-26 3D-24 3D-22 3D-20 3D-18 3D-16 3D-14 3D-12 3D-10 3D-8 3D-6 3D-4 GNDIO2 3D-2 3D-0 3A-0 3A-2 3A-4 3A-6 3A-8 fpBGA fpBGA AA11 AB11 AB12 AA12 AB13 AA13 AB14 AA14 AB15 AB16 AA15 AB17 AA16 AB18 AB19 AB20 AA18 AA19 AB21 Bank Signal 3A-10 GNDIO2 3A-12 3A-14 3A-16 3A-18 3A-20 3A-22 3A-24 3A-26 GNDIO2 3A-28 3A-30 3B-30 3B-28 3B-26 3B-24 3B-22 3B-20 3B-18 3B-16 3B-14 3B-12 GNDIO2 3B-10 3B-8 3B-6 3B-4 3B-2 3B-0 4B-0 4B-2 4B-4/PLL_FBK1 4B-6/PLL_RST1 4B-8 4B-10 GNDIO3 4B-12 4B-14 4B-16 4B-18 4B-20 4B-22 fpBGA fpBGA AA20 AA22
Lattice Semiconductor
ispMACH 5000VG Family Data Sheet
ispMACH 5768VG Logic Signal Connections (Continued)
Bank Signal 4B-24 4B-26 4B-28 4B-30/CLK_OUT1 GNDIO3 4A-30 4A-28 4A-26 4A-24 4A-22 4A-20 4A-18 4A-16 4A-14 4A-12 GNDIO3 4A-10 4A-8 4A-6 4A-4 4A-2 4A-0 5B-0 5B-2 5B-4 5B-6 5B-8 5B-10 GNDIO3 5B-12 5B-14 5B-16 5B-18 5B-20 5B-22 5B-24 5B-26 5B-28 5B-30 5A-30 5A-28 GNDIO3 5A-26 fpBGA fpBGA Bank Signal 5A-24 5A-22 5A-20 5A-18 5A-16 5A-14 5A-12 GNDIO3 5A-10 5A-8 5A-6 5A-4 5A-2 5A-0 5D-0 5D-2 GNDIO3 5D-4 5D-6 5D-8 5D-10 5D-12 5D-14 5D-16 5D-18 5D-20 5D-22 5D-24 5D-26 GNDIO3 5D-28 5D-30 5C-0 5C-2 5C-4 5C-6 5C-8 5C-10 5C-12/VREF3 5C-14 5C-16 5C-18 GNDIO3 fpBGA fpBGA
Lattice Semiconductor
ispMACH 5000VG Family Data Sheet
ispMACH 5768VG Logic Signal Connections (Continued)
Bank Signal 5C-20 5C-22 5C-24 5C-26 5C-28 5C-30 GCLK0 GCLK1 GCLK2 GCLK3 GOE0 GOE1 RESETB fpBGA fpBGA
Lattice Semiconductor
ispMACH 5000VG Family Data Sheet
ispMACH 51024VG Logic Signal Connections
Bank Signal 0C-30 0C-28 0C-26 0C-24 0C-22 0C-20 GNDIO0 0C-18 0C-16 0C-14/VREF0 0C-12 0C-10 0C-8 0C-6 0C-4 0C-2 0C-0 0D-30 0D-28 GNDIO0 0D-26 0D-24 0D-22 0D-20 0D-18 0D-16 0D-14 0D-12 0D-10 0D-8 0D-6 0D-4 GNDIO0 0D-2 0D-0 0A-0 0A-2 0A-4 0A-6 0A-8 0A-10 GNDIO0 0A-12 fpBGA fpBGA Bank Signal 0A-14 0A-16 0A-18 0A-20 0A-22 0A-24 0A-26 GNDIO0 0A-28 0A-30 0B-30 0B-28 0B-26 0B-24 0B-22 0B-20 0B-18 0B-16 0B-14 0B-12 GNDIO0 0B-10 0B-8 0B-6 0B-4 0B-2 0B-0 1A-0 1A-2 1A-4 1A-6 1A-8 1A-10 GNDIO0 1A-12 1A-14 1A-16 1A-18 1A-20 1A-22 1A-24 1A-26 1A-28 fpBGA fpBGA
Lattice Semiconductor
ispMACH 5000VG Family Data Sheet
ispMACH 51024VG Logic Signal Connections (Continued)
Bank Signal 1A-30 GNDIO0 1B-30/CLK_OUT0 1B-28 1B-26 1B-24 1B-22 1B-20 1B-18 1B-16 1B-14 1B-12 GNDIO0 1B-10 1B-8 1B-6/PLL_RST0 1B-4/PLL_FBK0 1B-2 1B-0 2B-0 2B-2 2B-4 2B-6 2B-8 2B-10 GNDIO1 2B-12 2B-14 2B-16 2B-18 2B-20 2B-22 2B-24 2B-26 2B-28 2B-30 GNDIO1 2A-30 2A-28 2A-26 2A-24 2A-22 2A-20 fpBGA fpBGA Bank Signal 2A-18 2A-16 2A-14 2A-12 GNDIO1 2A-10 2A-8 2A-6 2A-4 2A-2 2A-0 3B-0 3B-2 3B-4 3B-6 3B-8 3B-10 GNDIO1 3B-12 3B-14 3B-16 3B-18 3B-20 3B-22 3B-24 3B-26 3B-28 3B-30 3A-30 3A-28 GNDIO1 3A-26 3A-24 3A-22 3A-20 3A-18 3A-16 3A-14 3A-12 GNDIO1 3A-10 3A-8 3A-6 fpBGA fpBGA
Lattice Semiconductor
ispMACH 5000VG Family Data Sheet
ispMACH 51024VG Logic Signal Connections (Continued)
Bank Signal 3A-4 3A-2 3A-0 3D-0 3D-2 GNDIO1 3D-4 3D-6 3D-8 3D-10 3D-12 3D-14 3D-16 3D-18 3D-20 3D-22 3D-24 3D-26 GNDIO1 3D-28 3D-30 3C-0 3C-2 3C-4 3C-6 3C-8 3C-10 3C-12 3C-14/VREF1 3C-16 3C-18 GNDIO1 3C-20 3C-22 3C-24 3C-26 3C-28 3C-30 4C-30 4C-28 4C-26 4C-24 4C-22 fpBGA AA10 AB10 AA11 AB11 AB12 fpBGA AF10 AH10 AG11 AJ10 AF12 AH11 AK10 AJ11 AK11 AH12 AJ12 AK12 AH13 AJ13 AK13 AK18 AK19 AJ19 AH19 AK20 Bank Signal 4C-20 GNDIO2 4C-18 4C-16 4C-14 4C-12/VREF2 4C-10 4C-8 4C-6 4C-4 4C-2 4C-0 4D-30 4D-28 GNDIO2 4D-26 4D-24 4D-22 4D-20 4D-18 4D-16 4D-14 4D-12 4D-10 4D-8 4D-6 4D-4 GNDIO2 4D-2 4D-0 4A-0 4A-2 4A-4 4A-6 4A-8 4A-10 GNDIO2 4A-12 4A-14 4A-16 4A-18 4A-20 4A-22 fpBGA AA12 AB13 AA13 AB14 AA14 AB15 AB16 AA15 AB17 AA16 AB18 AB19 AB20 AA18 AA19 AB21 AA20 fpBGA AJ20 AK21 AH20 AF19 AJ21 AG20 AK22 AH21 AJ22 AK23 AH22 AJ23 AK24 AF21 AG22 AH23 AJ24 AK25 AH24 AJ25 AK26 AJ26 AH25 AG24 AF23 AK27 AK28 AJ27 AH26 AE23 AK29 AJ28 AH27 AG26 AF25 AJ29 AG27 AJ30 AH29
Lattice Semiconductor
ispMACH 5000VG Family Data Sheet
ispMACH 51024VG Logic Signal Connections (Continued)
Bank Signal 4A-24 4A-26 GNDIO2 4A-28 4A-30 4B-30 4B-28 4B-26 4B-24 4B-22 4B-20 4B-18 4B-16 4B-14 4B-12 GNDIO2 4B-10 4B-8 4B-6 4B-4 4B-2 4B-0 5A-0 5A-2 5A-4 5A-6 5A-8 5A-10 GNDIO2 5A-12 5A-14 5A-16 5A-18 5A-20 5A-22 5A-24 5A-26 5A-28 5A-30 GNDIO2 5B-30 5B-28 5B-26 fpBGA AA22 fpBGA AE25 AG28 AF27 AE26 AH30 AG29 AF28 AG30 AF29 AC25 AE28 AF30 AD27 AE29 AC26 AD28 AE30 AD29 AC28 AD30 AC29 AB27 AC30 AB28 AA26 AB29 AB30 AA28 AA29 AA30 Bank Signal 5B-24 5B-22 5B-20 5B-18 5B-16 5B-14 5B-12 GNDIO2 5B-10 5B-8 5B-6 5B-4 5B-2 5B-0 6B-0 6B-2 6B4/PLL_FBK1 6B6/PLL_RST1 6B-8 6B-10 GNDIO3 6B-12 6B-14 6B-16 6B-18 6B-20 6B-22 6B-24 6B-26 6B-28 6B-30/CLK_OUT1 GNDIO3 6A-30 6A-28 6A-26 6A-24 6A-22 6A-20 6A-18 6A-16 6A-14 6A-12 GNDIO3 fpBGA fpBGA
Lattice Semiconductor
ispMACH 5000VG Family Data Sheet
ispMACH 51024VG Logic Signal Connections (Continued)
Bank Signal 6A-10 6A-8 6A-6 6A-4 6A-2 6A-0 7B-0 7B-2 7B-4 7B-6 7B-8 7B-10 GNDIO3 7B-12 7B-14 7B-16 7B-18 7B-20 7B-22 7B-24 7B-26 7B-28 7B-30 7A-30 7A-28 GNDIO3 7A-26 7A-24 7A-22 7A-20 7A-18 7A-16 7A-14 7A-12 GNDIO3 7A-10 7A-8 7A-6 7A-4 7A-2 7A-0 7D-0 7D-2 fpBGA fpBGA Bank Signal GNDIO3 7D-4 7D-6 7D-8 7D-10 7D-12 7D-14 7D-16 7D-18 7D-20 7D-22 7D-24 7D-26 GNDIO3 7D-28 7D-30 7C-0 7C-2 7C-4 7C-6 7C-8 7C-10 7C-12/VREF3 7C-14 7C-16 7C-18 GNDIO3 7C-20 7C-22 7C-24 7C-26 7C-28 7C-30 GCLK0 GCLK1 GCLK2 GCLK3 GOE0 GOE1 RESETB fpBGA fpBGA
Lattice Semiconductor
ispMACH 5000VG Family Data Sheet
ispMACH 51024VG Logic Signal Connections (Continued)
Bank Signal fpBGA fpBGA
Lattice Semiconductor
ispMACH 5000VG Family Data Sheet
Signal Configuration
ispMACH 5768VG 256-ball fpBGA
I/O/
PLL_FBK1
VCCO3
I/O/
PLL_RST1
I/O/
CLK_OUT1
VCCO3
I/O/ VREF3
VCCO0
I/O/
CLK_OUT0
VCCO0
I/O/
PLL_FBK0
I/O/
PLL_RST0
VCCO3
I/O/
VREF0
VCCO0
VCCP1 GOE1 GCLK2 GCLK3
GNDP0 GNDP1
GCLK0
VCCP0
GOE0
RESETB
I/O/
VREF2
GCLK1 VCCJ
VCCO2
VCCO2
VCCO1
VCCO2
I/O/
VREF1
VCCO1
VCCO1
ispMACH 5768VG
Bottom View
Note: Ball indicator side package.
256fpBGA/5768VG
Lattice Semiconductor
ispMACH 5000VG Family Data Sheet
Signal Configuration
ispMACH 5768VG 51024VG 484-ball fpBGA
I/O/
VREF3
VREF0
VCCO3
VCCO0
VCCO3
VCCO0
VCCO3
VCCO3
VCCO3
VCCO0
VCCO0
VCCO0 I/O/
CLK_OUT0
VCCO3
VCCO0
VCCO3 I/O/
CLK_OUT1
VCCO0
VCCO3
VCCO0 I/O/
PLL_RST0
GNDP1 VCCP0 GNDP0
I/O/
PLL_RST1
VCCP1
I/O/
PLL_FBK0
I/O/
PLL_FBK1
GCLK3 VCCO2 GCLK2
GCLK0 VCCO1 VCCJ
VCCO1
RESETB
GOE0 GOE1 GCLK1
I/O/ VREF1
VCCO1
VCCO2 VCCO2
VCCO1
VCCO2
I/O/ VREF2
VCCO1
VCCO2
ispMACH 5768VG 51024VG
Bottom View
connected active signals, GND. Note: Ball indicator side package.
484BGA/51024VG
Lattice Semiconductor
ispMACH 5000VG Family Data Sheet
Signal Configuration
ispMACH 51024VG 676-ball fpBGA
I/O/ VREF0
I/O/
PLL_RST0
I/O/
CLK_OUT1
I/O/
CLK_OUT0
VCCO3
VCCO0
VCCO0 VCCO0
VCCO3
VCCO3
VCCO3
I/O/ VCCO3 VREF3
VCCO0
VCCO0
VCCO3
VCCO3
VCCO0
VCCO0
VCCO3
VCCO0
VCCO3
VCCO0
I/O/
VCCP0
I/O/
VCCP1
I/O/
PLL_FBK0
GCLK3 GNDP1
PLL_RST1 PLL_FBK1
GOE1 GCLK2
GNDP0 GCLK0
GOE0 RESETB
GCLK1
VCCJ
VCCO2
VCCO1 VCCO1
VCCO2
VCCO2
VCCO1
VCCO2 VCCO2
ispMACH 51024VG
Bottom View
VCCO2 VCCO1
VCCO1
VCCO2
VCCO1
VCCO2
VCCO1
VCCO2
VCCO1
VCCO1
I/O/ VREF2
I/O/ VREF1
676BGA/51024VG
connected active signals, GND. Note: Ball indicator side package.
Lattice Semiconductor
ispMACH 5000VG Family Data Sheet
Part Number Description
XXXXXVG FXXX
Device Family Device Number 5768 Macrocells 51024 1,024 Macrocells Speed 5.0ns 7.5ns 10ns 12ns*
*Industrial grade only.
Device Status Blank Final production Engineering Samples Grade Commercial Industrial Package F256 256-Ball fpBGA F484 484-Ball fpBGA F676 676-Ball fpBGA
0212/ispm5vg
Ordering Information
Commercial
Part Number LC51024VG-5F484C LC51024VG-75F484C LC51024VG-10F484C LC51024VG-5F676C LC51024VG-75F676C LC51024VG-10F676C LC5768VG-5F256C LC5768VG-75F256C LC5768VG-10F256C LC5768VG-5F484C LC5768VG-75F484C LC5768VG-10F484C Package fpBGA fpBGA fpBGA fpBGA fpBGA fpBGA fpBGA fpBGA fpBGA fpBGA fpBGA fpBGA Count Macrocells 1024 1024 1024 1024 1024 1024 Voltage
Note: ispMACH 5000VG family dual-marked with both Commercial Industrial grades. Commercial speed grade speed grade faster (i.e. LC51024VG-75F484C) than Industrial speed grade (i.e. LC51024VG-10F484I).
Lattice Semiconductor
Industrial
Part Number LC51024VG-75F484I LC51024VG-10F484I LC51024VG-12F484I LC51024VG-75F676I LC51024VG-10F676I LC51024VG-12F676I LC5768VG-75F256I LC5768VG-10F256I LC5768VG-12F256I LC5768VG-75F484I LC5768VG-10F484I LC5768VG-12F484I Package fpBGA fpBGA fpBGA fpBGA fpBGA fpBGA fpBGA fpBGA fpBGA fpBGA fpBGA fpBGA Count
ispMACH 5000VG Family Data Sheet
Macrocells 1024 1024 1024 1024 1024 1024
Voltage
Note: ispMACH 5000VG family dual-marked with both Commercial Industrial grades. Commercial speed grade speed grade faster (i.e. LC51024VG-75F484C) than Industrial speed grade (i.e. LC51024VG-10F484I).
Further Information
addition this data sheet, following technical notes helpful when designing with ispMACH 5000VG family: ispMACH 5000VG sysIO Design Usage Guidelines (TN1000) ispMACH 5000VG Timing Model Design Usage Guidelines (TN1001) Power Estimation ispMACH 5000VG Devices (TN1002) ispMACH 5000VG Usage Guidelines (TN1003)

3.3V In-System Programmable SuperBIG, SuperWIDE High Density PLDs

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