ispMACH 4000 Industry's Fastest Lowest Power CPLDs CPLD Architect
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IN-SYSTEM PROGRAMMABLE HIGH PERFORMANCE POWER
ispMACH 4000
Industry's Fastest Lowest Power CPLDs CPLD Architecture Couples SuperFAST Performance Power
ispMACH4000 industry's fastest lowest power ISPComplex Programmable Logic Device (CPLD) Family. With SuperFAST2.5ns pin-to-pin delay dynamic power, ispMACH 4000 Family ultimate solution high performance systems. ispMACH 4000 family contains separate subfamilies, supporting 2.5V (ispMACH 4000B), industry's first 1.8V CPLD family (ispMACH 4000C). Utilizing Lattice's latest generation UltraMOS® process technology, ispMACH 4000 architecture combines best features Lattice's ispMACH4A ispLSI® 2000 families provides high speed, dynamic power consumption, enhanced logic control, flexible I/O. ispMACH 4000 Family fully supported Lattice's easy-to-use powerful ispLEVERdesign software, plus wide range popular third-party tools. Designing with ispMACH 4000 devices quick easy using leading synthesis simulation tools from Exemplar Logic, Synplicity Model Technology.
Features Benefits
ispMACH 4000 Block Diagram
CLK0/I CLK1/I CLK2/I CLK3/I VCCO0 GOE0 GOE1
SuperFAST
SuperFAST Performance Pin-to-Pin Delay System Performance
Industry's Lowest Power Consumption 1.8V Core Dynamic Power Static Current 1-3.5 (1.8V ispMACH 4000B) 9-11 (2.5V ispMACH 4000C)
VCCO1
Generic Logic Block
Generic Logic Block
Bank
Global Routing Pool
Bank
Ease Design Excellent First-Time Refit Capability Global Clocks Inputs Logic Block Product Terms (PT) Output Locking Density Migration Flexible Control Clocking Enhanced Support Fast, SpeedLockingTM, Wide Paths Easy System Integration Operation with 1.8V 2.5V Supplies 1.8V, 2.5V, 3.3V Support IEEE 1532 In-System Programmable (ISPTM) IEEE 1149.1 Boundary Scan Test Open Drain Output Flexible Interface Capability Programmable Pull-Up Bus-Keeper Inputs Socketing Capability 3.3V Compatible Programmable Output Slew Rate
Output Routing Pool
Output Routing Pool
Block
Block
Output Routing Pool
Output Routing Pool
Block
Block
Generic Logic Block
Generic Logic Block
ispMACH 4000 Architecture
Generic Logic Block (GLB)
CLK0 CLK1 CLK2 CLK3
Global Routing Pool (GRP)
Macrocell
Power-up Reset Shared Initialization Initialization (optional) Initialization/CE (optional)
Clock Generator
Macrocell Macrocell Macrocell Macrocell Macrocell Macrocell Macrocell
1+OE
Delay From Logic Allocator
From Cell
Macrocell Feedback Signals
1+OE 1+OE
D/T/L
Inputs from Segment Routing Pool
Array
Inputs Product Terms
Logic Allocator
Macrocell Macrocell Macrocell Macrocell Macrocell Macrocell Macrocell Macrocell Macrocell
Output Routing Pool 1+OE (ORP)
1+OE 1+OE 1+OE 1+OE
Single
Block CLK0 Block CLK1 Block CLK2 Block CLK3 Clock (optional) Shared Clock
Shared Clock Shared Initialization
Product Term Output Enable Sharing
Flexible efficient clock control scheme ensures easy implementation with variety coding styles.
Cell Flexible Product Term Allocation
SuperFAST Product Term Fast Path high performance functions
5-PT Fast Path from
Enhanced Output Enable control selections each
VCCO
Fast Path Speed Locked Path
From
VCCO
From Macrocell
Macrocell
Cluster
Individual P-Term Allocator
Cluster Allocator
from
from
1.8V/2.5V/3.3V Mixed Voltage Support
Bank power supply 1.8V, 2.5V 3.3V. Input standard supported independent VCCO.
VCCO
SpeedLockedPath Product Terms
Wide Path
from from
Bank
Macrocell Cluster Individual P-Term Allocator Cluster Allocator from from
CLK0 CLK1
Logic Core
CLK3 CLK2
Wide Product Term Path Product Terms
Bank
VCCO
Each Bank VCCO
ispMACH 4000 Applications
Network Core Router SuperFAST performance ispMACH 4000 perfect implementing high speed data path control applications. this application, ispMACH 4256 implements: MPC765 SDRAM Data Pathway Controller Finite State Machine JTAG Control MUX/DEMUX ispMACH 4000 Strengths High Density I/Os Cost Effective Boundary Scan Improves Testability Design Simplicity
SDRAM Lattice ispGDX Processor
SDRAM
SDRAM
ispMACH 4256
SDRAM
Flash Memory
Lattice ispGDX
Bridge
Optical Transmission Processor Module ispMACH 4000 excellent solution multivoltage systems high-speed applications. this optical transmission application, ispMACH 4384 performs: Complex Data Path Control Dedicated Interrupts Watchdog Timer LED/Alarm Controls Arbitration Signals Chip Selects ASICs ispMACH 4000 Strengths Speed Socketing Capability Multi-Voltage Support Output Enable Control each
Memory Processor Module Interface
Optical ASSP
MPC8260
ispMACH 4384
Optical ASSP
ispGDX Service Managment
OC12 Edge Router in-system programmability, non-volatility very high speed ispMACH 4000 devices make them superior choice interface applications. this OC12 edge router application, ispMACH 4384 performs following functions: PowerPCTM, ASIC SDRAM Interface ispGDX® Data Flow Control Control Registers SDRAM Controller Multiple Interface Options: DS3, OC-3, OC-12, Ethernet Gigabit Ethernet ispMACH 4000 Strengths High Speed Package Migration In-System Programmable Different Interface Options
PowerPC
ispMACH 4384
ASIC ispGDX
ispMACH 4256
SDRAM
PowerPC
ispMACH 4000 Family Attributes (Preliminary)
Family Member ispMACH 4032 ispMACH 4064 Macrocells
User Options
30/32 30/32/64
(ns)
(ns)
(ns)
1.75 1.75
fMAX (MHz)
1.8/2.5 1.8/2.5
Standby Power 1.8V (mA)
Pins/ Package
44-pin TQFP 48-pin TQFP 44-pin TQFP 48-pin TQFP 100-pin TQFP 100-pin TQFP 128-pin TQFP 100-pin TQFP 176-pin TQFP 256-ball fpBGA* 176-pin TQFP 256-ball fpBGA 176-pin TQFP 256-ball fpBGA
ispMACH 4128 ispMACH 4256
64/92 64/128/160
1.8/2.5 1.8/2.5
ispMACH 4384 ispMACH 4512
options
128/192 128/208
1.8/2.5 1.8/2.5
ispMACH 4000 Advanced Packaging
Industry's Lowest Power Consumption
120mA
Less Power
60mA
Less Power
180mA
titi
ispMACH 4256
(2.5V, 1.8V)
0MHz
100MHz
200MHz
300MHz
Frequency
Superior Performance
400MHz Faster 300MHz
ispMACH 4000
Speed
200MHz
Competition
100MHz
Number Macrocells
Packages shown actual size. Dimensions refer package body size.
Applications Support
1-800-LATTICE (528-8423) (408) 826-6002 techsupport@latticesemi.com
www.latticesemi.com
December 2001 Order I01xx
Copyright 2001 Lattice Semiconductor Corporation. Lattice Semiconductor, (stylized) Lattice Semiconductor Corp., Lattice (design), ISP, ispMACH, ispLSI, ispDesignEXPERT, ispGDX, ispJTAG, sysIO, sysCLOCK, SpeedLocked, SpeedLocking, SuperBIG, SuperFAST, SuperWIDE UltraMOS either registered trademarks trademarks Lattice Semiconductor Corporation United States and/or other countries. Other product names used this publication identification purposes only trademarks their respective companies.
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