In-System Programmable High Density Features HIGH-DENSITY PROGRAM
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ispLSI 3160
In-System Programmable High Density Features
HIGH-DENSITY PROGRAMMABLE LOGIC Pins 7000 Gates Registers High Speed Global Interconnect Wide Input Gating Fast Counters, State Machines, Address Decoders, etc. Small Logic Block Size Random Logic HIGH PERFORMANCE E2CMOS® TECHNOLOGY fmax Maximum Operating Frequency Propagation Delay Compatible Inputs Outputs Electrically Erasable Reprogrammable Non-Volatile 100% Tested Time Manufacture Unused Product Term Shutdown Saves Power IN-SYSTEM PROGRAMMABLE In-System Programmability (ISPTM) Using Lattice Boundary Scan Test (IEEE 1149.1) Protocol Increased Manufacturing Yields, Reduced Time-toMarket, Improved Product Quality Reprogram Soldered Devices Faster Debugging 100% IEEE 1149.1 BOUNDARY SCAN COMPATIBLE OFFERS EASE FAST SYSTEM SPEED PLDs WITH DENSITY FLEXIBILITY FIELD PROGRAMMABLE GATE ARRAYS Complete Programmable Device Combine Glue Logic Structured Designs Five Dedicated Clock Input Pins Synchronous Asynchronous Clocks Programmable Output Slew Rate Control Minimize Switching Noise Flexible Placement Optimized Global Routing Pool Provides Global Interconnectivity ispDesignEXPERT- LOGIC COMPILER COMPLETE DEVICE DESIGN SYSTEMS FROM SYNTHESIS THROUGH IN-SYSTEM PROGRAMMING Superior Quality Results Tightly Integrated with Leading Vendor Tools Productivity Enhancing Timing Analyzer, Explore Tools, Timing Simulator ispANALYZER- UNIX Platforms
Functional Block Diagram
Boundary Scan
Array
Array
Twin
Array
Global Routing Pool (GRP)
Description
ispLSI 3160 High-Density Programmable Logic Devices containing Registers, Universal pins, five Dedicated Clock Input Pins, five Output Routing Pools (ORP) Global Routing Pool (GRP) which allows complete inter-connectivity between these elements. ispLSI 3160 features in-system programmability in-system diagnostic capabilities. ispLSI 3160 offers non-volatile reprogrammability logic, well interconnect provide truly reconfigurable systems. basic unit logic ispLSI 3160 device Twin Generic Logic Block (Twin GLB) labelled A1.E3. There total these Twin GLBs ispLSI 3160 device. Each Twin inputs, programmable array OR/Exclusive-OR Arrays, eight outputs which configured either combinatorial registered. Twin inputs come from GRP.
Copyright 1999 Lattice Semiconductor Corp. brand product names trademarks registered trademarks their respective holders. specifications information herein subject change without notice.
LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A. Tel. (503) 268-8000; 1-800-LATTICE; (503) 268-8556; http://www.latticesemi.com
December 2003
3160_09
Specifications ispLSI 3160
Functional Block Diagram
Figure ispLSI 3160 Functional Block Diagram
BSCAN/ispEN
GOE0
GOE1
Generic Logic Blocks
Input
Boundary Scan
TMS/MODE
TCK/SCLK
TDI/SDI TRST TDO/SDO
Input
Input
Global Routing Pool (GRP)
Input
Input
Megablock
RESET
0139isp/3160
IOCLK IOCLK
Specifications ispLSI 3160
Description (Continued)
local logic block outputs brought back into they connected inputs other logic block device. device also cells, each which directly connected pin. Each cell individually programmed combinatorial input, registered input, latched input, output bidirectional with 3-state control. signal levels compatible voltages output drivers source sink Each output programmed independently fast slow output slew rate minimize overall output switching noise. cells grouped into sets bits. Pairs these groups associated with logic Megablock through ORP. Each Megablock able provide Product Term Output Enable (PTOE) signal which globally distributed cells. PTOE generated Megablock. Each cell select seven available (two Global five PTOEs). Four Twin GLBs, cells ORPs connected together make logic Megablock. Megablock defined resources that shares. outputs pair Twin GLBs connected cells ORP. ispLSI 3160 device contains five these Megablocks. inputs outputs from Twin GLBs inputs from bidirectional cells. these signals made available inputs Twin GLBs. Delays through have been equalized minimize timing skew logic glitching. Clocks ispLSI 3160 device provided through five dedicated clock pins. five pins provide three clocks Twin GLBs clocks cells. table below lists attributes device along with number resources available. additional feature ispLSI 3160 Boundary Scan capability, which composed cells connected between on-chip system logic device's input output pins. pins have associated boundary scan registers, with 3-state using three boundary scan registers inputs using one. ispLSI 3160 supports IEEE 1149.1 mandatory instructions, which include BYPASS, EXTEST SAMPLE.
Attributes ispLSI 3160
Attribute Twin GLBs Registers Pins Global Clocks Global Test Quantity
Table 1-0003A/3160
Specifications ispLSI 3160
Absolute Maximum Ratings
Supply Voltage -0.5 +7.0V Input Voltage Applied -2.5 +1.0V Off-State Output Voltage Applied -2.5 +1.0V Storage Temperature 150°C Case Temp. with Power Applied 125°C Max. Junction Temp. (TJ) with Power Applied 150°C
Stresses above those listed under "Absolute Maximum Ratings" cause permanent damage device. Functional operation device these other conditions above those indicated operational sections this specification implied (while programming, follow programming specifications).
Recommended Operating Condition
SYMBOL PARAMETER Ambient Temperature Supply Voltage Input Voltage Input High Voltage MIN. 4.75 MAX. 5.25 UNITS
Table 2-0005/3160
Capacitance (TA=25°C,f=1.0 MHz)
SYMBOL PARAMETER Capacitance Clock Capacitance TYPICAL UNITS TEST CONDITIONS 5.0V, VI/O 2.0V 5.0V, 2.0V
Table 2-0006/3160
Data Retention Specifications
PARAMETER Data Retention ispLSI Erase/Reprogram Cycles MINIMUM 10000 MAXIMUM UNITS Years Cycles
Table 2-0008/3160
Specifications ispLSI 3160
Switching Test Conditions
Input Pulse Levels Input Rise Fall Time Input Timing Reference Levels Output Timing Reference Levels Output Load 3-state levels measured 0.5V from steady-state active level. 3.0V -125 Others 1.5V 1.5V Figure
Table 2-0003/3160
Figure Test Load
Device Output Test Point
Output Load conditions (See Figure
TEST CONDITION Active High Active Active High -0.5V Active +0.5V 35pF 35pF 35pF
Table 0004A
includes Test Fixture Probe Capacitance.
0213A/3160
Electrical Characteristics
Over Recommended Operating Conditions
SYMBOL PARAMETER Output Voltage Output High Voltage Input Leakage Current Input High Leakage Current Bscan/ispEN Input Leakage Current Active Pull-Up Current Output Short Circuit Current Operating Power Supply Current CONDITION IOL= (Max.) 3.5V VOUT 0.5V 0.0V, 3.0V fTOGGLE MIN. TYP.
MAX. UNITS -150 -150 -200
IIL-isp IIL-PU IOS1 ICC2,4
Table 2-0007/3160
output time maximum duration second. VOUT 0.5V selected avoid test problems tester ground degradation. Characterized 100% tested. Measured using 16-bit counters. Typical values 25°C. Maximum varies widely with specific device configuration operating frequency. Refer Power Consumption section this datasheet Thermal Management section Lattice Semiconductor Data Book CD-ROM estimate maximum ICC.
Specifications ispLSI 3160
External Switching Characteristics1,
Over Recommended Operating Conditions
PARAMETER TEST5 COND.
DESCRIPTION1
-125
-100 87.0 10.0 13.0 13.5 15.0 15.0 12.0 12.0
15.0 18.0 10.0 15.0 18.0 18.0 12.0 12.0 15.0 15.0
MIN. MAX. MIN. MAX. MIN. MAX. 10.0 10.0 12.0 12.0
UNITS
tpd1 tpd2 fmax fmax (Ext.) fmax (Tog.) tsu1 tco1 tsu2 tco2 trw1 tptoeen tptoedis tgoeen tgoedis ttoeen ttoedis tsu3
Data Prop. Delay, Bypass, Bypass Data Propagation Delay Clock Frequency with Internal Feedback Clock Frequency, Toggle
95.0
70.0 50.0 83.0 11.0 12.0
Clock Freq. with Ext. Feedback,1/(tsu2 tco1) Reg. Setup Time before Clock, bypass Reg. Clock Output Delay, bypass Reg. Hold Time after Clock, bypass Reg. Setup Time before Clock Reg. Clock Output Delay Reg. Hold Time after Clock Ext. Reset Output Delay Ext. Reset Pulse Duration Input Output Enable Input Output Disable Global Output Enable Global Output Disable Test Output Enable Test Output Disable Ext. Sync. Clock Pulse Duration, High Ext. Sync. Clock Pulse Duration, Reg. Setup Time before Ext. Sync. Clock (Y3, Reg. Hold Time after Ext. Sync. Clock (Y3,
Unless noted otherwise, parameters PTXOR path ORP. Refer Timing Model this data sheet further details. Standard 16-bit counter using feedback. fmax (Toggle) less than 1/(twh twl). This allow clock duty cycle other than 50%. Reference Switching Test Conditions section.
Timing Ext.3160.eps
Specifications ispLSI 3160
Internal Timing Parameters1
Over Recommended Operating Conditions
PARAMETER
DESCRIPTION
-125 MIN. -1.6 -0.2 MAX.
-100 MIN. -1.6 -0.2 MAX.
MIN. -2.5 MAX. 13.5
UNITS
Inputs
tiobp tiolat tiosu tioh tioco tior
Register Bypass Latch Delay Register Setup Time before Clock Register Hold Time after Clock Register Clock Delay Register Reset Delay Delay Product Term Bypass Path Delay (Comb.) Product Term Bypass Path Delay (Reg.) Product Term/XOR Path Delay Product Term/XOR Path Delay Adjacent Path Delay3 Register Bypass Delay Register Setup Time before Clock Register Hold Time after Clock Register Clock Output Delay Register Reset Output Delay Product Term Reset Register Delay Product Term Output Enable Cell Delay Product Term Clock Delay Delay Bypass Delay
tgrp
t4ptbp t4ptbr t1ptxor t20ptxor txoradj tgbp tgsu tgco tgro tptre tptoe tptck torp torpbp
Internal Timing Parameters tested reference only. Refer Timing Model this data sheet further details. adjacent path only used hard macros.
Timing Int.3160.eps
Specifications ispLSI 3160
Internal Timing Parameters1
Over Recommended Operating Conditions
PARAMETER
DESCRIPTION
-125 MIN. MAX. 11.6
-100 MIN. MAX. 12.6
MIN. MAX. 13.3
UNITS
Outputs
tobs toen todis
Clocks
Output Buffer Delay Output Buffer Delay, Slew Limited Adder Cell Output Enabled Cell Output Disabled Clock Delay, Global Line Clock Delay, Cell Global Clock Line Global Reset Registers Global Buffer Test Buffer
tgy0/1/2 tioy3/4
Global Reset
tgoe ttoe
Internal Timing Parameters tested reference only. Refer Timing Model this data sheet further details.
Timing Int.2.3160.eps
Specifications ispLSI 3160
ispLSI 3160 Timing Model
Cell Feedback Cell
(Input)
Bypass Input Register
Bypass Delays
Bypass Delay
Bypass Delay
#46,
(Output)
Reset Y3,4
#48,
Control
Y0,1,2
GOE0,1
0902/3160
Derivations tsu, from Product Term Clock
0.8ns 4.2ns 10.1ns Logic Clock (min) (tiobp tgrp t20ptxor) (tgsu) (tiobp tgrp tptck(min)) (#24+ #30+ #34) (#37) (#24+ #30+ #43) (0.8 4.0) (-0.2) (0.8 3.0) Clock (max) Logic (tiobp tgrp tptck(max)) (tgh) (tiobp tgrp t20ptxor) (#24+ #30+ #43) (#38) (#24+ #30+ #34) (0.8 3.6) (4.6) (0.8 4.0) Clock (max) Output (tiobp tgrp tptck(max)) (tgco) (torp tob) (#24 #43) (#39) (#44 #46) (0.8 3.6) (1.1) (1.2 1.6)
Table 2-0042/3160
Note: Calculations based upon timing specifications ispLSI 3160-125L.
Specifications ispLSI 3160
Power Consumption
Power consumption ispLSI 3160 device depends primary factors: speed which device operating number product terms used. Figure Typical Device Power Consumption fmax Figure shows relationship between power operating speed.
ispLSI 3160
(mA)
fmax (MHz)
Notes: Configuration 16-bit Counters Typical Current
estimated ispLSI 3160 using following equation: 0.73) nets Max. freq 0.0105) where: Number Product Terms used design nets Number Signals used device Max. freq Highest Clock Frequency device estimate based typical conditions (VCC 5.0V, room temperature) assumption loads average exists. These values estimates only. Since value sensitive operating conditions program device, actual should verified.
0127/3160
Package Thermal Characteristics
ispLSI 3160-125LB272, strongly recommended that actual verified ensure that maximum junction temperature (TJ) with power supplied exceeded. Depending specific logic design clock speed, airflow required satisfy maximum allowable junction temperature (TJ) specification. Please refer Thermal Management section Lattice Semiconductor Data Book CD-ROM additional information calculating
Specifications ispLSI 3160
Signal Descriptions
Signal Name GOE0, GOE1 RESET BSCAN/ispEN Description Global Output Enable input pins. Input/Output Pins These general purpose pins used logic array. Test Output Enable pin. This tristates pins when logic driven. Active Reset which resets registers device. Dedicated Clock inputs. These clock inputs connected clock inputs GLBs device. Dedicated Clock input. This clock input connected clock inputs cells device. Input Dedicated in-system programming enable input pin. When this high, BSCAN controller pins TMS, TDI, enabled. When this brought low, State Machine control pins MODE, SDI, SCLK enabled. High-to-low transition this will device programming mode pins high-Z state. Input This performs functions. Test Data input when ispEN logic high. When ispEN logic low, functions input load programming data into device. also used control pins State Machine. Input This performs functions. Test Clock input when ispEN logic high. When ispEN logic low, functions clock Serial Shift Register. Input This performs functions. Test Mode Select input when ispEN logic high. When ispEN logic low, functions control operation State Machine. Input Test Reset, active reset Boundary Scan State Machine. Output This performs functions. When ispEN logic low, functions read data. When ispEN high, functions Test Data Out. Ground (GND) Connect.
TDI/SDI
TCK/SCLK TMS/MODE TRST TDO/SDO
Signal Locations
Signal GOE0, GOE1 RESET BSCAN/ispEN TDI/SDI TCK/SCLK TMS/MODE TRST/NC1 TDO/SDO 133, 104, 115, 131, 146, 157, 169, 183, 196, 208-Pin PQFP J19, J20, K19, K20, L20, D13, D17, H17, J10, J11, J12, K10, K11, K12, L10, L11, L12, M10, M11, M12, N17, U13, A10, A14, A19, A20, B10, B14, B16, B17, B18, B19, C16, F18, F19, K17, K18, P20, R20, U11, U19, V11, V14, V18, V19, W11, W15, W17, W19, W20, Y10, Y11, Y18, 272-Ball
132, 130, 129, 128,
118, 143, 162, 181, D11, D15, F17, L17, R17, U10, 180, 182,
pins connected active signals, GND.
Specifications ispLSI 3160
Locations
Signal PQFP Signal PQFP Signal PQFP Signal PQFP Signal PQFP
Specifications ispLSI 3160
Configuration
ispLSI 3160 208-Pin PQFP (with Heat Spreader) Pinout Diagram
TDO/SDO
TMS/MODE TCK/SCLK TDI/SDI BSCAN/ispEN RESET 1TRST/NC
ispLSI 3160
View
GOE1 GOE0
208-MQFP/3160
pins connected active signal, GND.
Specifications ispLSI 3160
Signal Configuration
ispLSI 3160 272-Ball Signal Diagram
TDO/
ispLSI 3160
Bottom View
BSCAN/ ispEN
TDI/
TCK/ TMS/ SCLK MODE TRST/ RESET
connected active signals, GND. Note: Ball indicator side package.
Specifications ispLSI 3160
Part Number Description
ispLSI
Device Family Device Number Speed fmax fmax fmax
3160 XXXX
Grade Blank Commercial Package PQFP (with Heat Spreader) B272 Power
0212B/3160
Ordering Information
COMMERCIAL
FAMILY fmax (MHz) ispLSI (ns) ORDERING NUMBER ispLSI 3160-125LQ ispLSI 3160-125LB272 ispLSI 3160-100LQ ispLSI 3160-100LB272 ispLSI 3160-70LQ ispLSI 3160-70LB272 PACKAGE 208-Pin PQFP 272-Ball 208-Pin PQFP 272-Ball 208-Pin PQFP 272-Ball
Table 2-0041B/3160
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