2.4GHz Very Phase Noise DS4875 ISSUE July 2001 Fea

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2.4GHz Very Phase Noise DS4875 ISSUE July 2001 Fea

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SP5748
2.4GHz Very Phase Noise
DS4875
ISSUE
July 2001
Features
Complete Single Chip System (for faster device refer SP5768) Optimised Phase Noise, with Comparison Frequencies Prescaler Selectable Reference Division Ratio Reference Frequency Output Selectable Charge Pump Current Integrated Loop Amplifier Switching Ports Power Replacement SP5658 SP5668 Power Consumption 110mW with Ports Downwards Software Compatible with SP5658 Protection min., MIL-STD-883B Method 3015 Cat.1 (Normal handling procedures should observed)
Ordering Information
SP5748/KG/MP1S (Tubes) SP5748/KG/MP1T (Tape Reel) SP5748/KG/QP1S (Tubes) SP5748/KG/QP1T (Tape Reel)
allows coarse tuning up-converter application fine tuning down-converter. Comparison frequencies obtained either from crystal controlled on-chip oscillator from external source. buffered reference frequency output also available drive second SP5748. device also contains switching ports.
Absolute Maximum Ratings
Supply voltage, differential input voltage input offset Port voltage Charge pump offset Varactor drive offset Crystal offset Buffered reference output Data, clock enable offset Storage temperature Junction temperature MP14 thermal resistance Chip ambient, Chip case, 255°C 1125°C 1150°C 81°C/W 27°C/W
Applications
Cable Tuning Systems Communications Systems
Description
SP5748 single chip frequency synthesiser designed tuning systems optimized phase noise with comparison frequencies MHz. designed downwards software compatible with SP5658. programmable divider contains front dual-modulus 416/17 functioning over full operating range
CRYSTAL
INPUT
13-BIT COUNT
REFERENCE DIVIDER
416/17
4-BIT COUNT CHARGE PUMP
CRYSTAL PUMP DRIVE
17-BIT LATCH DATA CLOCK ENABLE
6-BIT LATCH
DATA INTERFACE 3-BIT LATCH PORT/TEST MODE INTERFACE
PORT P1/OC PORT P0/OP
Figure SP5748 Block Diagram (MP14 pinout)
SP5748
CHARGE PUMP CRYSTAL CRYSTAL ENABLE DATA CLOCK PORT P1/OC PORT P0/OP
CHARGE PUMP CRYSTAL CRYSTAL ENABLE DATA CLOCK PORT P1/OC
DRIVE INPUT RFINPUT PORTP0/OP
5748
5748
DRIVE INPUT INPUT
MP14
Figure connections view
QP16
Electrical Characteristics
Test conditions (unless otherwise stated): Tamb 240°C 180°C, These characteristics guaranteed either production test design. They apply within specified ambient temperature supply voltage ranges unless otherwise stated. Note: numbers refer MP14 package. Value Characteristic Supply current input Frequency range Input voltage Input impedance Data, clock enable Input high voltage Input voltage Input current Hysteresis Clock rate timing Data Data hold Enable Enable hold Clock enable Charge pump Output current Output leakage Drive output current Crystal frequency External reference Input frequency Drive level Buffered reference output Output amplitude Output impedance 11,12 5,6,4 5,6,4 Vp-p Vp-p Vp-p VPIN1 Table VPIN1 TAMB 25°C VPIN14 Figure application Sinewave coupled 10nF blocking capacitor Sinewave coupled 10nF blocking capacitor coupled, Note 2-20MHz cont. Min. Typ. Max. Units Conditions
2400 mVrms 150MHz 2400MHz, Figure mVrms 80MHz 150MHz, Figure Figure
input conditions
SP5748
Electrical Characteristics (continued)
Value Characteristic Comparison frequency Equivalent phase noise phase detector division ratio Reference division ratio Output Ports Sink current Leakage current Min. Typ. 2148 131071 Max. Units Conditions
dBc/Hz 10kHz with 2MHz comparison from 4MHz crystal Table Note VPORT VPORT
NOTES Reference output disabled connecting VCC. Output ports high impedance power-up, with data, clock enable logic `0'.
Functional description
SP5748 contains elements necessary, with exception frequency reference, loop filter external high voltage transistor, control varicap tuned local oscillator, forming complete frequency synthesised source. device allows operation with high comparison frequency fabricated high speed logic, which enables generation loop with excellent phase noise performance, even with high comparison frequencies. block diagram shown Figure packages allocations Figure SP5748 controlled standard 3-wire comprising data, clock enable inputs. programming word contains bits, which used port selection, programmable divider ratio, bits select reference division ratio (bits R0-R2, Table bits charge pump current, bits (see Table remaining access test modes (bit Table 3)). programming data format shown Figure clock input disabled enable signal, data therefore only loaded into internal shift registers during enable high clocked into controlling buffers enable high transition. This load also synchronised with programmable divider giving smooth fine tuning. signal internal preamplifier, which provides gain reverse isolation from divider signals. output preamplifier 17-bit fully programmable counter, which MN+A architecture. counter bits counter bits. output programmable divider phase comparator where compared both phase frequency domain with comparison frequency. This frequency derived either from on-chip crystal controlled oscillator from external reference source. both cases reference frequency divided down comparison frequency reference divider which programmable into1 ratios described Table output phase detector feeds charge pump loop amplifier section, which when used with external high voltage transistor loop fiIter integrates current pulses into varactor line voltage. charge pump current setting described Table buffered crystal reference frequency suitable driving further synthesisers available from required this output disabled connecting VCC. programmable divider output divided fPD/2 comparison frequency, fCOMP, switched ports respectively switching device into test mode. test modes described Table
SP5748
j0.5
j0.2
1GHz
2j0.2
S11: Normalised
2j0.5
Figure input impedance
CLOCK
ENABLE
DATA
FREQUENCY DATA
Programmable divider ratio control bits Reference divider control bits (see Table Reference divider mode select (see Table Port control bits (see Table Charge pump current bits (see Table Test mode enable
Figure Data format
Charge pump current (µA) 6230 61000 6115 6500
18pF 39pF
SP5748
Table Charge pump current
Figure Crystal oscillator application
SP5748
Division ratio Test mode description Normal operation Charge pump sink Charge pump source Charge pump disable Port fCOMP, fPD/2
Table Test modes
(mVRMS INTO
OPERATING WINDOW
Table Reference divider control
1000 2400 FREQUENCY (MHz)
Figure Typical input sensitivity
1.6GHz 50-900MHz 1650-2400MHz SP5748
38.9MHz
SP5748
Figure Example double conversion from VHF/UHF frequencies
130V 13.3k
Optional application using on-chip crystal controlled oscillator
BCW31 2.2n
112V
TUNER OSCILLATOR OUTPUT
REFERENCE ENABLE CONTROL MICRO DATA CLOCK
5748
Figure Typical application SP5748
SP5748
Applications
generic Application Notes AN168 designing with synthesisers such SP5748 been written, covering aspects such loop filter design decoupling. This application note published Zarlink Semiconductor site http:/www.zarlink.com. generic test/demonstration board been produced which used SP5748; circuit diagram shown Figure with component values Table board used following purposes:
There ways achieving higher phase comparator sampling frequency: Reduce division ratio between reference source phase comparator higher reference source frequency. Approach preferred best performance since possible that noise floor reference osciliator degrade phase comparator performance reference division ratio very small. Loop bandwidth majority applications which SP5748 intended require loop filter bandwidth between 2kHz and10kHz. Typically phase noise will specified both 1kHz and10kHz offset. common practice arrange loop filter bandwidth such that 1kHz figure lies within loop bandwidth. Thus phase noise depends synthesiser comparator noise floor, rather than VCO. 10kHz offset figure should depend providing loop designed correctly, underdamped.
Measuring sensitivity performance. Indicating port function. Synthesising voltage controlled oscillator. Testing external reference. Measurement phase noise performance.
Reference source SP5748 offers optimal phase noise performance when operated with large step size. This fact that phase comparator noise within loop bandwidth 120log10 frequency (Phase comparator frequency
Assuming phase comparator noise floor flat irrespective sampling frequency, this means that best performance will achieved when overall Component Value/type 18pF 68pF 10nF 100nF 100nF 10pF 100pF 100pF 100pF 10nF 39pF 100pF
Component
Value/type HLMPK-150 HLMPK-150 DIP-2 BCW31 POS_2000 4MHz
Table Component values Figure
POWER CONNECTOR 130V
130V
VARACTOR
fitted normal operation 5748
INPUT
Figure SP5748 evaluation board
LED1
DATA
ENABLE
PORT OUTPUTS
tuning range 1370MHz 2000MHz
CLOCK LED2
COMP OUTPUT
SP5748
SP5748
view
Bottom view
Figure SP5748 evaluation board layout
SP5748
CHARGE PUMP
INPUTS DRIVE
Figure inputs
Figure Loop amplifier
PORT
Figure Enable, Data Clock inputs
Figure Output ports
CRYSTAL CRYSTAL
Figure Reference oscillator
Figure Reference output
Figure Input/output interface circuits
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2.4GHz Very Phase Noise DS4875 ISSUE July 2001 Fea

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