2.7GHz Controlled Synthesiser Preliminary Information DS4852 ISSU
|
|
|
Top Searches for this datasheet
SP5669
2.7GHz Controlled Synthesiser Preliminary Information
DS4852 ISSUE 1999
Complete 2.7GHz single chip system Compatible with offset requirements Optimised phase noise Selectable divide prescaler Selectable reference division ratio Selectable reference/comparison frequency output Selectable charge pump current Four selectable address 5-level compatible with SP5658 3-wire controlled synthesiser SP5659 synthesiser SP5659 synthesiser protection; (Normal handling procedures should observed)
Ordering Information
SP5669/KG/MP1S (Tubes) SP5669/KG/MP1T (Tape reel)
comparison frequency obtained either from on-chip crystal controlled oscillator, from external source. oscillator frequency Fref comparison frequency Fcomp switched REF/COMP output. This feature ideally suited providing reference frequency second synthesiser such double conversion tuner (see Fig. synthesiser controlled bus, responds four programmable addresses which selected applying specific voltage `address' input. This feature enables more synthesisers used system. device contains four switching ports P0-P3 5-level ADC. output read bus. device also contains varactor line disable chargepump disable facility.
Applications
Complete 2.7GHz single chip system Optimised phase noise
Description
SP5669 single chip frequency synthesiser designed tuning systems 2.7GHz offers step size compatible with offset requirements. preamplifier drives divide prescaler which disabled applications 2GHz, allowing direct interfacing with programmable divider enabling step size equal comparison frequency. applications 2.7GHz divide enabled, giving step size twice comparison frequency.
SP5669
Preliminary Information
CHARGE PUMP CRYSTAL REF/COMP ADDRESS PORT PORT
DRIVE INPUT INPUT PORT PORT
MP16
Figure connections view
REF/COMP Fcomp COUNT PHASE COMP Fref CRYSTAL
INPUTS
PROGRAMMABLE DIVIDER 16/17
REFERENCE DIVIDER (see Fig.
LOCK DETECT COUNT CHARGE PUMP
CHARGE PUMP DRIVE
LATCH LATCH DIVIDE RATIO
LATCH
LATCH
LATCH MODE CONTROL LOGIC (see Fig. ADDRESS POWER DETECT PORT PORT TRANSCEIVER
MODE CONTROL
DISABLE
LATCH PORT INTERFACE
TEST CONTROL
PORT PORT
Figure Block diagram
Preliminary Information
Electrical Characteristics
SP5669
-20°C +80°C, +4.5V +5.5V. Reference frequency 4MHz. These characteristics guaranteed either production test design. They apply within specified ambient temperature supply voltage ranges unless otherwise stated. Characteristics Supply current, input voltage 14100 13,14 input impedance input capacitance SDA, Input High voltage Input voltage Input High current Input Current LeakageCurrent Input hysteresis Output voltage Charge pump output current Charge pump output leakage Charge pump drive output current Drive output saturation voltage when disabled External reference input frequency External reference input ampltude Crystal frequency Crystal oscillator drive level Recommended crystal series resistance Value Units Conditions prescaler enabled, prescaler disabled, 300MHz 2.7GHz Prescaled enabled, Fig. 80MHz Prescaler enabled, PE=1, Fig. 80MHz 2.0GHz Prescaler disabled, Fig. Refer Fig. Refer Fig.
Input voltage Input voltage sink Fig. pin1
pin16 0.7V
MHzAC coupled sinewave p-pAC coupled sinewave
Applies 4MHz crystal only. `Parallel resonant' crystal. Figure quoted under conditions including start Includes temperature process tolerances. coupled output. Output enabled,RE=1. Note
Crystal oscillator negative resistance REF/COMP output Voltage
SP5669
Preliminary Information
Electrical Chacteristics (cont.)
-20°C 4.5V 5.5V. Reference frequency 4MHz. These characteristics guaranteed either production test design. They apply within specified ambient temperature supply voltage ranges unless otherwise stated. Characteristics Comparison frequency Equivalent phase noise phase detector Value Units -148 dBC/Hz 6kHz loop phase comparator freq 250kHz. Figure measured 1kHz offset, (within loop band width). Prescaler disabled, Prescaler enabled, Fig. Conditions
division ratio Reference division ratio Output ports Sink current Leakage current input voltage input current Address input current High Address input current
7,8,9,
131071 262142
-0.5
port 0.7V port 13.2V Table input Input voltage Input voltage =VEE
Note REF/COMP output used, output should left open circuit connected disabled setting RE=0.
Absolute Maximum Ratings
voltages referred Characteristics Supply Voltage, input voltage input offset Port voltage Total port current input offset REF/COMP output offset Charge pump offset Drive offset Crystal oscillator offset Address offset offset Storage temperature Junction temperature MP16 thermal resistance chip ambient chip case Power consumption =5.5V protection 13,14 13,14 7-10 7-10 7-10 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 Value +0.3 +0.3 +0.3 +0.3 +0.3 +0.3 +0.3 +150 +150 Units °C/W °C/W Conditions
coupled application Port state Port state
ports off, prescaler enabled 3015
Preliminary Information
Functional Description
SP5669 contains elements necessary, with exception frequency reference, loop filter external high voltage transistor, control varicap tuned local oscillator, forming complete frequency synthesised source. device allows operation with high comparison frequency fabricated high speed logic, which enables generation loop with good phase noise performance. block diagram shown Fig. input signal internal preamplifier, which provides gain reverse isolation from divider signals. output preamplifier interfaces with 17-bit fully programmable divider divide- by-two prescaler. applications 2GHz input, prescaler disabled eliminating degradation phase noise prescaler action. divider MN+A architecture, where dual modulus prescaler 16/17, counter 4-bits, counter 13-bits. output programmable divider phase comparator where compared both phase frequency domain with comparison frequency. This frequency derived either from on-board crystal controlled oscillator from external reference source. both cases reference frequency divided down comparison frequency reference divider which programmable into ratios detailed Fig. output phase detector feeds charge pump loop amplifier section, which when used with external voltage transistor loop filter, integrates current pulses into varactor line voltage. invoking device test modes described Fig. varactor drive output disabled switching external transistor 'off' allowing external voltage written varactor line tuner alignment purposes. Similarly, charge pump also disabled high impedance state. programmable divider output Fpd/2 switched port programming device into test mode. test modes described Fig. high
SP5669
Programming
SP5669 controlled data bus. Data Clock lines respectively defined format. synthesiser either accept data (write mode) send data (read mode). address byte (R/W) sets device into write mode low, read mode high. Tables Fig. illustrate format data. device programmed respond several addresses, which enables more than synthesiser system. Table Fig.4 shows address selected applying voltage 'address' input. When device receives valid address byte, pulls line during acknowledge period, during following acknowledge periods after further data bytes received. When device programmed into read mode, controller accepting data must pull line during status byte acknowledge periods read another status byte. controller fails pull line during this period, device generates internal STOP condition, which inhibits further reading.
Write Mode
With reference Table bytes contain frequency information bits inclusive. Auxillary frequency bits byte most frequencies only bytes will required. remainder byte byte control prescaler enable, reference divider ratio (see Fig. charge pump, REF/COMP output (see Fig. output ports test modes (see Fig. After reception acknowledgement correct address (byte first following byte determines whether byte interpreted byte logic indicating byte logic indicating byte Having interpreted this byte either byte following data byte will interpreted byte respectively. Having received complete data bytes, additional data bytes entered, where byte interpretation follows same procedure, without readdressing device. This procedure continues until STOP condition received. STOP condition generated after data byte, however occurs during byte transmission, previous data retained.
SP5669
Preliminary Information
Additional Programmable Prescaler enable divide prescaler enabled setting within byte logic '1'. logic disables prescaler, directly passing input frequency 17-bit programmable counter. static select only. Charge pump current charge pump current programmed bits within data byte defined Fig. Test mode test modes invoked setting bits RE=0 RTS=1 within programming data, selected bits TS2, shown Fig. When TS2, received, device retains previously received data. Reference/Comparison frequency output reference frequency switched REF/COMP output, setting RE=1 RTS=0 within byte comparison frequency comp switched REF/COMP output, setting RE=1 RTS=1 within byte logic '0', output disabled high state. default logic during device power thus enabling comparison frequency comp REF/COMP output.
Comparison frequency with 4MHz external reference 2MHz 1MHz 500kHz 250kHz 125kHz 62.5kHz 31.25kHz 15.625kHz 666.67kHz 333.33kHz 166.67kHz 83.33kHz 41.67kHz 20.83kHz 10.42kHz
facilitate smooth fine tuning, frequency data bytes only accepted device after bits frequency data have been received, after generation STOP condition. Repeatedly sending bytes only will change frequency. frequency change occurs when following data sequences sent addressed device;
Bytes Bytes when STOP condition follows valid data bytes follows; Bytes STOP Bytes STOP Bytes STOP Bytes STOP Bytes STOP should noted that device must initially addressed with both frequency control byte data, since control byte contains reference divider information which must provided before chosen frequency synthesised. This implies that after initial turn bytes must sent followed STOP condition minimum requirement. Alternatively bytes must sent port information also required.
Read Mode
When device read mode, status byte read fromthe device takes form shown Table Fig. (POR) power-on reset indicator, this logic supply device dropped below 25°C), e.g. when device initially turned reset when read sequence terminated STOP command. When high programmed information lost output ports high impedance. (FL) indicates whether device phase locked, logic present device locked, logic device unlocked. Bits (A2, combine give output ADC. used feed information microprocessor bus.
Ratio Allowed
Figure Reference division ratios
Preliminary Information
SP5669
ADDRESS PROGRAMMABLE DIVIDER PROGRAMMABLE DIVIDER CONTROL DATA CONTROL DATA
Byte Byte Byte Byte Byte
P2/TS2 P1/TS1 P0/TS0
Table Write data format (MSB transmitted first)
ADDRESS STATUS BYTE
Byte Byte
Table Read data format (MSB transmitted first)
MA1, R3,R2,R1,R0 TS2, TS1,
Acknowledge Variable address bits (see Table Programmable division ratio control bits Prescaler enable Reference division ratio select (see Fig. Charge pump current select (see Fig.6) Reference oscillator output enable REF/COMP output select when RE=1 (see Fig.5) Test mode enable when RE=0 (see Fig.5) Test mode control bits (valid when RE=0, RTS=1, Fig. port output state (always valid except when RE=0, RTS=1) port output states Power Reset indicator Phase Lock Flag data (see Table Don't care Voltage input 0.6V 0.45V 0.6VCC 0.3V 0.45VCC 0.15V 0.3VCC 0.15VCC
Address input voltage level 0.1VCC Open circuit 0.4V 0.6VCC 0.9V Programmed connecting resistor between Table Address selection
Table levels
Figure Data formats
SP5669
X=don't care
Preliminary Information
REF/COMP OUTPUT MODE Disabled high state Disabled high state Disabled high state Disabled high state Disabled high state Disabled high state switched comp switched Test mode description Normal operation Charge pump sink. Status byte logic Charge pump source. Status byte logic Charge pump disabled. Status byte FL=logic Port Varactor Drive Output disabled Normal operation Normal operation
Figure REF/COMP output mode Test modes
byte
byte ±195 ±416 ±900
Current ±120 ±260 ±555 ±1200 ±150 ±325 ±694 ±1500
Figure Charge pump current
INTO
INTO
OPERATING WINDOW
OPERATING WINDOW
1000
2000
3000 3500
1000
2000
3000 3500 2700
FREQUENCY (MHz)
FREQUENCY (MHz)
Figure Typical input sensitivity (prescaler disabled, PE=0)
Figure Typical input sensitivity (prescaler enabled, PE=1)
Preliminary Information
Double Conversion Tuner Systems
high 2.7GHz maximum operating frequency excellent noise characteristics SP5669 enables construction double conversion high tuners. typical system shown Fig.8 will SP5669 first control full band upconversion greater than 1GHz.
SP5669
wide range reference division ratios allows SP5669 used both converter with high phase comparator frequency (hence phase noise) down converter which utilises device lower comparison frequency mode (which offers fine step size).
50-900MHz
1.6GHz
38.9MHz
1650-2700MHz Reference Clock First SP5659 SP5669 Second SP5659 SP5669
Figure Example double conversion from VHF/UHF frequencies
+30V 4MHz 18pF 68pF 15nF 13k3 BCW31
Optional application utilising on-board crystal controlled oscillator
+12V
ADDRESS
OSCILLATOR OUTPUT
TUNER
CONTROL MICRO
SP5669 SP5659
Figure Typical appliction
Application Notes
generic application notes AN168 designing with synthesisers such SP5659 been written. This covers aspects such loop filter design decoupling. This application note also featured Media Data Book, refer Zarlink Semicondor Internet Site http://www.zarlink.com. generic test/demo board been produced which used SP5669. circuit diagram list components board shown Figs. board used following purposes: Measuring sensitivity performance. Indicating port function. Synthesising voltage controlled oscillator. Testing external reference
SP5669
Preliminary Information
+30V EXTERNAL REFERENCE SKT2 10nF* *(NOT FITTED) 68pF 13K3
+12V C7/C8/C9 100nF 2n2F INPUT SKT1
15nF
2N3904
4MHz DISABLE ENABLE DATA CLOCK 100pF 100pF 18pF
LOCK NOTE circuit diagram shown designed with number synthesisers. connected redundant when SP5669 used this board. SP5659
Figure Test board
Figure Test board (layout)
Preliminary Information
Loop Bandwidth
majority applications which SP5669 intended require loop filter bandwidth between 2kHz and10kHz. Typically phase noise will specified both 1kHz and10kHz offset. common practice arrange loop filter bandwidth such that 1kHz figure lies within loop bandwidth. Thus phase noise depends synthesiser comparator noise floor, rather than VCO. 10kHz offset figure should depend providing loop designed correctly, underdamped.
SP5669
There ways achieving higher phase comparator sampling frequency:- Reduce division ratio between reference source phase comparator higher reference source frequency. Approach preferred best performance since possible that noise floor reference oscillator degrade phase comparator performance reference division ratio very small.
Reference Source
SP5669 offers optimal phase noise performance when operated with large step size. This fact that phase noise within loop bandwidth
phase comparator frequency noise floor phase comparator frequency
Driving Devicesfrom Common Reference
mentioned earlier Datasheet, SP5669 REF/COMP output which allows synthesisers driven from common reference. this, ``Master" should programmed setting driven device should programmed normal operation i.e. devices should connected shown below.
Assuming phase comparator noise floor flat irrespective sampling frequency, this means that best performance will achieved when overall phase comparator division ratio minimum.
SP5669
Preliminary Information
4MHz 18pF
SP5669SP5659
SP5659 SP5669
Figure Driving devices from common reference
+j0.5
+j0.2
-j0.2
S11:Z0 NORMALISED
-j0.5
FREQUENCY MARKERS 100MHz, 500MHz, 1GHz 2.7GHz
Figure typical input impedance
Preliminary Information
SP5669
VREF
CHARGE PUMP
INPUTS
(Output disable)
DRIVE OUTPUT
inputs
Loop amplifier
PORT SCL/SDA/ADC
ONLY
Output Ports
ADDRESS CRYSTAL
REF/COMP enable/ disable
Reference oscillator
Address input
REF/COMP output
Figure Input/Output interface circuits
http://www.zarlink.com
World Headquarters Canada Tel: (613) 0200 Fax: (613) 1010
North America West Coast Tel: (858) 675-3400 Fax: (858) 675-3450
North America East Coast Tel: (978) 322-4800 Fax: (978) 322-4888
Asia/Pacific Tel: 6193 Fax: 6192
Europe, Middle East, Africa (EMEA) Tel: 1793 518528 Fax: 1793 518581
Information relating products services furnished herein Zarlink Semiconductor Inc. trading Zarlink Semiconductor subsidiaries (collectively "Zarlink") believed reliable. However, Zarlink assumes liability errors that appear this publication, liability otherwise arising from application such information, product service infringement patents other intellectual property rights owned third parties which result from such application use. Neither supply such information purchase product service conveys license, either express implied, under patents other intellectual property rights owned Zarlink licensed from third parties Zarlink, whatsoever. Purchasers products also hereby notified that product certain ways combination with Zarlink, non-Zarlink furnished goods services infringe patents other intellectual property rights owned Zarlink. This publication issued provide information only (unless agreed Zarlink writing) used, applied reproduced purpose form part order contract regarded representation relating products services concerned. products, their specifications, services other information appearing this publication subject change Zarlink without notice. warranty guarantee express implied made regarding capability, performance suitability product service. Information concerning possible methods provided guide only does constitute guarantee that such methods will satisfactory specific piece equipment. user's responsibility fully determine performance suitability equipment using such information ensure that publication data used date been superseded. Manufacturing does necessarily include testing functions parameters. These products suitable medical products whose failure perform result significant injury death user. products materials sold services provided subject Zarlink Semiconductor's conditions sale which available request.
Purchase Zarlink's components conveys licence under Philips Patent rights these components System, provided that system conforms Standard Specification defined Philips
Zarlink Zarlink Semiconductor logo trademarks Zarlink Semiconductor Inc. Copyright 2001, Zarlink Semiconductor Inc. rights reserved.
TECHNICAL DOCUMENTATION RESALE
Other recent searches
TA49308 - TA49308 TA49308 Datasheet
TA49058 - TA49058 TA49058 Datasheet
TA49306 - TA49306 TA49306 Datasheet
SP3238 - SP3238 SP3238 Datasheet
SH7046 - SH7046 SH7046 Datasheet
FX029 - FX029 FX029 Datasheet
FN18RL - FN18RL FN18RL Datasheet
AOD4112 - AOD4112 AOD4112 Datasheet
Privacy Policy | Disclaimer
© 2012 Datasheet Archive
