300-012, CCITT I.430 ANSI T1.605 interface Full-duplex 2B+D, kbit/s tr
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CMOS ST-BUS FAMILY MT8930C Subscriber Network Interface Circuit
300-012, CCITT I.430 ANSI T1.605 interface Full-duplex 2B+D, kbit/s transmission Link activation/deactivation D-channel access contention resolution Point-to-point, point-to-multipoint star configurations Master (NT)/Slave (TE) modes operation Exceeds loop length requirements Complete loopback testing capabilities chip HDLC D-channel protocoller Motorola/Intel microprocessor interface Controllerless microprocessor-controlled operation Zarlink ST-BUS interface power CMOS technology Single volt power supply
ISSUE3
November 1997
Ordering Information MT8930CE Plastic MT8930CP PLCC -40°C +85°C
Description
MT8930C Subscriber Network Interface Circuit (SNIC) implements ETSI 300-012, CCITT I.430 ANSI T1.605 Recommendations ISDN reference points. Providing point-topoint point-to-multipoint digital transmission, SNIC used either subscriber line TE). HDLC D-channel protocoller included controlled through Motorola/Intel microprocessor port. controllerless mode allows SNIC operate without microprocessor. MT8930C fabricated Zarlink's CMOS process.
Applications
ISDN ISDN interface ISDN Terminal Adaptor (TA) Digital sets (TE1) wire ISDN interface Digital PABXs, Digital Line Cards (NT2)
DSTi DSTo
ST-BUS Interface
D-channel Priority Mechanism
S-Bus Link Interface VBias
F0od STAR/Rsto CK/NT Cmode Microprocessor Interface Timing Control HDLC Transceiver Link Activation Controller
Rsti
HALF
AD0-7
R/W/WR, AFT/PRI
DS/RD, DinB
AS/ALE, P/SC
DReq
IRQ/NDA, DCack
Figure Functional Block Diagram
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MT8930C
HALF VBias F0od DSTi DSTo Cmode CK/NT R/W/WR, AFT/PRI DS/RD, DinB AS/ALE, P/SC DReq IRQ/NDA, DCack AD0, AD1, AD2, SYNC/BA PLCC STAR/Rsto Rsti AD7, AD6, AD5, AD4, AD3,
HALF F0od DSTi DSTo Cmode CK/NT R/W/WR, AFT/PRI DS/RD, DinB AS/ALE, P/SC DReq IRQ/NDA, DCack
VBias STAR/Rsto Rsti AD7, AD6, AD5, AD4, AD3, AD2, SYNC/BA AD1, AD0,
PDIP
Figure Connections
Description
PLCC
Name HALF
Description HALF Input/Output: this input mode output mode identifying which half S-interface frame currently being written/read over ST-BUS (HALF sampled falling edge within frame pulse window, identifies information transmitted/received first half S-Bus frame while HALF identifies information transmitted/received into second half S-Bus frame). Tying this mode will allow device free run. This signal also accessed from ST-BUS C-channel. 4.096 Clock: 4.096 ST-BUS Data Clock input mode. mode, 4.096 output clock phase-locked line data signal. Frame Pulse: active frame pulse input indicating beginning active STBUS channel times mode. Frame pulse output mode. Delayed Frame Pulse Output: active delayed frame pulse output indicating active ST-BUS channels this device. used daisy chain other ST-BUS devices share ST-BUS stream. Data ST-BUS Input: 2048 kbit/s serial PCM/data ST-BUS input with channels assigned first four timeslots. These channels contain data transmitted line chip control information. Data ST-BUS Output: 2048 kbit/s serial PCM/data ST-BUS output with channels assigned first four timeslots respectively. remaining timeslots placed into high impedance. These channels contain data received from line chip status information. Controller Mode Select Input: when high, microprocessor control selected. When controllerless mode enabled microport pins redefined control inputs status outputs. Clock/Network Termination Mode Select Input. mode, this must tied 4.096 clock clock required standard ISDN applications). mode, this must tied VDD. Refer "ST-BUS Interface" section further explanation. pull-up resistor needed when driven device.
F0od
DSTi
DSTo
Cmode
CK/NT
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MT8930C
Description (continued)
PLCC
Name
Description
R/W/WR Read/Write Write Input (Cmode defines data transfer read W=1) write (R/W=0) Motorola mode. Redefined Intel mode. AFT/PRI Adaptive-Fixed Timing/Priority Select Input (Cmode=0): mode, causes filters peak detectors disabled favour fixed timing fixed thresholds short passive operation (0=fixed, 1=adaptive). mode, this Priority input. High priority (PRI=1) normally reserved signalling. DS/RD Data Strobe/Read Input (Cmode active high input indicates SNIC that valid data during write operation that SNIC must output data during read operation Motorola mode. Redefined Intel mode. D-Channel Timeslot Input (Cmode active high input that causes eight ST-BUS D-channel bits, instead usual bits, routed from S-interface timeslot. When active, marks transmitted S-interface D-channel. Address Strobe/Address Latch Enable Input (Cmode Motorola mode falling edge used strobe address into SNIC during microprocessor access. Redefined Intel mode. Parallel/Serial Control Input (Cmode determines serial C-channel (P/SC=0) microport pins (P/SC=1) source chip control when controllerless mode selected. ST-BUS chosen source, dedicated Control input pins ignored status output pins remain valid. Chip Select Input (Cmode=1): active input used select SNIC microprocessor access. D-Channel Request Input (Cmode active high input that mode only causes SNIC transmit "01111110" flag immediately D-channel free, wait until becomes available then transmit flag. DCack signals successful acquisition D-channel. DReq tied low, continuous ones transmitted S-Bus D-channel. Internal Connection (Cmode normal operation mode only. Interrupt Request (Open Drain Output) (Cmode output indicating unmasked HDLC interrupt. interrupt remains active until microprocessor clears reading HDLC Interrupt Status Register. This interrupt source enabled with B2=0 Master Control Register. Data Available (Open Drain Output) (Cmode active output signal indicating availability data from S-Bus. This signal selected with B2=1 Master Control Register. D-Channel Acknowledge (Open Drain Output) (Cmode mode only indicates that SNIC gained access D-channel response DReq transmitted first zero opening flag. user should immediately begin transmitting rest packet over ST-BUS D-channel. this signal goes high middle transmission, lost must regain access Dchannel before retransmitting packet. Internal Connection (Open Drain Output) (C-mode=0). This used mode should left disconnected. This must tied with resistor. Ground. Bidirectional Address/Data (Cmode electrically logically compatible either Intel Motorola micro-bus specifications. DS/RD rising edge AS/ALE then chip operates Motorola specs. DS/RD high rising edge AS/ALE Intel mode selected. Taking Rsti sets Motorola mode. Internal State Outputs (Cmode =0): Binary encoded state number outputs.
Mode deactivated pending deactivation pending activation activated Mode deactivated synchronized activation request activated
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DinB
AS/ALE
P/SC
DReq
DCack
AD0-7
24-26 30-32 34-35 1516 2425
IS0-IS1
MT8930C
Description (continued)
PLCC
Name
Description
SYNC/BA Synchronization/Bus Activity Output (Cmode output indicating synchronization incoming frames when activation request asserted deactivation request Synchronization declared once three successive frames conforming 14-bit bipolar violation criteria have been detected. part deactivated activation request this indicates presence activity. Multiframe Input/Output (Cmode=0): multiframe input mode output mode. Setting this mode when HALF forces pair respectively. This going high mode indicates that been received. This signal updated rising edge HALF signal. Maintenance Channel (Q-channel) Input/Output (Cmode=0): output mode which valid only frame following transmission MFR. mode, this maintenance channel (Q-channel) input which transmitted bits following reception multiframe signal. This input sampled falling edge HALF signal. Input/Output (Cmode=0): input mode output mode. read written when HALF=1 while read written when HALF=0. Activate Request Input (Cmode asserting with will initiate appropriate S-interface activation sequence coded activation/ deactivation controller. Deactivate Request Input (Cmode asserting high will initiate appropriate S-interface deactivation sequence coded activation/ deactivation controller. Reset Input: Schmitt trigger reset input. '0', sets control registers default conditions, resets activation state machines deactivated state, resets HDLC, clears HDLC FIFO`s. Sets microport Motorola mode.
Rsti
STAR/Rsto Star/Reset (Open Drain Output): 192kbit/s data output fixed relative ST-BUS timebase. group NTs, fixed timing mode, wire or'ed together create Star configuration. Active reset output mode indicating consecutive marks have been received. connected directly Rsti allow reset bus. This must tied with resistor. Receive Line Signal Input: this high impedance input pseudoternary line signal connected line through ratio transformer. Figures bias level this input equal VBias must maintained. Transmit Line Signal Output: this current source output designed drive nominal line through ratio transformer. Figures Bias Voltage: analog ground transformers. This must decoupled through 10µF capacitor with good high frequency characteristics (i.e., tantalum). Power Supply Input. Connection.
VBias
1,5-6,1012,15,18, 23,27-29,
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MT8930C
Functional Description
MT8930C Subscriber Network Interface Circuit (SNIC) multifunction transceiver providing complete interface Reference Point specified 300-012, CCITT Recommendation I.430 ANSI T1.605. Implementing both point-to-point point-to-multipoint voice/data transmission, SNIC used either digital subscriber loop. programmable digital interface allows MT8930C configured Network Termination (NT) Terminal Equipment (TE) device. SNIC supports kbit/s (2B+D overhead) full duplex data transmission 4-wire balanced transmission line. Transmission capability both channels, well related timing synchronization functions, provided chip. signalling capability procedures necessary enable customer terminals (TEs) activated deactivated, form part MT8930C's functionality. SNIC handles D-channel resource allocation prioritization access contention resolution signalling requirements passive line configurations. Control status information allows implementation maintenance functions monitoring device subscriber loop. HDLC transceiver included SNIC link access protocol handling D-channel. Depacketized data passed from transceiver microprocessor port. byte deep FIFOs, transmit receive, provided buffer data. HDLC block transmit receive to/from either S-interface port ST-BUS port. Further, transmit destination receive source independently selected, e.g., transmit S-interface while receiving from ST-BUS. transmit receive paths separately enabled disabled. Both, byte address recognition supported SNIC. transparent mode allows data passed directly channel without being packetized. block diagram MT8930C shown Figure SNIC three interface ports: 4-wire CCITT compatible interface (subscriber loop interface), 2048 kbit/s ST-BUS serial port, general purpose parallel microprocessor port. This 8-bit parallel port compatible with both Motorola
CONTROLLER MODE MODE HALF C4bi F0bi F0od DSTi DSTo Cmode R/W/WR DS/RD AS/ALE IRQ, VBias STAR Rsti HALF C4bo F0bo F0od DSTi DSTo Cmode R/W/WR DS/RD AS/ALE IRQ, MODE VBias Rsto Rsti
CONTROLLERLESS MODE MODE HALF C4bi F0bi F0od DSTi DSTo Cmode DinB P/SC VBias STAR Rsti M/Si MCHo MFRi SYNC/BA HALF C4bo F0bo F0od DSTi DSTo Cmode DinB P/SC DReq DCack MODE VBias Rsto Rsti M/So MCHi MFRo SYNC/BA
Figure SNIC Connections Various Modes
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MT8930C
Intel microprocessor signals timing. SNIC also provisions controllerless mode (Cmode=0), where microprocessor port redefined allow access control/status registers external hardware.
Channel (B2)
Channel (B1)
Don't care
three major blocks MT8930C, consisting system serial interface (ST-BUS), HDLC transceiver, digital subscriber loop interface (S-interface) interconnected high speed data busses. Data sent received from S-interface port (B1, channels) accessed from either parallel microprocessor port serial ST-BUS port. This also true SNIC control status information (C-channel). Depacketized D-channel information from HDLC section only accessed through parallel microprocessor port.
S-Bus Interface
S-Bus four wire, full duplex, time division multiplexed transmission facility which exchanges information kbit/s rate including kbit/s voice data channels, kbit/s signalling channel kbit/s synchronization overhead. relative position these channels with respect ST-BUS shown Figures SNIC makes first four channels ST-BUS transmit receive control/status data from S-interface port. These C-channels (see Figure channels each have bandwidth kbit/s used carry voice data across network. D-channel primarily intended carry signalling information circuit switching through ISDN network. SNIC provides capability having kbit/s full kbit/s D-channel allocating B1-channel timeslot D-channel. Access depacketized D-channel only granted through parallel microprocessor port. C-channel provides means system control monitor functionality SNIC. This control/status channel accessed system through ST-BUS microprocessor port. C-channel provides access registers which provide complete control over state activation machine, D-channel priority mechanism well various maintenance functions. detailed description these registers discussed microprocessor port interface.
Channel
DSTo
Figure ST-BUS Channel Assignment
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F0od
DSTi
Only valid with kbit/s D-channel
Channel
Output high impedance state
DSTi
62.5 62.5
HALF Input
DSTo
HALF Output
DSTi
62.5
HALF Output 62.5
DSTo
HALF Input Activation Multiframing S-channel Note: Shaded areas reveal data mapping Auxiliary framing bits Auxiliary framing Q-channel within B1-channel within B2-channel
Framing balancing within D-channel D-echo channel
MT8930C
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Figure S-Bus Frame Structure Functional Timing
MT8930C
Line Code line code used S-interface Pseudo ternary code with 100% pulse width seen Figure below. Binary zeros represented marks line successive marks will alternate polarity.
BINARY VALUE
criterion criterion direction specified Recommendations I.430 T1.605 satisfied. B1-channel binary ones, first zero following L-bit will violate line code sequence, thus allowing subsequent marks alternate without bipolar violations. bits also used identify multiframe structure (when this done, criterion met). This multiframe structure will make provisions speed signalling channel used direction (Q-channel). will consist five frame multiframe which identified binary inversion N-bit first frame consequently every fifth frame multiframe. Upon detection multiframe signal, will replace next Fabit transmitted with Q-bit. balancing bits used remove content from line. balancing will mark number preceding marks previous balancing odd. number marks even, L-bit will space. A-bit used during line activation procedures (refer state activation diagrams). state A-bit will advise achieved synchronization. E-bit D-echo channel. will reflect binary value received D-channel into E-bits. This used establish access contention resolution point-to-multipoint configuration. This described more detail section D-channel priority mechanism. M-bit second level multiframing which used structuring Q-bits. frame with Mbit=1 identifies frame twenty frame multiframe. Q-channel then received shown Table synchronization with multiframes must performed externally. FRAME
LINE SIGNAL Violation
Figure Alternate Zero Inversion Line Code mark which does adhere alternating polarity known bipolar violation. Framing valid frame structure transmitted contains following (refer Fig. Framing channels (B1,B2) balancing bits D-channel bits (D0, Auxiliary framing (Fa, N=Fa Activation D-echo channel bits Multiframing S-channel Framing channels (B1, balancing bits D-channel bits (D0, Auxiliary framing (Fa) Q-channel framing mechanism S-interface makes line code violations identify frame boundaries. F-bit violates alternating line code sequence allow quick identification frame boundaries. secure frame alignment, next mark following frame balancing will also produce line code violation. data following balancing binary ones, zero auxiliary framing (Fa) N-bit (for direction will provide successive violations ensure that
Q-Bit
M-Bit
Table Q-channel Allocation Order When using B-channels voice, first transmitted S-Bus should sign bit. This complies with existing telecom standards which transmit voice most significant first. However, B-channels
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MT8930C
carry data, ordering must reversed comply with existing datacom standards (i.e., least significant first). These contradicting standards place restriction information input output through serial parallel ports. Information transferred through serial ports, will maintain integrity order. Data sent either serial port from parallel port, will transmit least significant first. Therefore, byte input through microprocessor port must reordered have sign least significant bit. When microprocessor reads channel data either ST-BUS S-bus serial port, least significant read first received that particular channel either serial port. D-channel received serial ST-BUS ports must ordered with least significant first shown Figure This also applies D-channel directed ST-BUS from microprocessor port. C-channel mapping from parallel port ST-BUS organized such that most significant transmitted received first. State Activation state activation controller activates deactivates SNIC response line activity external command. controller completely hardware driven need initialized microprocessor. state diagram initialization shown Figure protocol used state activation controller defined follows: deactivated state, neither assert signal line (Info0). wants initiate activation, must begin transmitting continuous signal consisting positive zero, negative zero followed ones (Info1). Once detected Info1, begins transmit Info2 which consists S-Bus frame with zeros D-channel activation (A-bit) zero. soon synchronizes Info2, responds with valid S-Bus frame with data D-channel (Info3). will then transmit valid frame with data D-channel. will also activation binary once synchronization Info3 achieved. wishes initiate activation, steps ignored starts sending Info2. initiate deactivation, either begins send Info0 (Idle line). D-channel Priority Mechanism SNIC contains hardware priority mechanism D-channel contention resolution. connected point-to-multipoint configuration allocated D-channel using systematic approach. Allocation D-channel accomplished monitoring D-echo channel (E-bit) incrementing D-channel priority counter with every consecutive echoed back bit. zero found D-echo channel will reset priority counter. There classes priority within SNIC, user accessible other being strictly internal. user accessible priority selects class operation precedence over internal priority. latter (internal priority), will select level priority within each class (i.e., internal priority subsection user accessible priority). User accessible priority selects terminal count 10/11 consecutive ones E-bit being high priority while being priority). internal priority selects terminal between high class class. first terminal equipment attain E-bit priority count will immediately take control D-channel sending opening flag. more than terminal same priority, them will eventually detect collision. that detect collision will immediately stop trans-mitting D-channel, generate interrupt through Dcoll bit, reset DCack next frame pulse, restart counting process. remainder packet FIFO ignored. After successfully completing transmission, internal priority level reduced from high low. internal priority will only increased once terminal count respective level priority been achieved (e.g., high priority internally externally, must count consecutive ones D-echo channel. Once this achieved successful transmission been completed, internal priority reduced lower level (i.e., count This terminal will return high internal priority until consecutive ones have been monitored D-echo channel).
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MT8930C
Signals from Info0 Signal Info0 Info1 Signals from Signal Continuous Signal +`0', -`0' `1's(1) Where: BA(2) Activity Deactivation Request Activation Request Sync(2) Frame Sync Signal Activation Time Timer Signal Note signal timebase locked Info3 Info4 Valid frame with data D-echo channels. Valid frame with data Bits Note Sync/BA Status Register configured Sync when when change state and/or bits will cause change function Sync/BA following ST-BUS frame.
Info2
Valid frame structure with D-echo bits
State Activation Diagram Deactivated send Info0 Sync Activated send Info3 A=1& Sync Sync State Activation Diagram Pending Activation send Info2 Sync Sync Activated send Info4 Pending Deactivation Send Info0 Deactivated send Info0 Time Synchronized send Info3 Sync send Info0 Sync Activation Request send Info1 send Info0 Sync
Figure Link Activation Protocol, State Diagram Line Wiring Configuration SNIC fixed timing mode, filters/peak detectors disabled threshold voltage fixed. However, SNIC MT8930C interface three SNIC adaptive timing mode), wiring configurations which specified CCITT filters/peak detectors enabled. this Recommendation I.430 ANSI T1.605 (refer manner, device compensate variable Figs. 10). These consist point-to-point round trip delays line attenuation using point-to-multipoint configurations (i.e., threshold voltage fixed percentage short passive extended passive bus). pulse peak amplitude. selection line configurations performed using timing Mode Control Register). Another operation implemented using SNIC star configuration shown Figure short passive bus, devices connected This mode allows multiple NTs, with physically random points along cable. However, independent S-Busses, share common input extended passive connection points source transfer information down S-Bus grouped cable from
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MT8930C
operating adaptive timing line termination resistor
Figure Point-to-Point Configuration
impedance cable impedance cable
operating fixed timing line termination resistor
Fiure Short Passive Configuration, supported
0-500 0-50
operating adaptive timing line termination resistor
Figure Extended Passive Configuration, supported devices connected into star will receive information transmitted branches star, exactly they were same physical S-Bus. star configuration must operating fixed timing mode. Refer description star configuration ST-BUS section. SNIC last mode operation called slave mode. This effect operating SNIC network termination mode (CK/NT having frame structure registers description defined mode. This used where multiple subscriber loops must carry fixed phase relation between each line. typical situation when system trying synchronize nodes synchronous network. This allows multiple share common ST-BUS timebase. synchronization loops established using clock signals produced local input timing source slave. Adaptive Timing Operation power-up after reset, SNIC mode operate fixed timing. switch adaptive timing, user should: Timing C-channel Control Register wait period proceed using bits desired Switching from adaptive timing mode completed resetting Timing bit.
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MT8930C
Channel Channel Channel
Channel
Channel
Channel
(8/2048)
Figure ST-BUS Stream Format
ST-BUS CELLS
Channel
Channel
Channel
Channel
Channel
Figure Clock Frame Alignment ST-BUS Streams
ST-BUS Interface
ST-BUS synchronous time division multiplexed serial bussing scheme with data streams operating 2048 kbit/s configured kbit/s channels (refer Fig. 11). Synchronization data transfer provided from frame pulse which identifies frame boundaries repeats rate. Figure shows frame pulse (F0b) defines ST-BUS frame boundaries. data clocked into device rising edge 4096 clock (C4b) three quarters into cell, while data clocked falling edge 4096 clock start cell. timing signals (i.e. C4b) identified bidirectional (denoted terminating configuration these pins controlled mode operation TE). mode, synchronized signals supplied from external source SNIC uses this timing while transferring information from ST-BUS. mode, on-board analog phase-locked loop extracts timing from received data S-Bus generates system 4096 (C4b) frame pulse (F0b). analog phase-locked loop also maintains proper phase relation between timing signals well filtering jitter which present received line port.
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When mode selected tying CK/NT low, continuous INFO0 signal receiver will cause frequency drift from nominal 4.096 value (C4b output). Hence, transmitted INFO1 from will kbps required I.430 T1.605. However, user's application requires transmission INFO1 exactly kbit/s presence exact 4.096 clock times, then 4.096 clock should connected CK/NT pin. This input clock serves configure device mode train absence INFO2 INFO4 signal line. SNIC uses first four channels ST-BUS shown Figure simplify distribution serial stream, SNIC provides delayed frame pulse (F0od) eliminate need channel assignment circuit. This signal used drive subsequent devices daisy chain (refer Figure 13). this type arrangement, only first SNIC chain will receive system frame pulse (F0b) with following devices receiving predecessor's delayed output frame pulse (F0od). SNIC makes efficient through Star configuration. does sharing four common ST-BUS channels multiple devices.
MT8930C
ST-BUS Clock ST-BUS Stream Active Channel MT8930C System Frame Pulse F0od Active Channels MT8930C F0od Active Channels MT8930C F0od Active Channels MT8930C F0od
Figure Daisy Chaining SNIC
MT8930C System Frame Pulse STAR DSTi MT8930C STAR DSTi DSTo
Output ST-BUS Stream Input ST-BUS Stream MT8930C STAR DSTi MT8930C STAR DSTi
Figure Star Configuration eight SNICs mode with physically independent S-Busses connected parallel realize star configuration, shown Figure devices connected into star will carry same input, thus information sent simultaneously. 2B+D data received from every transmitted through STAR pin. Consequently, DSTo streams will carry identical 2B+D data reflecting what being transmitted various TEs. flow data direction S-Bus ST-BUS transparent SNIC, regardless state machine status. other hand, flow data direction ST-BUS S-Bus becomes transparent only after state machine active state (IS0, IS1=1,1), case synchronization state (IS0, IS1=1), case Intel multiplexed signals timing. MOTEL circuit (MOtorola InTEL Compatible bus) uses level DS/RD rising edge AS/ALE select appropriate timing. DS/RD rising edge AS/ALE (refer Fig. then Motorola timing selected. Conversely, DS/RD high rising edge AS/ALE (refer Figs. 25), then Intel timing selected. This effect redefining microprocessor port transparently user. this mode, user option writing C-channel Control Diagnostic Register through parallel port interface through C-channel DSTi. Master Control Register provides this option. parallel port SNIC allows complete control HDLC transceiver access data, control status registers. internal registers (defined Table accessed through microprocessor port only when Cmode held high. Reading these registers allows microprocessor monitor incoming data ST-BUS without interrupting normal data flow.
Microprocessor/Control Interface
parallel port SNIC operates either general purpose microprocessor interface hardwired control port. microprocessor control mode (Cmode parallel port compatible with either Motorola
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MT8930C
Address Lines Write Master Control Register ST-BUS Control Register HDLC Control Register HDLC Control Register HDLC Interrupt Mask Register HDLC FIFO HDLC Address Byte Register HDLC Address Byte Register C-channel Control Register Control Register Available DSTo C-channel S-Bus D-channel DSTo D-channel S-Bus B1-channel DSTo B1-channel S-Bus B2-channel DSTo B2-channel Table SNIC Address Read verify verify verify HDLC Status Register HDLC Interrupt Status Register HDLC FIFO verify verify C-channel Status Register available Master Status Register DSTi C-channel DSTi D-channel S-Bus D-channel DSTi B1-channel S-Bus B1-channel DSTi B2-channel S-Bus B2-channel
Some registers classified asynchronous others synchronous. Synchronous registers single-buffered require synchronous access. synchronous registers have same access times, accessed synchronously time during which signal (refer Fig. Therefore, recommended that user make signal access these registers. Since synchronous registers common circuitry, essential that register read before being written. This sequence important write cycle will overwrite last data received. These parallel accesses must refreshed every frame. Asynchronous registers, other hand, accessed time. When Cmode low, controllerless mode selected parallel port reverts hardwired control/status pins. This allows MT8930C function without need controlling microprocessor. controllerless mode, parallel direct connection relevant control/status registers (refer Description). Discrete logic used drive/sense respective pins. this mode, (P/SC determines whether microport pins C-channel bits DSTi stream control source device. C-channel selected source, P/SC tied low, then microport pins ignored C-channel loaded into C-channel Control Register.
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data Mode Status Register, depending upon mode selected, always sent C-channel DSTo. However, microprocessor control mode user overwrite this data writing DSTo C-channel Register. This access done anytime outside frame pulse interval ST-BUS frame. Data written current ST-BUS frame will only appear Cchannel following frame. least significant (B0) C-channel Register, selects between control register diagnostic register. Setting C-channel Register allow access control register. Setting C-channel Register allow access diagnostic register. interpretation each register defined Tables mode Tables mode. important note that mode, C-channel Diagnostic Register should cleared while device active state (IS0, 1,1). This accomplished setting ClrDia Cchannel Control Register until device activated. serial control mode, C-channel ST-BUS loaded into C-channel Control Register every ST-BUS frame; user should make sure that written ClrDia every frame. However, parallel control mode user needs ClrDia only once keep
MT8930C
Diagnostic Register cleared. Once full activation achieved Diagnostic Register written order enable various test functions. HDLC Transceiver HDLC Transceiver handles oriented protocol structure formats D-channel level X.25 packet switching protocol defined CCITT. transmits receives packetized data (information control) serially format shown Figure while providing data transparency zero insertion deletion. generates detects flags, various link channel states abort sequence. Further, provides cyclic redundancy check data packets using CCITT defined polynomial. addition, recognize single byte, dual byte call address received frame. There also provision disable protocol functions provide transparent access either serial port through microprocessor port. Other features provided HDLC include, independent port selection transmit received data (e.g. transmit S-Bus receive from ST-BUS), selectable kbit/s D-channel well HDLC loopback from transmit receive port. These features enabled through HDLC control registers (see Tables HDLC Frame Format frames start with opening flag with closing flag shown Figure Between these flags, frame contains data frame check sequence (FCS). Data data field refers Address, Control Information fields defined CCITT recommendations. valid frame should have data field least bits. first second byte data field address frame. iii) Frame Check Sequence (FCS) bits following data field frame check sequence bits. generator polynomial G(x)=x16+x12+x5+1 transmitter calculates bits data field transmits complement with most significant first. receiver performs similar computation bits received data also includes field. generating polynomial will assure that integrity transmitted data maintained, remainder will have consistent pattern this used identify, with high probability, errors occurred during transmission. error status received packet indicated bits HDLC Status Register. Zero Insertion Deletion transmitter, while sending either data from FIFO bits FCS, checks transmission bit-by-bit basis inserts ZERO after every sequence five contiguous ONEs (including last five bits FCS) ensure that flag sequence imitated. Similarly receiver examines incoming frame content discards ZERO directly following five contiguous ONEs. Abort transmitter aborts frame sending zero followed seven consecutive ONEs. HDLC Control Register along with write HDLC Transmit FIFO enables transmission abort sequence instead byte written register have valid abort there must least bytes packet). receive side, frame abort defined seven more contiguous ONEs occurring after start flag before flag packet. interrupt generated reception abort sequence using HDLC Interrupt Mask/Vector Registers (refer Tables 10).
FLAG Byte
DATA FIELD Bytes
Bytes
FLAG Byte
Figure Frame Format Flag flag unique pattern bits (01111110) defining frame boundary. transmit section generates flags appends them automatically frame transmitted. receive section searches incoming packets flags bit-by-bit basis establishes frame synchronization. flags used only identify synchronize received frame transferred FIFO.
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MT8930C
Interframe Time Fill When HDLC Tranceiver sending packets, transmitter states mentioned below depending status IFTF HDLC Control Register Idle State Idle state defined more contiguous ONEs. When HDLC Protocoller observing this condition receiving channel, Idle HDLC Status Register HIGH. transmit side, Protocoller ends transmission ones (idle state) when data loaded into transmit FIFO. CCITT I.430 Specification requires every that does have layer frames transmit, send binary ONEs D-channel. this manner, other line will have opportunity access D-channel using priority mechanism circuitry. Flag Fill State HDLC Protocoller transmits continuous flags (7EHex) Interframe Time Fill state ends this state when data loaded into transmit FIFO. reception interframe time fill will have effect setting idle HDLC Status Register '0'. HDLC Transmitter power HDLC transmitter disabled idle state. transmitter enabled setting TxEN HDLC Control Register start packet, data written into byte Transmit FIFO starting with address field. data must written FIFO bytewide manner. When data detected transmit FIFO, HDLC protocoller will proceed following ways: transmitter idle state, present byte ones completely transmitted before sending opening flag. data transmit FIFO then transmitted. transmitting Dchannel will contention circuitry described previously D-channel Priority Mechanism access this channel. transmitter flag fill state, flag presently being transmitted used opening flag packet stored transmit FIFO.
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HDLC transmitter transparent data mode, protocol functions disabled data transmit FIFO transmitted without framing structure. indicate that particular byte last byte packet, HDLC Control Register must before last byte written into transmit FIFO. cleared automatically when data byte written FIFO. After transmission last byte packet, frame check sequence bits) sent followed closing flag. there more data transmit FIFO, immediately sent after closing flag. That closing flag packet also used opening flag next packet. However, CCITT I.430 ANSI T1.605 Recommendations state that after successful transmission packet, must lower priority level within specified priority class. user meet this requirement loading FIFO with more than packet then waiting DCack zero, HDLC interrupt TEOP HDLC Interrupt Status Register, before attempting load packet. there more data transmitted, transmitter assumes selected link channel state. During transmission either data frame check sequence, Protocol Controller checks transmitted information basis insert ZERO after every sequence five consecutive ONEs. This required eliminate possibility imitating opening closing flag, idle code abort sequence. Transmit Underrun transmit underrun occurs when last byte loaded into transmit FIFO `flagged' with `end packet' (EOP) there more bytes FIFO. such situation, Protocol Controller transmits abort sequence (zero seven ones) moves selected link channel state. Conversely, event that transmit FIFO full, further writes will overwrite last byte Transmit FIFO. Abort Transmission desired abort packet currently being loaded into transmit FIFO, next byte written FIFO should `flagged' cause this happen. HDLC Control Register must
MT8930C
HIGH, before writing next byte into FIFO. This cleared automatically once byte written Transmit FIFO. When `flagged' byte reaches bottom FIFO, frame abort sequence sent instead byte transmitter operation returns normal. frame abort sequence ignored packet less then bytes. iii) Transparent Data Transfer Trans (B4) HDLC Control Register provide transparent data transfer disabling protocol functions. transmitter longer generates Flag, Abort Idle sequences does insert zeros calculate FCS. should noted that none protocol related status interrupt bits applicable transparent data transfer state. However, FIFO related status interrupt bits pertinent carry same meaning they while performing protocol functions. HDLC Receiver After reset power receive section disabled. Address detection also disabled when reset occurs. address detection required, Receiver Address Registers loaded with desired address ADRec HDLC Control Register HIGH. receive section then enabled RxEN this same Control Register HDLC interrupts masked, thus desired interrupt signal must unmasked through HDLC Interrupt Mask Register. active interrupts cleared reading HDLC Interrupt Status Register. Normal Packets After initialization explained above, serial data starts clocked receiver checks idle channel flags. idle channel detected, `Idle' HDLC Status Register HIGH. Once flag detected, receiver synchronizes itself bytewide manner incoming data stream. receiver keeps resynchronizing flags until incoming packet appears. incoming packet examined bit-by-bit basis, inserted zeros deleted, calculated data bytes written into byte Receive FIFO. However, other control characters, i.e., flag abort never stored Receive FIFO. address detection enabled, address field following flag compared bytes Receive Address Registers. byte address recognition enabled, address field byte long compared with most significant bits address recognition register byte address recognition enabled, address field bytes long compared with address recognition registers address byte also recognized call address (i.e., seven most significant bits match found, entire packet ignored, nothing written Receive FIFO receiver waits next packet. active address byte valid, packet received normal fashion. bytes written receive FIFO flagged with status bits. status bits found HDLC status register indicate whether byte read from FIFO first byte packet, middle packet, last byte packet with good last byte packet with FCS. This status indication valid byte which read from Receive FIFO. incoming data always written FIFO bytewide manner. However, event data sent being multiple eight bits, software associated with receiver should able pick data bits from positions last byte received data written FIFO. Protocoller does provide indication many bits this might Invalid Packets mode, there less than data bits between opening closing flags, packet considered invalid data never enters receive FIFO (inserted zeros form part valid count). This true even with data abort sequence, total which less than bits. data packets that least bits less than bits long also invalid, ignored. They clocked into receive FIFO tagged having FCS. mode, however, data packets that less than bits long considered invalid. They clocked into receive FIFO with "Bad FCS" status. iii) Frame Abort When frame abort received, EOPD bits HDLC Interrupt Status Register set. last byte aborted packet written FIFO with status "Packet Byte". there more than packet FIFO, aborted packet
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MT8930C
distinguished fact that "Last Byte" status bytes. Idle Channel Receive Overflow While receiving idle channel, idle HDLC status register remains set. Transparent Data Transfer setting Trans HDLC Control Register select transparent data transfer, receive section will disable protocol functions like Flag/ Abort/Idle detection, zero deletion, calculation address comparison. received data shifted from active port written receive FIFO bytewide format. should noted that none protocol related status interrupt bits applicable transparent data transfer state. However, FIFO related status Receive overflow occurs when receive section attempts load byte already full receive FIFO. attempts write full FIFO will ignored until receive FIFO read. When overflow occurs, rest present packet ignored receiver will disabled until reception next opening flag. interrupt bits pertinent carry same meaning they while performing protocol functions.
B6-B3
NAME NA(1) IRQ/NDA
DESCRIPTION will allow access Control Register Master Status Register. will prevent Keep normal operation. state this will select mode IRQ/NDA pin. will enable HDLC interrupts. will enable Data Available signal which identifies access time synchronous registers. enabled, HDLC interrupts disabled.) will enable transmission M(2) selected Mode C-channel Register (refer Table 13). selection determined HALF signal (refer functional timing). will disable this feature forcing bits binary zero. Parallel/Serial Control selects source control channel. '0', then Cchannel Register access through ST-BUS stream. '1', then C-channel Register accessed through microprocessor port. Table Master Control Register (Read/Write Add. 00000B)
M/Sen
P/SC
Note Note
These bits have designated memory space will read last values written microprocessor port. transmission used second level multiframing.
NAME RxDIS Keep normal operation.
DESCRIPTION
When `1', this disables S-Bus signal receiver. used, example, force INFO4 INFO2 transition state machine while receiving INFO3 from Keep normal operation. Table Control Register (Write Add. 10000B)
B5-B0
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MT8930C
NAME CH3i(3) CH2i(3) CH1i(3) CH0i(3) CH3o(3) CH2o(3) CH1o(3) CH0o(3) DESCRIPTION '1', then ST-BUS channel input port enabled (B2-channel). '0', then channel disabled, will read FFH. '1', then ST-BUS channel input port enabled (B1-channel). '0', then channel disabled, will read FFH. '1', then ST-BUS channel input port enabled (C-channel). '0', then channel disabled, will read 00H. '1', then ST-BUS channel input port enabled (D-channel). '0', then channel disabled, will read FFH. '1', then ST-BUS channel output port enabled (B2-channel). '0', then channel disabled will placed High impedance. '1', then ST-BUS channel output port enabled (B1-channel). '0', then channel disabled will placed High impedance. '1', then ST-BUS channel output port enabled (C-channel). '0', then channel disabled will placed High impedance '1', then ST-BUS channel output port enabled (D-channel). '0', then channel disabled will placed High impedance. Table ST-BUS Control Register (Read/Write Add. 00001B)
Note ST-BUS channels enabled controllerless mode.
NAME TxEn RxEn ADRec
DESCRIPTION enables HDLC transmitter selected D-channel (i.e., ST-BUS S-Bus). disables HDLC transmitter (i.e., signal will sent). enables HDLC receiver selected D-channel (i.e., ST-BUS S-Bus). disables HDLC receiver (i.e., signal will received). '1', then address recognition enabled. This forces receiver recognize only those packets having unique address programmed Receive Address Registers address byte All-Call address (all 1s). '0', then address recognition disabled every valid packet stored received FIFO. This selects port HDLC transmitted D-channel. A'1' selects S-Bus port. selects ST-BUS port. This selects port HDLC received D-channel. selects S-Bus port. selects ST-BUS port. This selects Inter Frame Time Fill. selects continuous flags. selects idle state. Keep normal operation. will activate HDLC loopback where transmitted D-channel looped back received D-channel(1). mode, transmission packet affected. Mode, however, DReq C-channel Control Register must packet transmitted S-Bus. disables loopback. Table HDLC Control Register (Read/Write Add. 00010B)
TxPrtSel RxPrtSel IFTF HLoop
Note HDLC receiver must enabled well designated channel.
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B7-B5 NAME Trans Keep normal operation. will place HDLC transparent mode. This will perform serial parallel parallel serial conversion without inserting deleting opening closing flags, bytes zero insertion. source destination data determined port selection bits HDLC Control Register transition from will reset receive FIFO. This causes receiver disabled until reception next flag. (The status Register will identify RxFIFO being empty). device resets this immediately after clearing receive FIFO. transition from will reset transmit FIFO. This causes transmitter clear data TxFIFO. device resets this immediately after clearing transmit FIFO. will 'tag' next byte written transmit FIFO cause abort sequence transmitted once reaches bottom FIFO. will 'tag' next byte written transmit FIFO cause packet sequence transmitted once reaches bottom FIFO. Table HDLC Control Register (Write Add. 00011B)
Note These bits will reset after write TxFIFO
DESCRIPTION
RxRst
TxRst
FA(2) EOP(2)
B7-B6
NAME RxByte Status
DESCRIPTION These bits indicate status received byte which ready read from deep received FIFO. status encoded follows: Packet Byte First Byte Last Byte (Good FCS) Last Byte (Bad FCS) These bits indicate status deep receive FIFO. This status encoded follows: FIFO Empty Bytes FIFO Overflow Bytes These bits indicate status deep transmit FIFO follows: FIFO Full Bytes FIFO Empty Bytes '1', idle channel state been detected. unmasked asynchronous interrupt been detected. Table HDLC Status Register (Read Add. 00011B)
B5-B4
RxFIFO Status
B3-B2
TxFIFO Status
Idle
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NAME EnDcoll EnEOPD EnTEOP EnFA EnTxFL EnTxFun EnRxFF EnRxFov DESCRIPTION will enable D-channel collision interrupt. will disable This available only mode. will enable received Packet interrupt. will disable will enable transmit Packet interrupt. will disable will enable Frame Abort interrupt. will disable will enable Transmit FIFO interrupt. will disable will enable Transmit FIFO Underrun interrupt. will disable will enable Receive FIFO Full interrupt. will disable will enable Receive FIFO Overflow interrupt. will disable Table HDLC Interrupt Mask Register (Write Add. 00100B)
NAME Dcoll(1)
DESCRIPTION indicates that collision been detected D-channel (i.e., received E-bit does match with transmitted D-bit). This available only mode when HDLC transmitter enabled. always reads mode. '1'indicates that packet been detected HDLC receiver. This form flag, abort sequence invalid packet. indicates that transmitter finished sending closing flag last packet FIFO, internal priority level reduced from high low. indicates that receiver detected frame abort sequence received data stream. indicates that device only four Bytes remaining FIFO. This significance only when FIFO being depleted when getting loaded. indicates that FIFO empty without being given 'end packet' indication. HDLC will transmit abort sequence after encountering underrun condition. indicates that HDLC controller accumulated least bytes FIFO. indicates that FIFO overflown (i.e., attempt write full FIFO). HDLC will always disable receiver once receive overflow been detected. receiver will re-enabled upon detection next flag. Table HDLC Interrupt Status Register (Read Add. 00100B)
EOPD(1) TEOP(1) FA(1) TxFL(1) TxFun(1) RxFF(1) RxFov(1)
Note
interrupts will reset after read HDLC Interrupt Status Register.
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B7-B2 NAME DESCRIPTION
R1A7-R1A2 mask used interrogate first byte received address (where MSB). address recognition enabled, packet failing address comparison will stored FIFO. A1En applicable address recognition.
'0', first byte address field will used during address recognition. address recognition enabled, most significant bits first address byte will compared with first bits this register. Table HDLC Address Recognition Register (Read/Write Add. 00110B)
B7-B1
NAME
DESCRIPTION
R2A7-R2A1 seven mask used interrogate second byte received address (where MSB). address recognition enabled, packet failing address comparison will stored FIFO. This mask ignored address Broadcast (i.e., 1111111). A2En '0', second byte address field will used during address recognition. address recognition enabled, seven most significant bits second address byte will compared with first seven bits this register. Table HDLC Address Recognition Register (Read/Write Add. 00111B)
NAME DinB
DESCRIPTION Setting this will initiate activation S-Bus. '0', device will remain present state. Setting this will initiate deactivation S-Bus. '0', device will remain present state. This priority over '1', D-channel will placed timeslot allocating kbit/s D-channel.(1) '0', D-channel will assume position with kbit/s bandwidth.(1) will short passive configuration using fixed timing source compensation line length). will point-to-point extended passive configuration with adaptive timing compensation. This represents state transmitted M/S-bit. when HALF=0 when HALF=1. state this identifies which half frame will transmitted SBus. operation this signal similar that HALF pin. this bit, while HALF will force transmission multiframe sequence bits, i.e., Fa=1 N=0. will resume normal operation, i.e., Fa=0 N=1.
Timing
HALF TxMFR RegSel
register select '1', control register redefined diagnostic register. give access control register. Table Mode C-channel Control Register(2) (Write Add. 01000B
Note Note
Allow ST-BUS frame input C-channel ST-BUS frame establish connection. C-channel Control Register updated once every ST-BUS frame. Therefore, this register should written more than once frame, otherwise, last access will override previous ones.
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B7-B6 NAME Loop DESCRIPTION status these bits determine which type loopback performed: loopback active near loopback digital loopback DSTi DSTo remote loopback '1', device will maintain frame synchronization even after losing framing sequence (i.e., device transmitting INFO2 INFO4 this set, same INFO signal will still transmitted even frame sync sequence received signal lost). '0', synchronization will declared when three consecutive framing sequences have been detected without error. '1', frame sync sequence will violate bipolar violation encoding rule. '0', framing pattern resumes normal operation, i.e., Framing bipolar violation. Setting this will force signal transmitted line. Setting this will force D-echo bits zero. '1', device will operate slave mode. This allows device used terminal equipment line while receiving clocks from external source. register select '1', control register redefined diagnostic register. gives access control register.
FSync
Idle Echo Slave RegSel
Table Mode C-channel Diagnostic Register (Write Add. 01000B
NAME Sync/BA
DESCRIPTION This when device achieved frame synchronization while activation request asserted there deactivation request this indicates presence activity(1). activity identifies reception INFO frames (INFO1 INFO3). Binary encoded state sequence. deactivated pending deactivation pending activation activated Following input HALF HALF C-channel Control Register, state this reflects received maintenance Q-channel (received position during multiframing). This will always read multiframing used. These bits will read '1'. Table Mode Status Register(2) (Read Add. 01001B)
B6-B5
IS0-IS1
RxMCH
B3-B0
Note Note
activity when three zeros received time period equivalent bits reset when consecutive ones received. Status Register updated internally once every ST-BUS frame. Therefore, more than read access frame will return same value.
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NAME DinB DESCRIPTION Setting this will initiate activation S-Bus. '0', device will remain present state. Setting this will initiate deactivation S-Bus. '0', device will remain present state. This priority over '1', D-channel will placed timeslot allocating kbit/s D-channel. '0', D-channel will assume position with kbit/s bandwidth.(1) status this selects priority class terminal equipment. selects high priority selects priority. This used request relinquish D-channel S-Bus when D-channel source ST-BUS. will request D-channel, will relinquish Keep when D-channel source HDLC transmitter. state this will transmitted maintenance channel (Q-channel). will clear contents Diagnostics Register. will enable maintenance functions found Diagnostic Register. This should long device fully active (IS0, 1,1). register select '1', control register redefined diagnostic Register. gives access Control Register.
Priority DReq
TxMCH ClrDia
RegSel
Table Mode C-channel Control Register
Note Note
(Write Add. 01000B
Allow ST-BUS frame input C-channel ST-BUS frame establish connection. C-channel Control Register updated once every ST-BUS frame. Therefore, this register should written more than once frame, otherwise, last access will override previous ones.
B7-B6
NAME Loop
DESCRIPTION status these bits determine which type loopback performed: loopback active near loopback digital loopback DSTi DSTo remote loopback '1', device will maintain frame synchronization even after losing frame sync sequence (i.e., device transmitting INFO3 this set, INFO3 will still transmitted even frame sync sequence received signal lost). '0', synchronization will declared when three consecutive framing sequences have been detected. '1', frame sync sequence will violate normal bipolar encoding rule. '0', framing pattern resumes normal operation, i.e., framing will bipolar violation. '1', signal transmitted line. '0', transmitter will resume normal operation. Unused.
FSync
B2-B1
Idle RegSel
register select '1', control register redefined diagnostic register. gives access control register. Table Mode Diagnostic Register (Write Add. 01000B
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MT8930C
NAME Sync/BA DESCRIPTION This device achieved frame synchronization while activation request asserted there deactivation request that this indicates presence activity(1). activity identifies reception INFO frames (INFO2 INFO4). Binary encoded state sequence. deactivated synchronized activation request activated This respresents state received M/S-bit. when HALF=0 when HALF=1 state this identifies which half S-Bus frame currently being output ST-BUS. when HALF=0 indicates that multiframe pattern been detected. status this indicates internal priority device within designated priority class. then high priority within priority class designated control register. then priority within priority class designated control register. indicates that device gained access D-channel transmitted opening flag. This reset when closing flag last packet TxFIFO transmitted internal priority reduced from high low. collision during transmission will also reset this back `0'. Table Mode Status Register(2) (Read Add. 01001B)
B6-B5
IS0-IS1
HALF RxMFR Priority
DCack
Note Note
activity when three zeros received time period equivalent bits reset when consecutive ones received. Status Register updated internally once every ST-BUS frame. Therefore, more than read access frame will return same value.
B7-B2
NAME INFO1 INFO0 available.
DESCRIPTION
mode, this only when device transmitting INFO1. available mode. mode, this only when device transmitting INFO0. Table Master Status Register (Read Add. 10010B)
These bits used along with status bits distinguish between states F6/F8 F4/F5 device's state machine mode. Please refer "State Machine" section Application Note MSAN-141 further details.
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Applications
MT8930C useful wide variety ISDN applications. Being used both Network Termination (NT) Terminal Equipment (TE) ends line, SNIC finds application digital subscriber line cards full featured digital telephone sets. SNIC combined with MT8971B/72B implement function(with biphase line code interface) shown Figure also combined with MT8910 implement ISDN function (with 2B1Q line code interface) shown Figure MT8930C configured mode, acting master Sinterface line, while MT8971B/72B MT8910 operates slave mode derives timing from U-interface line originating from central office. Figure communication between devices done serial STBUS ports. Control status SNIC communicated with MT8971B/72B through C-channel ST-BUS. Figure illustrates SNIC conjunction with MT9094 implement ISDN telephone set. MT9094 provides such features conversion, handset interface, handsfree operation tone ringer. encoded voice passed from MT9094 SNIC ST-BUS port transmission B-channels. second B-channel available transmission data. These devices have been designed connect together with virtually interconnection components.
MT8930C 1:2*
Both MT8930C MT9094 controlled monitored microprocessor implement various features control functions. Signalling performed scanning keypad generating appropriate messages packetized HDLC section SNIC transmitted Dchannel. twelve segment, non-multiplexed display connected directly S12-S1 outputs provide various status call progress indicators. must noted, that pseudo-ternary line code will tolerate line reversals within pair between However, reversal transmit pair between more will make S-interface inoperable. multidrop applications, powered-off must load line prevent communications between other TEs. avoid such situation, mechanical relay should used disconnect from line transformers.
Interfacing Non-Multiplexed Busses
microprocessor interface SNIC designed around multiplexed architecture which found with most Intel processors/ controllers Motorola processors. event that your choice processors restricted, simple application circuit convert nonmultiplexed bussing that multiplexed architecture. Figure provides interface MC6802 MC6809 microprocessors.
MT8971B/72B DSTi DSTo
DSTo DSTi
LOUT
VBias 1:2*
P/SC Rsti
VREF VBias
0.33 0.33
10.24 XTAL
OSC1
0.33
Star Cmode
OSC2
Converter
terminating resistor
Figure Function
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MT8930C
Microprocessor
Termination Network Lout+ Lin+ MH89101 LinLoutDSTi DSTo Power Supply Power Feed Reference Point DSTo DSTi MT8910-1 DSLIC
MT8930C Mode VBias
10µF
Reference Point terminating resistor
Figure using MT8910-1 (DSLIC) MT8930C (SNIC)
MT8930C VBias Cmode DSTo DSTi DSTi DSTo
MT9094 HSPKR+ HSPKRHandset MMIC+ MICSPKR+ Speaker SPKRMicrophone
Data Port
S12-1 DATA1 SCLK
Display
Converter
8051
terminating resistor
Figure ISDN Digital Telephone
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MT8930C
MT8930C
74HCT245 Address Decoder
MC6802 (MC6809)
AD0-AD7
74HCT245
EXTAL
Connections interface MC6809
Figure Interfacing MC6802 Microprocessor 300-012 NT&TE Line Interface Figures show recommended line interface circuits meeting 300-012 requirements. These circuits assume that test measurements made using "standard reference cord" which following specifications: 315pF 350pF Length Several types transformers used: Filtran TPW-3852-4 (Figure T60403-L4096-X028 (Breakdown Voltage 4KV) (Figure T60403-L4096-X027 Breakdown Voltage 2KV) (Figure T60403-L4096-X029 (Breakdown Voltage 4KV) (Figure T60403-L4096-X030 (Breakdown Voltage 2KV) (Figure L4096-X028 L4096-X027 with exceptions out; L4096-X029 L4096-X030 compatible with L4096-X028-80. Figure (Filtran TPW-3852-4) provides isolation, longitudinal balance, impedance matching voltage level conversion. (germanium) ensure that pulse shape lies within center various pulse templates. D1-4 protect MT8930C from line transients. decouple VBias voltage optimize receiver sensitivity. make low-pass filter recommended delaying signal applications, this filter also used applications allowing common hardware applications. isolates MT8930C from line multidrop applications cases where device powered down. 4-winding common mode choke suppress 4-wire line. TPW-3852-4 available from: Filtran Ltd. Colonnade Road Nepean, Ontario Canada Telephone: (613) 226-1626
L4096-X029 L4096-X030 equivalent
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MT8930C
Figure types diodes (germanium 1N270 schottky MBD301) used D5,6. 1N270 will leave more margin pulse template longitudinal conversion loss. However, MBD301 will leave more margin impedance template. other components described previously Figure Transformers available from: Germany Vacuumschmelze GMBH Postfach D-63412 Hanau Telephone: (49) 6181 Canada Votron Electronic Ltd. Rayette Road Concord, Ontario Telephone: (905) 669-9870 Vacuumschmelze Corporation 4027 Will Rogers Parkway Oklahoma City, 73108 Telephone: (405) 943-9651
Proprietary NT&TE Line Interface proprietary applications, where stringent requirements such 300-012 have met, line interface circuit simpler consequently less expensive. Figure shows such line interface circuit. should chosen according transformer selected desired output signal level, typical values vary from Numerous types transformers used, including following: Filtran Filtran Pulse 8016D (dual with common mode choke) TEW-5660 (surface mount) TPW-3852-4 (single) PE-65495 (dual) L4097-X028-80 (single)
Figure everything same Figure except transformer out.
MT8930C
VBias
Parts List: 0.1µF Ceramic 10µF Tantalum 22pF D1-4 IN914 IN270 Germanium IN4003 Form Relay (eg., Aromat TQ2E-5V) N4025-X034 3k01 Filtran TPW-3852-4
Figure 300-012 Line Interface Filtran TPW-3852-4
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MT8930C
VBias
Parts List: 0.1µF Ceramic 10µF Tantalum 22pF D1-4 IN914 IN270 Germanium MBD301 Schottky IN4003 Form Relay (Aromat TQ2E-5V) N4025-X034 3k01 R2,3 T60403-L4096X027 T60403-L4096X028
Figure 300-012 Line Interface X027 X028
MT8930C
VBias
Parts List: 0.1µF Ceramic 10µF Tantalum 22pF D1-4 IN914 IN270 Germanium MBD301 Schottky IN4003 Form Relay (Aromat TQ2E-5V) N4025-X034 3k01 R2,3 T60403-L4096X029 T60403-L4096X030
Figure 300-012 Line Interface X029 X030
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MT8930C
VBias
RxR4
Parts List: 0.1µF Ceramic 10µF Tantalum D1-4 IN914 circuit description circuit description
Figure Proprietary Line Interface
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MT8930C
Absolute Maximum Ratings*
Parameters Supply Voltage Voltage Current Storage Temperature Package Power Dissipation Symbol VI/O II/O -0.3 -0.3 1000 Units
Exceeding these values cause permanent damage. Functional operation under these conditions implied.
Recommended Operating Conditions Voltages with respect ground (VSS) unless otherwise stated
Characteristics Supply Voltage Input High Voltage* Input Voltage* Load Resistance Load Capacitance (LTx) (LTx) 4.75 250** 5.25 Units 400mV noise margin 400mV noise margin With reference VBias With reference VBias Test Conditions
Operating Temperature
Typical figures 25°C design only: guaranteed subject production testing. Except CK/NT pin. below. Including transformer resistance.
Electrical Characteristics Voltages with respect ground (VSS) unless otherwise stated
Characteristics Supply Current Activated Deactivated Activated Deactivated Input High Voltage except CK/NT Input High Voltage CK/NT Input Voltage except CK/NT Input Voltage CK/NT Output High Current Output Current Input Leakage (except Input Current Output Leakage High Imped. IDDNA IDDND IDDTA IDDTD Units Test Conditions Outputs loaded Outputs unloaded Outputs loaded Outputs unloaded Digital inputs Digital input Digital inputs Digital input VOH=2.4V digital outputs VOL=0.4V digital outputs VOUT
Typical figures 25°C design only: guaranteed subject production testing.
Electrical Characteristics Voltages with respect ground (VSS) unless otherwise stated
Characteristics
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Units
Test Conditions Peak with Ref. VBias VI=1.5Vp Ref. VBias Ref. VBias, RL=250 VO=1.5Vp Ref. VBias, RL=250
Input Voltage Input Current Output Voltage Output Current Input Impedance
(LRx) (LRx) (LTx) (LTx) (LRx)
Typical figures 25°C design only: guaranteed subject production testing.
MT8930C
Electrical Characteristics ST-BUS Timing Mode (Ref. Figure
Characteristics input pulse width Frame pulse (F0b) set-up time Frame pulse (F0b) hold time input clock period pulse width High transition time F0od delay F0od pulse width Serial input set-up time Serial input hold time Serial output delay tFPW tFPS tFPH tP4o tC4W tC4T tDFD tDFW tSIS tSIH tSOD Units load load (HDLC connected ST-BUS) Load Test Conditions
HALF input setup time HALF input hold time
tHAS tHAH
Timing over recommended temperature power supply voltages Typical figures 25°C design only: guaranteed subject production testing.
ST-BUS Cell
tFPW tFPS tC4T F0od DSTi tSOD DSTo tHAS HALF tHAH tSIS tSIH tDFW tC4W tDFD tFPH tP4o tC4W
Figure ST-BUS Timing Mode
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Electrical Characteristics ST-BUS Timing Mode (Ref. Figure
Characteristics output pulse width (F0b) delay (F0b) hold time output clock period pulse width High transition time F0od delay F0od pulse width Serial input setup time Serial input hold time Serial output delay HALF output Delay tFPW tCFD tCFH tP4o tC4W tC4T tDFD tDFW tSIS tSIH tSOD tHAD Units load load Test Conditions load load load load load (activated state) load
Timing over recommended temperature power supply voltages Typical figures 25°C design only: guaranteed subject production testing.
ST-BUS Cell
tFPW tCFD tC4W F0od tSOD tHAD HALF tSIS tSIH tDFW tC4T tDFD tCFH tP4o tC4W
DSTi
DSTo
Figure ST-BUS Timing Mode
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MT8930C
Electrical Characteristics Intel Interface Timing
Characteristics Chip select setup time Chip select hold time Address Latch pulse width Address setup time Address hold time Data setup time Write Data hold time Write Data output delay Read Data hold time Read Write pulse width delay Read pulse width Read setup time tCSS tCSH tALW tADS tADH tDWS tDHW tDOD tDHR tWPW tRWD tRPW tRDS
(Ref. Figure
Units load load Test Conditions
Timing over recommended temperature power supply voltages Typical figures 25°C design only: guaranteed subject production testing. tCSS tALW tADS tADH tDHW Data tWPW tRDS tDWS tCSH
tRWD
AD0-7
Address
Figure Intel Interface Timing (Write Cycle)
tCSS tALW tADS AD0-7 VI/OH VI/OL tRDS Address tRWD tDOD tRPW tADH Data tDHR tCSH
Figure Intel Interface Timing (Read Cycle)
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Electrical Characteristics Motorola Interface Timing (Ref. Figure
Characteristics Chip select setup time Chip select hold time Address strobe pulse width Data strobe setup time Data strobe hold Data strobe pulse width Read/Write setup time Read/Write hold time Address setup time Address hold time Data setup time Write Data hold time Write Data output delay Data hold time Read Write Read tCSS tCSH tASW tDSS tDSH tDSW tRWS tRWH tADS tADH tDWS tDHW tDOD tDHR Units load load Test Conditions
Characteristics clocked operation over ranges recommended operating temperature supply voltage. Typical figures 25°C design only: guaranteed subject production testing.
tCSS
tCSH
tASW tDSS tRWS tADS -AD7 (Write) tADH tDWS tDHW tDSW tRWH tDSH
Address
Data Input tDHR
tADS -AD7 (Read) VI/OH VI/OL
tADH
tDOD
Address
Data Output
Figure Motorola Interface Timing
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MT8930C
Electrical Characteristics Controllerless Mode Timing (Ref. Figure
Characteristics Cmode inputs setup time Mode) Cmode inputs setup time Mode) Cmode inputs hold time Mode) Cmode inputs hold time Mode) Cmode outputs delay Mode) Cmode outputs delay Mode) tCIS tCIS tCIH tCIH tCOD tCOD Units load load Test Conditions
Characteristics clocked operation over ranges recommended operating temperature supply voltage. Typical figures 25°C design only: guaranteed subject production testing. tCIS Inputs tCOD Outputs Mode) Mode) Mode) Controllerless Outputs include: Mode) Mode) Mode) tCIH
Controllerless Inputs include:
Figure Controllerless Mode Timing
Electrical Characteristics IRQ, Rsti Timing (Ref. Figure
Characteristics Interrupt release delay Reset pulse width tIRD tRSW Units Test Conditions
Characteristics clocked operation over ranges recommended operating temperature supply voltage. Typical figures 25°C design only: guaranteed subject production testing.
DS/RD
tIRD
tRSW
Rsti
Figure Rsti Timing
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MT8930C
Notes:
9-70
Package Outlines
Notes: scale Dimensions inches (Dimensions millimeters)
Plastic Dual-In-Line Packages (PDIP) Suffix
8-Pin
0.115 (2.92) 0.014 (0.356) 0.045 (1.14) 0.008 (0.203) 0.355 (9.02) 0.005 (0.13) 0.300 (7.62) 0.240 (6.10) 0.325 (8.26) 0.280 (7.11)
16-Pin Plastic
0.210 (5.33) 0.115 (2.92) 0.014 (0.356) 0.045 (1.14) 0.008 (0.203) 0.780 (19.81) 0.005 (0.13) 0.300 (7.62) 0.240 (6.10) 0.325 (8.26) 0.280 (7.11) 0.195 (4.95) 0.022 (0.558) 0.070 (1.77) 0.014(0.356) 0.800 (20.32)
18-Pin Plastic
0.210 (5.33) 0.115 (2.92) 0.014 (0.356) 0.045 (1.14) 0.008 (0.203) 0.880 (22.35) 0.005 (0.13) 0.300 (7.62) 0.240 (6.10) 0.325 (8.26) 0.280 (7.11) 0.195 (4.95) 0.022 (0.558) 0.070 (1.77) 0.014 (0.356) 0.920 (23.37)
20-Pin Plastic
0.210 (5.33) 0.115 (2.92) 0.014 (0.356) 0.045 (1.14) 0.008 (0.203) 0.980 (24.89) 0.005 (0.13) 0.300 (7.62) 0.240 (6.10) 0.325 (8.26) 0.280 (7.11) 0.195 (4.95) 0.022 (0.558) 0.070 (1.77) 0.014 (0.356) 1.060 (26.9)
Plastic
0.210 (5.33) 0.195 (4.95) 0.022 (0.558) 0.070 (1.77) 0.014 (0.356) 0.400 (10.16)
0.100 (2.54) 0.300 (7.62) 0.115 (2.92) 0.150 (3.81) 0.430 (10.92) 0.060 (1.52)
0.100 (2.54) 0.300 (7.62) 0.115 (2.92) 0.150 (3.81) 0.430 (10.92) 0.060 (1.52)
0.100 (2.54) 0.300 (7.62) 0.115 (2.92) 0.150 (3.81) 0.430 (10.92) 0.060 (1.52)
0.100 (2.54) 0.300 (7.62) 0.115 (2.92) 0.150 (3.81) 0.430 (10.92) 0.060 (1.52)
NOTE: Controlling dimensions parenthesis millimeters.
General-8
Package Outlines
Notes: scale Dimensions inches (Dimensions millimeters)
Plastic Dual-In-Line Packages (PDIP) Suffix
22-Pin
0.115 (2.93) 0.160 (4.06) 0.100 (2.54) 0.400 (10.16) 0.330 (8.39) 0.380 (9.65) 0.125 (3.18) 0.014 (0.356) 0.045 (1.15) 0.008 (0.204) 1.050 (26.67) 0.005 (0.13) 0.390 (9.91) 0.430 (10.92)
24-Pin Plastic
0.250 (6.35) 0.125 (3.18) 0.014 (0.356) 0.030 (0.77) 0.008 (0.204) 1.150 (29.3) 0.005 (0.13) 0.600 (15.24) 0.290 (7.37) 0.485 (12.32) 0.246 (6.25) 0.670 (17.02) .330 (8.38) 0.580 (14.73) 0.254 (6.45) 0.195 (4.95) 0.022 (0.558) 0.070 (1.77) 0.015 (0.381) 1.290 (32.7)
28-Pin Plastic
0.250 (6.35) 0.125 (3.18) 0.014 (0.356) 0.030 (0.77) 0.008 (0.204) 1.380 (35.1) 0.005 (0.13) 0.600 (15.24) 0.670 (17.02) 0.195 (4.95) 0.022 (0.558) 0.070 (1.77) 0.015 (0.381) 1.565 (39.7)
40-Pin Plastic
0.250 (6.35) 0.125 (3.18) 0.014 (0.356) 0.030 (0.77) 0.008 (0.204) 1.980 (50.3) 0.005 (0.13) 0.600 (15.24) 0.670 (17.02) 0.195 (4.95) 0.022 (0.558) 0.070 (1.77) 0.015 (0.381) 2.095 (53.2)
Plastic
0.210 (5.33) 0.195 (4.95) 0.022 (0.558) 0.070 (1.77) 0.015 (0.381) 1.120 (28.44)
0.485 (12.32)
0.580 (14.73)
0.485 (12.32)
0.580 (14.73)
0.100 (2.54) 0.600 (15.24) 0.300 (7.62) 0.430 (10.92) 0.115 (2.93) 0.200 (5.08)
0.100 (2.54) 0.600 (15.24)
0.100 (2.54) 0.600 (15.24)
0.115 (2.93)
0.200 (5.08)
0.115 (2.93)
0.200 (5.08)
Shaded areas Body Width PDIP only
Package Outlines
(lead coplanarity) Notes: scale Dimensions inches (Dimensions millimeters) allowable Mold Protrusion 0.010"
20-Pin
28-Pin
0.165 (4.20) 0.090 (2.29) 0.485 (12.32)
44-Pin
0.165 (4.20) 0.090 (2.29) 0.685 (17.40)
68-Pin
0.165 (4.20) 0.090 (2.29) 0.985 (25.02)
84-Pin
0.165 (4.20) 0.090 (2.29) 1.185 (30.10)
D1/E1 D2/E2
0.165 (4.20) 0.090 (2.29) 0.385 (9.78) 0.350 (8.890) 0.290 (7.37) 0.026 (0.661) 0.013 (0.331)
0.180 (4.57) 0.120 (3.04) 0.395 (10.03)
0.180 (4.57) 0.120 (3.04) 0.495 (12.57)
0.180 (4.57) 0.120 (3.04) 0.695 (17.65)
0.200 (5.08) 0.130 (3.30) 0.995 (25.27)
0.200 (5.08) 0.130 (3.30) 1.195 (30.35)
0.356 0.450 0.456 0.650 0.656 0.950 0.958 1.150 1.158 (9.042) (11.430) (11.582) (16.510) (16.662) (24.130) (24.333) (29.210) (29.413) 0.330 (8.38) 0.004 0.032 (0.812) 0.021 (0.533) 0.390 (9.91) 0.026 (0.661) 0.013 (0.331) 0.430 (10.92) 0.004 0.032 (0.812) 0.021 (0.533) 0.590 (14.99) 0.026 (0.661) 0.013 (0.331) 0.630 (16.00) 0.004 0.032 (0.812) 0.021 (0.533) 0.890 (22.61) 0.026 (0.661) 0.013 (0.331) 0.930 (23.62) 0.004 0.032 (0.812) 0.021 (0.533) 1.090 (27.69) 0.026 (0.661) 0.013 (0.331) 1.130 (28.70) 0.004 0.032 (0.812) 0.021 (0.533)
0.050 (1.27 BSC) 0.020 (0.51)
0.050 (1.27 BSC) 0.020 (0.51)
0.050 (1.27 BSC) 0.020 (0.51)
0.050 (1.27 BSC) 0.020 (0.51)
0.050 (1.27 BSC) 0.020 (0.51)
Plastic J-Lead Chip Carrier P-Suffix
General-10
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