double-polysilicon trench isolated bipolar process optimised applicati

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double-polysilicon trench isolated bipolar process optimised applicati

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Mitel Semiconductor 0.6µm BiCMOS Process
double-polysilicon trench isolated bipolar process optimised applications range 900MHz 2.4GHz, coupled with 0.6µm CMOS dense logic functions.
Base Emitter epitaxy (n-) Oxide Collector
geometry
1.00E-06
Metal3 IMD2 Metal2 IMD1 Metal2 Metal1 Gate Field Oxide Metal1 IMD1
Substrate (p-)
Passivation
1.00E-05
1.00E-04
1.00E-03
1.00E-02
P-Well
Poly2
N-Well
Gate Poly Field Oxide
NMOS
PMOS
Poly1-Poly2 Capacitor
www.mitelsemi.com
PROVISIONAL
Applications: LNAs, Synthesisers, Cellular radios, Wireless LANs, High speed logic. Features:
npn. lateral pnp. Varactor diode. Hi-Res, Mid-Res Lo-Res polysilicon resistors 1400 /sq. CMOS; layout performance compatible with leading Foundry Process. double poly capacitor options. DLM, Integrated Inductors option. Typical Worst-Case models BSIM2 (MOS, BJT, RES, CAP), BSIM3v2 (MOS). noise characterised included model. Interconnect model Diva2D. Models supported TCAD measurement. PCell component library. Diva Dracula verification decks.
transistor, 3.0um emitter
Parameter Condition Value
Passives
Device capacitor (optional) Poly1 Poly2 capacitor (optional) fF/µm2 0.85 fF/µm2 1400
BVCBO BVCEO
Ic=0.6mA, Vce=3V Ic=10µA, Vcb=0 Ic=1µA Ic=5µA Vbe=0 Vbe=0 Vbe=0
>4.5
Hi-Res Poly resistor Mid-Res Poly resistor Lo-Res Poly resistor
Layout Rules
Feature Size (µm)
Lateral
Parameter Condition Value
BVCBO
Ic=40µA, Vce=2V Ic=10µA, Vcb=0 Ic=1µA
>7.5
Transistors
Device (µA/µm) BVDSS
NMOS PMOS
0.90
Active Area pitch Active Area contacted pitch Polysilicon pitch Polysilicon contacted pitch Emitter (minimum) transistor minimum width transistor minimum length NMOS PMOS space Metal1 pitch Metal1 contacted pitch Metal2 pitch Metal2 contacted pitch Metal3 pitch Metal3 contacted pitch
1.35 2.15 0.75
www.mitelsemi.com
PROVISIONAL
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