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Process [C06] Automotive, including standard. Printer Drivers. DC
Top Searches for this datasheet0.6µm CMOS Process [C06] Automotive, including standard. Printer Drivers. DC/DC converters. Switch-mode PSU. Industrial. Display Drivers. Smart Power. power MOS. Communications. Main Process Flow Metal3 IMD2 Metal2 IMD1 Metal1 Gate Field Oxide Poly2 Gate Poly Metal1 Metal2 IMD1 Substrate Well Formation LOCOS Field Oxidation Twin Retrograde Wells Source Drain Formation Gate Formation Gate Formation Poly resistor formation (optional) Poly2 Resistor Capacitor (optional) Inter Layer Dielectric Metal Inter Metal Dielectric Metal Inter Metal Dielectric (optional) Metal Oxide Nitride Passivation Process Features fully-symmetrical CMOS. Industry standard CMOS. High resistance polysilicon resistors. Zener diode one-time programming. Diagrams Passivation P-Well N-Well Field Oxide NMOS PMOS Figure double poly capacitor structure Figure layer metal structure IMD1 IMD1 Metal1 Field Oxide Gate Field Oxide Gate Metal1 HV-Nwell Figure NMOS structure Figure PMOS structure 0.6µm CMOS Process Logic layout performance compatible with industry standard. cell library 5.5k gates/mm2. High resistance polysilicon resistors (optional). Zener diode structure allowing one-off programming (analogous fuse). Double poly capacitor optional. Typical worst-case models BSIM3v3.1 (MOS, BJT, RES, CAP). noise characterised included model. Interconnect model Diva2D. Models supported TCAD measurement. PCell component library. Diva Dracula verification decks. Transistors Device (µA/µm) BVDSS Capacitors Device Area (fF/µm2) NMOS PMOS Poly1 Poly2 Layout Rules Feature 0.85 Size (µm) Transistors Device IDS* (µA/µm) BVDSS NMOS PMOS VDS=VGS=40V. Resistors Device Poly1 High Poly1 Poly2 P-diffusion N-diffusion N-Well (/sq.) 1000 1050 Active Area pitch Active Area contacted pitch Polysilicon pitch Polysilicon contacted pitch Transistor minimum width Transistor min. length Transistor min. length Metal1 pitch Metal1 contacted pitch Metal2 pitch Metal2 contacted pitch Metal3 pitch Metal3 contacted pitch Via1 placement restricted? Via2 placement restricted? 1.35 2.15 0.75 Zarlink Semiconductor, Tamerton Road, Roborough, Plymouth, Devon, 7BQ. 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