Process SC/SD [C06] Mixed signal embedded systems systems chip (S

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Process SC/SD [C06] Mixed signal embedded systems systems chip (S

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0.6µm CMOS
Process SC/SD [C06]
Mixed signal embedded systems systems chip (SOC). High precision mixed signal circuits. Low-power mixed signal circuits. Analogue frontends sensors. Communications, consumer, automotive industrial markets.
Main Process Flow
Substrate Twin Wells LOCOS Field Oxidation Gate Formation (14nm) Poly2 Resistor Capacitor (optional) Inter Layer Dielectric Metal Inter Metal Dielectric Metal Inter Metal Dielectric (optional) Metal Oxide Nitride Passivation
Process Features
Industry standard core process. Double poly capacitor (optional). Well characterised exacting mixed signal designs.
Diagrams
Passivation Metal3 IMD2 Metal2 IMD1 Metal1 Gate Field Oxide Metal1 Metal2 IMD1
P-Well
N-Well
Poly2 Gate Poly Field Oxide
NMOS
PMOS
Figure Double poly capacitor structure.
Figure layer metal structure.
0.6µm CMOS Process
Logic layout performance compatible with industry standard. operation. Double poly capacitor optional. Process production fully documented characterised. Typical models BSIM2 (MOS, BJT, RES, CAP), BSIM3v2 (MOS). Worst-case model BSIM2, BSIM3v2 (MOS). noise characterised included model. Interconnect model Diva2D. Models supported TCAD measurement. PCell component library. Diva Dracula verification decks.
Transistors
Device (µA/µm) BVDSS
Layout Rules
Feature Size (µm)
NMOS PMOS
0.78 0.90
Device
Area (fF/µm2)
Capacitors Poly1 Poly2 Resistors
Device
0.85
(/sq.)
Poly1 Poly2 P-diffusion N-diffusion N-Well
1050
Active Area pitch Active Area contacted pitch Polysilicon pitch Polysilicon contacted pitch Transistor minimum width Transistor minimum length NMOS PMOS space Metal1 pitch Metal1 contacted pitch Metal2 pitch Metal2 contacted pitch Metal3 pitch Metal3 contacted pitch Via1 placement restricted? Via2 placement restricted?
1.35 2.15 0.75
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Process SC/SD [C06] Mixed signal embedded systems systems chip (S

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