Systen Controller Data Modem Advance Information DS4290 ISSUE Jan
|
|
|
Top Searches for this datasheet
ACE9050
Systen Controller Data Modem Advance Information
DS4290 ISSUE January 2001
ACE9050 provides control interface functions needed AMPS TACS analog cellular handsets. device been designed using Zarlink Semiconductor submicron CMOS technology power high performance. ACE9050 contains embedded microcontroller peripheral functions. controller 6303 type with Serial Communication Interface, Timer, RAM. peripheral functions are: Data Modem, Management, Serial Chip Interfaces, Interface, Pulse Width Modulators, Counter, Tone generator, ports, Watchdog Crystal Oscillator. Several power down modes incorporated device processor emulation mode software system development. index this data sheet given pages
Ordering Information
Industrial temperature range. TQFP 100-lead 14314mm, pitch package (FP100) ACE9050C FP8N: trays packed ACE9050C FP8Q: tape mounted packed
TESTN XOUT DFMS BAUDCLK SCL/P1 SDA/P1
Features Power, Voltage Operation Memory Interface Power Down Emulation Modes 6303R-type Microcontroller AMPS TACS Modem Watchdog Power Control Logic Detection, Generation Loopback bytes Interface FLASH EEPROM Memories byte Boot Block Ports Keyboard Scanning Controller Small Outline 100-pin package Applications AMPS ETACS Cellular Telephones Two-way Radio Systems Related Products
ACE9050 part Zarlink Semiconductor's chipset, together with following: ACE9020 Receiver Transmitter interface ACE9030 Radio Interface Twin Synthesiser ACE9040 Audio Processor
OUTP2 LATCH1 OUTP2 LATCH0 PWM2 DTFG EMUL IRQN POFFN EXRESN C1008 CPUCL DTMS PWM1 ECLK RXCD
LATC SERV SYNTHCLK SYNTHDATA INRQ0 INRQ1 TXDATA TXSAT TXPOW AFC/RXDATA INP1[4] INP1[3] INP1[2] RXSAT
ACE9050
BA17 BA16 BA15 BA14 VDDM CSE2N CSEPN
FP100
Figure connections view. identified moulded spot coding orientation. Table detailed descriptions.
CLOCK BAUD GENERATOR MEMORY INTERFACE WATCHDOG POWER CONTROL INTERRUPT CONTROL
PORTS
KEYPAD INTERFACE ACEBus INTERFACE
Absolute Maximum Ratings
Supply voltages VDD, VDDM Storage temperature Operating temperature Voltage 255°C 1150°C 240°C 185°C
6303R MICROPROCESSOR UART (SCI) TIMER PORTS
INTERFACE 23PULSE WIDTH MODULATOR
AMPS TACS DATA MODEM COUNTER MANAGEMENT TONE GENERATOR
Figure ACE9050 simplified block diagram
ACE9050
Advance Information
SYNTHDATA SYNTHCLK DTFG LATCH0 LATCH1 LATCH3
SYNTHDATA SYNTHCLK DTFG LATCH0
SERIAL INTERFACE
ONRAD SINTSLEEP C1008 IRQSEND IRQREC
PORT3[6] PORT4[7]
PULSE WIDTH MODULATOR
DAC1 DAC2
OUT2 CONTROL PORT5 PORT5 [5:4] OUT2 LATCH2
CONTROL
}INTERRUPTS
ID[7:0]
OUTP2 [1]/ PWM1 OUTP2 [2]/ PWM2/ LATCH2
LSICOM0 LSICOM1 LATCH1 LSICOM2 LSICOM3 LATCH3 LSICOM4 LSICOM5 LATCH2 LSICOM6 ID[7:0] STR_WIDTH
INTERNAL PORTS
EXTERNAL PORTS
OUT2 BONDED CPUCL POWERDET SERV
6303 18-25 46-41 92,93 40,39,35-30 EMUL EMUL
REFER TEXT INDIVIDUAL FUNCTIONS
EMULATION DATA INTERNAL ADDRESS
PORT3 [7:0] PORT4 [7:0] PORT5 [7:0]
PORT3 PORT4 PORT5
PORT3 PORT4 PORT5
PORT2
OUT_PORT2
OUT2 OUT2 [5:3] OUT2 OUT2 OUT2
OUTP2 OUTP2
EMUL [7:0] [7:0] [13:8] [15:14] [17:14] CSE2N CSEPN
INTERFACE
EMUL ONLY EMUL EMUL DATA/AD ID7:0 AD15:0
ID[7:0] LVN1
PORT1
IN_PORT1 [7:0]
INP1 INP1 INP1 [4:2] INP1 [1:0]
INP1 [4:2]
6016 BYTES (IRAM)
[12:0] IRAM
IRQE
EXT. INTERRUPTS
IRQPRT4-RESET IRQPRT5-MASK IRQPRT6-READ 59-55 66-69
INRQ [1:0]
50-47
MEMORY BANK SWITCHING EPROM
BANK_SEL ID[4:0] AD[15:14]
BYTES (IROM) BOOT BLOCK
[7:0] [8:0] IROM
KEYPORT/CHIP
KEYP PORT KPOT TRISTATE ID[7:0] ISDA ISCL
[4:0] [3:0]
IN_PORT1 OUT_PORT2
IRQPRT4
DECODER
IRQPRT5 IRAM EPROM IROM IROME
ACE9050 REGISTER SELECTS MEMORY SELECTS
PORT4 PORT3
6303 MICROPROCESSOR ID7:0 READ/WRITE KERNEL
AD15:O EMUL COUNTER RESET CLOCK
PORT1 [7:0] PORT2 PORT2 BAUDCLK
7-9, 12-16
INTERRUPT IRQN 83BAUD
[7:0] DFMS/P2 DTMS/P2 IRQN BAUDCLK
BAUD RATE CLOCK
PORT5 ENABLE RESET I2C_ADDR I2C_DATA I2C_CNTR ISCL I2C_INTERRUPT IRQTX IRQWS IRQBISAT IRQRX IRQREQ IRQSEND IRQTO ID[7:0]
IRQN INTERRUPT IRQE (EXTERNAL INT.) IRQPRT0-RESET IRQPRT1-MASK IRQPRT2-READ
AD[15:0] SLEEP
BEEP ALARM RING GENERATOR (BAR)
BARENABLE BARHIGH BARLOW ID[7:0] CLKBUS 126kHz
I2C_STAT I2C_CCR
ISDA
TESTN CLKBUS ID[7:0]
INTERRUPT CONTROL INTERRUPT SOURCE ID[7:0]
OUT2 WATCHDOG
6303
(EMUL) AFC/RXDATA
COUNTER
IFFREQ (2432/256) STIFCN (START/RESET) PORT3 PORT3
INTERRUPTS
PORT4 PORT3 PORT3
IRQRX IRQBISAT IRQWS IRQTX AFC/RXDATA NOMPLL MDMSLP ENMOD
MODEM
MODPRT0 MODPRT1 MODPRT2 [7:0] BARPORT TEST ACCESS ONLY TXDATA C1008 PORT5 PORT4 PORT3 PORT5 P[1]
CLOCK GENERATOR
XOSC-PD TURBO ENSIS CLKENAB (CPU CLOCK) CLKBUS C1008 LVN1 CPUCL
54kHz/450kHz
VDDM
INP1
CPUCL/ OUTP2 C1008 ECLK XOUT TESTN
WATCHDOG
REWD MASTER RESET WATCHDOG RESET LOGIC RESATO FILTER LOGIC IRQTO LVN1
MANAGEMENT
PORT4 SELECT GENERATOR
SERV
TXDATA TXSAT RXSAT EXRESN
RXCD TXPOW
POFFN
CLKBUS TESTN INP1 POWDET PORT3 UPOFFN
Figure Detailed block diagram ACE9050
Advance Information
FUNCTIONAL OVERVIEW
MICROPROCESSOR UNIT processor unit program compatible with standard 6303R. contains following hardware: 8-bit Serial Communication Interface: (UART) 16-bit timer/counter 8-bit port (P1) 2-bit port (P2) processor speed either MHz. Emulation mode provided whereby internal 6303 bypassed allow software development standard 6303 In-Circuit Emulator (ICE). MEMORY ACE9050 contains bytes ofROM 6144 bytes internally. code facilitates system initiation after reset programming FLASH memory 6303 (UART). Internal area represents total requirement anticipated cellular phone. INTERFACE MEMORY BANK SWITCHING These blocks create Data, Address Control lines external memory. external address expanded from standard bits bits banked addressing scheme. This increases memory address space from 256K. programmable Chip Selects (CSEPN CSE2N) generated. Memory Interface will operate down 13V, allowing voltage memory parts. Emulation mode external processor controls ACE9050 Interface block. EXTERNAL PORTS ACE9050 contains Keypad Interface ports, maskable external interrupts, both Input Output ports. These addition 6303 bidirectional Port1 Port2. Output port provides high current outputs driving LEDs. DECODER INTERRUPT CONTROL Decoder block memory maps ACE9050 register locations onto processor's address space. Interrupt Control block handles both internal external interrupt sources. These into control logic allowing individual masking reset software. Interrupt control logic output internally connected 6303 also drives external pin. SERIAL INTERFACE (SINT) Three serial interface protocols supported: UART, ACEBus. 6303 provides UART interface block.
ACE9050
ACE9050 block provides interface with both Master Slave capability. ACEBus designed with Chipset data rate just over 1MBits/sec. Three Latch pulse available target data relevant control ACE9030 Synthesiser. BEEP, ALARM RING TONE GENERATOR (BAR) Generator intended drive acoustic tone transducer. programmable single digital pulse train output. MODEM MANAGEMENT Modem provides data transfer management over radio link between base station phone handset. AMPS TACS data rates supported Modem block contains: Digital Discriminator, Data Decoder Word Synchronising hardware. Various modes selected software. squelch level also software that quality each data byte assessed. detection generation standard three frequencies 5970Hz, 6000Hz 6030Hz included. WATCHDOG POWER CONTROL (ATO) Watchdog function will provide internal external Reset processor does make write access defined address every seconds. Autonomous Time circuit (ATO) will drive POFFN output Transmitter power detected without Receiver power, independent processor operation. POFFN must used conjunction with external regulators control power mobile handset. CONTROL COUNTER (IFC) Intermediate Frequency Control (IFC) Counter used part Loop. Counter provides pulse after number input pulses. Counter output connected 6303 timer input external (ICN). TWIN PULSE WIDTH MODULATORS independently programmable Pulse Width Modulators (PWMs) available. These provide digital output pulse trains, controllable software. output filtered externally provide function. Typical applications battery charging control contrast control. CLOCK GENERATOR Clock Generator provides various internal external clocks from single source. source either external crystal ACE9030.
ACE9050
Name TESTN XOUT DFMS/P2 BAUDCLK P1[7] P1[6] P1[4]/SCL P1[5] P1[3]/ P1[2] P1[1] P1[0] CSEPN CSE2N VDDM BA14 BA15 BA16 BA17 RXSAT INP1 INP1 INP1 AFC/RXDATA TXPOW TXSAT TXDATA
Advance Information
DESCRIPTIONS
Type Block CLK/WDATO BINT BAUD BINT BINT BINT BINT BINT BINT BINT BINT MEMB MEMB BINT BINT BINT BINT BINT BINT Description Connect Crystal connection CMOS input: Crystal connection Port2 Serial interface (SCI) output Address strobe (Latch Address during Emulation) Baud Rate Gen. output Emulation (lnput test mode) PORT PORT PORT CPU/I2C Ground Digital Supply PORT PORT CPU/I2C PORT PORT PORT Ground Data (and Emulation Address Input) Data (and Emulation Address Input) Data (and Emulation Address Input) Data (and Emulation Address Input) Data (and Emulation Address Input) Data (and Emulation Address Input) Data (and Emulation Address Input) Data (and Emulation Address Input) Output Enable Write Enable External EPROM External EEPROM Address Address Address Address Address Address Ground Ground Digital Supply Memory Interface (pins18-35, 38-50) Address Address Address (Input during Emulation) Address (Input during Emulation) Address (Input during Emulation) Address (Input during Emulation) Address (Input during Emulation) Address (Input during Emulation) Address (Extended Address: From Bank Select Register) Address (Extended Address: From Bank Select Register) Address (Extended Address: From Bank Select Register) Address (Extended Address: From Bank Select Register) Received input Input Port1 Input Port1 Input Port1 Keypad scan output/output port Keypad scan output/output port Keypad scan output/output Keypad scan output/output port Keypad scan output/output port 54/450kHz input fromACE9030 Power detect from transmitter Output TACS AMPS Modem Output Digital Supply Digital Supply Table Internal None None None None None None None None None None None None None None None None None None None None None None None None None None None None None None Cont.
BINT BINT BINT BINT BINT BINT BINT BINT MEMB MEMB MEMB MEMB MODEM EPORT EPORT EPORT EPORT EPORT EPORT EPORT EPORT IFC/MODEM WDATO MODEM MODEM
Advance Information
Name INRQ1 INRQ0 SYNTHDATA SYNTHCLK SERV LATCH3 OUTP2 LATCH1 OUTP2[7] LATCH0 OUTP2[2]/PWM2/ LATCH2 DTFG EMUL IRQN POFFN EXRESN C1008 CPUCL/OUTP2 DTMS OUTP2 [1]/PWM ECLK RXCD Type Block EPORT EPORT EPORT EPORT EPORT EPORT SINT SINT WDATO SINT EPORT SINT EPORT SINT Description
ACE9050
Internal None None None None None None None
Keypad scan input/input port Keypad scan input/input port Keypad scan input/input port Keypad scan input/input port External Interrupt (also Bit1 Input Port1) External Interrupt (also Bit0 Input Port1) SynthBus Data Line SynthBus 126kHz Clock Service Mode Latch, programmable length. ACE9030, LATCHC pin) Output Port2 High Current Driver Counter Output Emulation (input Test mode) Latch ACE9030 receiver Interface, LATCHB pin) Output Port2 High Current Driver Latch ACE9040, Output Port2 2/Pulse Width Modulator Output/ SynthBus Latch O/P. SINT Bidirectional serial inter-chip data, to/from ACE9030 BINT/CPU Emulation Mode Interrupt Emulation (input Test mode) WDATO Power On/Off Ground Ground Digital Supply WDATO External reset output Clock ACEBus, ACE9030 ACE9040 WDATO Chip reset BINT Address input Emulation only BINT Address input Emulation only CLK/EPORT 8.064MHz clock/Out Port BINT Read/Write (Input during Emulation) Beep, Alarm, Ring Tone Output Port Serial interface (SCI) input Output Port 1/Pulse Width Modulator Output Processor Clock (Input during Emulation) WDATO Carrier detect from Table (continued) MODEM SINT WDATO interface Control counter AMPS/TACS Modem Pulse Width Modulator Serial Inter-chip interface Watchdog/Autonomous Time Internal Pullup resistor present Internal Pulldown resistor present
ABBREVIATIONS Beep, Alarm Ring tone generator BAUD Baud Rate generator BINT Interface MEMB Memory Bank switching Clock generator 6303 microprocessor unit Decoder EPORT External Port
UNUSED INPUTS Input bidirectional pins must have suitable pullup pulldown reststor they configured inputs, with external drive. Some inputs have internal pullup pulldown resistor order 100k; this value suitable subject excessive noise residual current greater than 15µA. pins shown Table used system, external resistor will required. DFMS Name Name RXSAT INP1 INP1 INP1 AFC_IN/RXDATA Table Name TXPOW SERV DTFG (Requires programming resistor) DTMS RXCD
NOTE: [7:0], DFMS DTMS configured inputs upon reset.
ACE9050
Advance Information
ELECTRICAL CHARACTERISTICS
Electrical Characteristics guaranteed over following range operating conditions (unless otherwise stated): TAMB 240°C 185°C, VDDM (note
CHARACTERISTICS
Value Characteristic Supply current (Normal clock) Supply current (Turbo clock) Supply current (Static) Input high voltage Input voltage Output high voltage Output voltage High current drive source (pins High current drive sink (pins Tristate leakage current Input leakage current Pullup/down resistance Symbol IDDNOR IDDTUR IDDSB IOHHI IOLHI Min. Typ. Max. Units Conditions ECLK, ECLK, clock osc. powered down
2mA, 1mA, 2mA, Pullup/down cell Pullup/down cell TAMB 25°C
NOTES Characteristics Min. figures guaranteed test. voltage VDDM must less than equal VDD.
CHARACTERISTICS (CLOCKS CRYSTAL)
Value Characteristic Oscillator frequency Oscillator external coupling capacitor External resistor External capacitors Crystal Startup time Radio serial control Microprocessor clock Microprocessor clock Clock output Watchdog time Autonomous time Symbol fOSC CCOUPLE XTALESR C1008 ECLK1 ECLK2 CPUCL WDTO ATOTO Min. Typ. 1000 Max. Units Conditions External crystal CMOS/800mV sine coupled Sine input Crystal oscillator Crystal oscillator (note Crystal oscillator Crystal oscillator Normal clock Turbo clock Output enabled Normal Mode Normal Mode
NOTES Refer crystal manufacturer exact deatils.
Advance Information
TIMING DIAGRAMS
NORMAL MODE PROCESSOR INTERFACE
Read Cycle
ACE9050
tECLK
ECLK
ADDR
tCSLCLL
tCLLADI tCLLCSH
tADVCSL tOELCLL
tCLLOEH
tDAVCLL
DATA
tCLLDAI
Figure ACE9050 6303 Read cycle timing diagram
Timing Cycle Conditions
Input clock frequency, Worst case Timings: TAMB 240°C 185°C, Typical timings: TAMB 125°C, Normal clock Description Cycle time Address valid Chip Select set-up time set-up time Data set-up time Data hold time hold time hold time Address hold time Symbol Min. Typ. Max. Min. Turbo clock Typ. Max. Units
tECLK tADVCSL tCSLCLL tOEL tDAVCLL tCLLDAI tCLLOE tCLLCSH tCLLADI
Table ACE9050 6303 Read cycle timing
ACE9050
Advance Information
Write Cycle (Normal Mode)
tECLK
ECLK
ADDR
tADVWEH
tWEHADI
tADVCSL
tCSLWEH
tWELWEH
DATA
tWEHCSH
tADVDALZ
tDAVWEH
tWEHDAI
Figure ACE9050 6303 Write cycle timing diagram
Timing Cycle Conditions
Input clock frequency, Worst case timings: TAMB 240°C 185°C, Typical timings: TAMB 125°C, Normal clock Description Cycle time Address valid Write Address hold time Chip enable set-up time pulse width Data valid set-up time Data hold time Address valid data Address valid chip select high high Symbol Min. Typ. Max. Min. Turbo clock Typ. Max. Units
tECLK tADVWEH tWEHADI tCSLWEH tWELWEH tDAVWEH tWEHDAI tADVDALZ tADVCSL tWEHCSH
Table ACE9050 6303 Write cycle timing
Advance Information
EMULATION MODE PROCESSOR INTERFACE Read Write Cycles
tCYC
ECLK
ACE9050
tECLRWV
INVALID STABLE INVALID
tECLADV
A[15:8]
tECLADI
tADVASL
A[7:0]/D[7:0] AD[7:0]
tASLADI
tDAV
DA[7:0]
tDAI
Figure ACE9050 6303 Emulation mode Read/Write cycles timing diagram
Emulation Mode Timing Cycle Conditions
Input clock ECLK frequency (Normal clock), (Turbo clock), TAMB 125°C, 610% Normal clock Description Cycle time Read/Write settling time Address delay time Address hold time Address latch set-up time Address latch hold time Data set-up time WRITE Data hold time WRITE Data set-up time READ Data hold time READ Symbol Min. Typ. Max. Min. Turbo clock Typ. Max. Units
tCYC tECL tECL tECL tADV tASLADI tDAV tDAI-W tDAV tDAI-R
Table 6303 Emulation Mode Read/Write cycles timing
ACE9050 Advance Information SERIAL INTERFACE BLOCK
ACEBus Read Write Timings
C1008 DATA1 LATCH1 DATA2 DATA3
DATA
Fig.7 ACEBus Transmit Data flow
C1008 DATA DATA3 LATCH1 PREAMBLE RESULT1 RESULT2
Fig.8 ACEBus Receive Data flow
tCLH tCLL
tDAVCLH
C1008
tCLHDAI
tCLLDAZ
DTFG
D1-7
D1-6
D3-2
D3-1
D3-0
tCLHDA
SYNTHDATA
LATCH0/1/3
tCLHLAH
Fig.9 ACEBus Transmit timing diagram
C1008
DTFG
tDAVCLL
Fig.10 ACEBus Receive timing diagram
tCLLDAI
Advance Information
ACEBus Timing Cycle Conditions
ACE9050
Input clock frequency, Worst case Timings: TAMB 240°C 85°C, Typical timings: TAMB 125°C, Value Characteristic TRANSMIT Clock high Data driven Data set-up time Data hold time Clock high Latch high Latch width Latch width Clock Clock high Clock high data line tristate RECEIVE Data set-up time Data hold time Symbol Min. Typ. Max. Units Conditions
tCLHDA tDAVCL tCLHDAI tCLHLAH tPW01 tPW3 tCLL tCLH tCLHDAZ tDAVCL tCLLDAI
Programmable width
Table ACEBus Read Write timings
SynthBus (Note: SynthBus required when ACE9050 used part Chipset)
tD17VCLH
SYNTHCLK
tCLH tCLL
SYNTHDATA
D1-7
D1-6
D3-1
D3-0
tDAVCLH
DTFG
tCLHDAI
LATCH
tCLHLAH
Figure SynthBus timing diagram
tLAH
SynthBus Timing Cycle Conditions
Input clock frequency, Worst case Timings: TAMB 240°C 185°C, Typical timings: TAMB 125°C, Value Characteristic First data set-up time Data set-up time (except first) Data hold time Clock high latch high Latch width Clock Clock high Symbol Min. Table SynthBus timing Typ. Max. Units Conditions
tD17VCLH tDAV tCLHDAI tCLHLAH tLAH tCLL tCLH
ACE9050
Advance Information
INTERNAL REGISTERS RESET STATUS
ACE9050 REGISTERS
Name IN_PORT1 OUT_PORT2 PORT3 BARPORT IRQPRT2 IRQPRT6 MODPRT0 MODPRT1 MODPRT2 KEYP LSICOM4 LSICOM5 LSICOM6 PORT4 PORT5 BANK_SEL RESERVED BARHIGH BARLOW BARENABLE I2C_ADDR I2C_DATA I2C_CNTR I2C_STAT I2C_CCR DAC1 DAC2 LSICOM0 LSICOM1 LSICOM2 LSICOM3 STR_WIDTH KPOT REWD RESAT0 IRQPRT0 IRQPRT1 IRQPRT4 IRQPRT5 Address 22-23 24-25 26-27 28-29 2C-2D 2E-2F 30-31 32-33 34-35 36-37 3A-3B 3C-3D 3E-3F 40-41 42-43 60-61 62-63 64-65 68-69 6A-6B 6C-6D 70-71 72-73 74-75 76-77 Description External Port External Port Internal Port Test-Do Access Read Interrupts Read Interrupts Modem Modem Modem Chip Interface Interface Interface Internal Port Internal Port Bank Select Access UART Baud select data Data Interface Interface Interface Interface Control Latch Width type Reset Watchdog Reset Time Reset Interrupts Mask Interrupts Reset Interrupts Mask Interrupts D7-0 reset condition
EE0EEE00
Notes
00000000 00000000 111X111 XXXX1111 00000000 00000000 00000000 0010EEEE
EEEEEEEE EEEEEEEE EEEEEEEE
00000010 00000011 XXX00000 00000000 00000000 XXXXXX0 XXXXX000 00000000 00000000 00000000 11111000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 XXX11111
XXXXXXXX XXXXXXXX
00000000 (Reset) 00000000 (Masked) XXXX0000 XXXX0000
Table ACE9050 ports NOTES: SERV mode. Bits corresponding interrupt enabled (inverse IRQPRT6). (UPOFFN) SERV mode, reset Normal mode. used should treated undetermined. LSICOM4, ports values will depend DTFG input. SERV mode Boot block will 00000100 (9600 Baud). Depends external input. used undetermined.
Advance Information
ACE9050 6303 REGISTERS
Name DDR1 DDR2 PORT1 PORT2 TCSR FRC_HIGH FRC_LOW OCR_HIGH OCR_LOW ICR_HIGH ICR_LOW RMCR TRCSR RAMCR Address Description Data Register Data Register Data Port Data Port Timer Control/Status Free Counter Free Counter Compare Compare Capture Capture Rate Mode Control Tx/Rx Control Status Data Data Used Table 6303 ports
NOTES: Both ports Input I/P, O/P) external input 6303 internally Multiplexed mode Unused undetermined 00001100 SERV mode 00111010 SERV mode This register Read only ACE9050
ACE9050
Notes
D7-0 reset condition 00000000 00000000
EEEEEEEE 010XXXXX
00000000 00000000 00000000 11111111 11111111 00000000 00000000 XXXX0000 00100000 00000000 00000000 00000000
MODES OPERATION
ACE9050 three independent modes operation: Normal, Emulation, Service. Mode Emulation Service Normal EMUL SERV Enabled High High Default mode D[7:0] A[13:8] A[15:14] ECLK IRQN Normal mode Function Type Data Address used 6303 used used used used Emulation mode Function Data A[7:0] Address A[13:8] Address A[15:14] ACE9050 Clock Read/Write strobe Address Latch strobe 6303 Interrupt 6303 Timer Type
Table Modes operation
NORMAL MODE
This intended mode operation when ACE9050 fully commissioned application. internal 6303 Microprocessor used Boot block ensures program counter goes beginning code area after initialisation. Normal mode various blocks powered down save current, processor programmed
Table Normal Emulation mode functions
SERVICE MODE
This mode intended system development phone service, where reprogramming FLASH device required. areas that affected Service mode are: Watchdog Autonomous Time (ATO) resets inhibited. This intended software development work. POFFN (85) initially programmed code this mode. internal code facilitates loading program into area from SCI. This program would normally FLASH loading program. then used load object code into FLASH memory system.
EMULATION MODE
This mode intended system software development work. Emulation mode Internal 6303 processor made redundant function replaced system external 6303 processor. This facilitate using generic 6303 In-Circuit Emulator (ICE) software development. Table shows functionality external pins that change this mode. This enable internal functions ACE9050 operate they would Normal mode. Emulation mode external processor must operate Multiplexed mode. This mode only intended room temperature.
ACE9050
Advance Information
Name XTAL External Port2 Port2 Port2 Port2 Port2 Port1 [7:0] Addr [15:8] [7:0] STBY I/O* I/O* Description Internal power supply Internal Ground connected Used (System Clock Driven into directly) System Clock used: Tied Connected Interrupt Control block IRQN Connected Internal Reset Internally connected Counter connected Internally connect Baud External (SCI Port2) External (SCI Port2) External (Port1 Access) Connected internal address Internally connected Buses Connected internal logic Connected internal logic Standby mode disabled
code time function that valid start code detected normal code operation will begin. code fully described Internal Boot Block section.
TEST MODE
Test mode increases efficiency volume testing part. TESTN, should hardwired VDD.
POWER DOWN MODES
reduce overall power consumption, selective power down various blocks available under software control. power down state each block will predetermined logic state. following power reduction features included: Interface (CSEPN Address 3FFF) external Clock external Clock AMPS/TACS Modem power down Serial Chip Interface Power down Sleep Mode Crystal Oscillator 1MHz/2MHz speed
FUNCTIONAL DESCRIPTIONS
ACE9050 6303R DESCRIPTION General Description
embedded processor ACE9050 functionally equivalent generic 6303R micro. This data sheet outlines functionality embedded processor, detailing operation with internal peripheral circuitry. intended programmers guide 6303. further information required following publications recommended:
*Port2 bits must configured inputs 6303
Baud rate generator functions.
Table Generic 6303 mapping Port This eight port with direction each being defined data direction register DDR1 given Table Port accessed read write Port1 register. output buffers have tristate capability, being high impedance when used inputs. When processor reset these high impedance. pins (Bits associated with this port also used from interface ACE9050. This configured Port 6303 internally configured mimic Multiplexed mode operation, this port cannot configured output lower address bits. ACE9050 dedicated pins this purpose. Associated Registers Name DDR1 Bits Port Bits [7:0] Description Sets corresponding Port line output Sets corresponding Port line input Read Write access Port
HITACHI 8-bit single-Chip Microcomputer Data Book Sept.1989 Motorola Microprocessors Data Manual Macro Assemblers Reference Manual, Motorola Semiconductors MC68MASR(D).
6303 8-bit processing unit which completely compatible instruction with 6301. object code upwardly compatible with HD6300, HD6801 HD6802. ACE9050 6016 bytes internal (the 6303R bytes). Other features are: Serial communications interface (SCI UART), 16-bit timer, 8-bit port 5bit port (only bonded from ACE9050). speed configured Normal mode Turbo mode. ACE9050 Emulation mode whereby internal 6303 bypassed peripheral functions driven externally standard 6303 ICE.
ACE9050 6303R Description
ACE9050 6303 embedded kernel which interfaces rest circuitry. Table describes internal connections ACE9050 6303. Emulation mode, none output pins drive internal buses. Clock Clock provided from Clock Generator Circuit ACE9050. This clock either further divided down 6303, this clock frequency same processor speed. Refer Clock Generator section details configure internal clocks.
Table Port associated registers
Port This five-bit port with direction each being defined data direction register DDR2. Only connected external pins. This allows access port Serial Interface functions. internally connected Baud clock. They must configured inputs these functions. externally accessible. ACE9050 additional Output Port which separate from 6303 Port
Advance Information
Name DDR2* Bits [4:0] Port Bits [4:3] Description Sets corresponding Port line output Sets corresponding Port line input Read Write access Port Table Port associated registers
ACE9050
Serial Communication Interface (SCI UART)
processor contains full-duplex asynchronous Serial Communications interface. consists transmitter receiver which operate independently with same data format rate. Both parts communicate with data outside world Port Interrupts generated individually masked. receiver sent `sleep' software. receive interrupts generated during message this state. Baud rate generated within ACE9050 6303 ACE9050 provide baud rate generator selection register external processor block. This allows following standard baud rates programmed: 600,1200. 2400, 4800 9600. hardware consists four registers: 8-bit control/ status register, 4-bit mode select, 8-bit receive data 8-bit transmit data register. Name Description
*The TRCSR register overrules these registers.
Programmable Timer
ACE9050 6303R contains programmable timer which measure period input waveform, with standard 6303R. This counter runs from ECLK. counter cannot generate output waveform. input timer internally connected counter loop function. timer hardware consists 8-bit status control register, 16-bit free running counter 16-bit input capture register. TCSR (Timer Control Status Register) Control Status register three flags: Input capture, Output Compare Match Timer Overflow. Each flag associated interrupt enable. other bits register control output level input edge select. bits described Table Name Description Transition appropriate type occurred input (ICN). Cleared read Input Capture register Match between Free Running Counter Output Compare Register* Timer overflow. Cleared read counter. Enable interrupt Enable interrupt* Enable Timer overflow interrupt Negative edge trigger Positive edge trigger Output level*
RDRF Data Register Full* ORFE Overrun/Framing Error* TDRE Data Register Empty Interrupt Enable: Enables interrupt both Enable. This sets Port2 Input regardless DDR2 Interrupt enable: will generate Interrupt Enable: This sets Port2 Output regardless DDR2 Wake software cleared hardware.**
EICI
EOCI ETOI IEDG OLVL
Overrun where data placed Receive register before data been read. Framing Error where counter synchronised with boundary byte Received stream defined Table Wake mode intended systems where more than Processor UART link, addressed first byte data. address incorrect processor disable interrupts effectively ignore word.
Table TRCSR: Transmit/Receive Control Status Register descriptions Condition Data Good Data Framing error Overrun error
timer cannot generate output these bits considered nonfunctional ACE9050.
Table TCSR descriptions FRC: Free Running Counter 16-bit ReadWrite counter; Data read from written register extra hardware load save both bytes counter simultaneously when double byte store instruction used. counter incremented processor clock. Reading from counter does affect ICR: Input Capture Register a16-bit Read register which holds value Free Running Counter when transition detected ICN, i.e. Counter Output.
NOTE: Bits cleared reading Status register, followed reading Received Data register
Table
RMCR Transfer Rate/Mode Control Register mode select register controls clock source setup. This write-only register. processor internally divided down processor clock give Baud clock. Baud rate division ratio value from 4096. However, this could lead non-standard Baud rates ACE9050 provides separate Baud rate generator.The functions this register described Table
ACE9050
Bits Value
Advance Information
Description mode fully supported ACE9050 6303. This mode entered execution instruction. Escape interrupt reset
XXXX
used Clock Control mode disabled processor Baud rate used 9050 Baud rate generator Speed Select (Bits E416 E4128 E41024 E44096
Address, Data Memory Control
Address, Data control lines from ACE9050 6303 connect kernel which interfaces chip structures. Interface block provides suitable buffering drive required buses externally, configure Emulation mode.
Interrupt Processing
interrupt processing ACE9050 6303 essentially same generic 6303, exception being NMI, which available. IRQN internally connected interrupt, External Interrupt Internal interrupt blocks. These blocks combine possible sources interrupts into line which connected IRQN. This also connected Emulation mode. IRQN maskable. interrupt mask Condition Code Register must zero respond Interrupt request, with generic 6303. Interrupt Vector Memory shown Table Vector FFFE FFEE FFFA FFF8 FFF6 FFF4 FFF2 FFF0 FFFF FFEF FFFB FFF9 FFF7 FFF5 FFF3 FFF1
Table RMCR Transfer Rate/Mode Control register Bits [7:0] (Data) Description RDR: Received Data Register Read received bits. First received placed last TDR: Transmit Data Register Write register store bits before serial transfer from Transmit shift register, first
[7:0] (Data)
Priority
Interrupt TRAP Software Interrupt (SWI) IRQN (Timer Input Capture) (Timer Compare) (Timer Overflow) (UART)
Table Receive Transmit Data registers Normal Mode should initialised before operation. This means writing mode select control/status register. Service Mode configured 9600 baud, receive interrupt enabled. When transmitter first initialised will send ten-bit preamble `1's before being ready transmit data. Once initialisation complete data transmission enabled writing transmit data register. TDRE start transmitted (0). Next eight data starting bit0 transmitted followed single stop (1). hardware sets TDRE TRCSR register. does transfer another word output goes high. receiver configured during initialisation. enabled start detected (0), next nine bits will sampled approximately centre each bit. ninth data transferred Receive data register. RDFR TRCSR register. ninth receive data register full then ORFE indicate error. read TRCSR register followed read Received data register (RDR) will clear these flags. Control Register (RAMCR) This register read only ACE9050. (RAME) zero: this because ACE9050 external 6303 block. (STBY) also zero ACE9050 because Standby mode supported.
Table Interrupt vector memory
Error Processing
interrupt generated when undefined op-code fetched, when instruction fetched from impossible address. This range 0000- 007F ACE9050 (0000001F standard 6303).
INTERNAL BOOT BLOCK
code provides boot block ACE9050. Following reset condition code execution will always start internal ROM. internal data flow depends condition SERV Input thus mode operation ACE9050. operation flow IROM shown Fig. described following sections:
Normal Mode
Read serial data ACEBus DTFG line Configure ACE9030 Reference dividers ACEBus. program counter beginning external (1800H).
Operating Modes
Generic 6303R modes: Multiplexed nonMultiplexed, where mode selected externally using P2[0], P2[1] P2[2]. This required ACE9050, where mode mimic multiplexed internally when reset (MRN) released ACE9050 processor fundamental modes operation: Emulation Normal, which described MODES OPERATION section. Power Consumption Modes generic 6303 Standby mode supported ACE9050 6303. STBY accessible. Sleep
Service Mode
Read serial data ACEBus DTFG line Configure ACE9030 Reference Dividers ACEBus Configure UART Wait seconds special code UART found step Normal Mode Load Data from UART into
Advance Information
Pass control Program loaded Interrupt Vectors space. program then Program FLASH memory UART. Steps 1and Both Modes Chipset offers flexibility using three different crystal frequencies: MHz. chosen crystal used generate system clocks local oscillator frequencies required cellular phone application. ACE9050 must detect what crystal being used correct value OSC8 dividers ACE9030. This handled Internal ROM. Upon Reset ACE9030 sets OSC8 Crystal, ACE9050 clocked faster than MHz. system designer must DTFG input (the Radio Serial Interface, 82), using external resistor approximately 10k. crystal frequency determines where resistor terminated, shown Table Upon reset ACE9050 Internal reads DTFG input programs ACE9030 OSC8 accordingly. Crystal Serial Data RXed 000000 Data FFFFFF FFFFFF Resistor from (Gnd) (pin
ACE9050
where: Number bytes xx1pp1dd1cc record. pppp Load address data bytes, xxxx Name proqram (ASCII coded) eeee Program entry address checksum calculated from [2552sum(pp)1sum (dd)1 (xx)1sum (ee)1nn)] When `s9' read from File Record, code will jump reset vector. This mapped 0FFE IROM. program will then begin execution reset. last characters record file (nneeeecc) will received while program running. Binary dump file This format binary representation code, proprietary binary format code. start code this format `OB' ASCII 30H, 42H) First bytes start address pointer. next bytes address pointer11. next bytes data bytes. These loaded consecutively from start address. When last data byte received program counter will loaded code start address pointer. Step7-Interrupt Vector table Internal will 6303 Interrupt vector table address space loaded program deal with interrupts shown Table general only interrupt required Flash Loading program. Vector address 0FFE 0FEE 0FFC 0FFA 0FF8 0FF6 0FF4 0FF2 0FF0 Interrupt Reset Trap Implemented Software interrupt IRQN Timer Input compare Timer Output compare Timer overflow Table Area Reserved IROM Operation IROM code itself requires small amount during operation. This area must used storage program. Reserved area: 080H 100H Fig. shows data flow internal ROM.
Table Step Normal Mode Program code external EPROM address 1800H started. Internal resides processor address space FE00H FFFFH. Obviously main program requires access this space Interrupt vectors. Internal deselected setting PORT4 zero. recommended that external program does this quickly always before enabling Interrupt sources. Step Service Mode Internal will initialise 6303 (UART) Baud rate generator 9600 Baud. initialised following: Receiver Transmitter Receive Interrupt enabled 9600 Baud rate from ACE9050 Baud Rate Generator Receive interrupt will remain enabled after IROM code execution. UART always configured 8-bit data transfer, parity stop bit. Steps Service Mode When service mode ACE9050 download program from RAM. achieve this first code (start code) must sent down within seconds releasing Reset. boot block code will write subsequent code into RAM. code formats supported: Motorola Record format Binary dump Motorola S-Record Format start code this format `OA' ASCII i.e. 30H, 41H). s0nnppppxxxxxxxxxcc First Record file s1nnppppdddddddddddddcc Data record with 16-bit address
DECODER
Decoder logic creates memory system containing ACE9050. Internally, maps ACE9050 registers, onto System Memory map. External also mapped onto available address space Decoder, situation complicated Bank Address switching circuitry. Refer Table following page details memory mapping. Note that ACE9050 contains Memory Banked Switching circuitry. Refer section `BUS INTERFACE MEMORY BANKING' below details. Decoder also creates suitably timed Output Enable Write Enable signals (refer Figs. parallel read write cycles external devices.
s9nneeeecc
file record
ACE9050
Address (hex) 0000-001F 0020-007F 0080-17FF 1800-7FFF 8000-BFFF C000-FDFF FE00-FFFF
Advance Information
Description 6303 Registers Internal ACE9050 Registers Banked external Banked external Non-Banked external Internal External Table
External Pins
Output Enable, active (pin This signal used when accessing external memory other suitable devices. Driving Output Enable input external memory reduces possibility data contention conditions. Write Enable, active (pin This output used latch data into external memory other suitable devices.
Associated Registers
IROM Port ACE9050 internal (IROM) mapped bytes address space allowing provide interrupt handler routines. Upon reset IROM select enabled. should disabled software before interrupts enabled. IROM Description Address range FE00H-FFFFH: External Internal (reset state) Table SLEEP Port this enabled then CSEPN will become inactive during periods when 6303 Sleep mode. When 6303 Sleep mode activated, processor puts FFFFH address bus. Decoder simply does activate CSEPN this address when SLEEP enabled. SLEEP Description Address FFFFH: CSEPN active CSEPN inactive Table
(UART): 9600 BAUD; BIT: PARITY. RECEIVE INTERRUPT ENABLED
RESET RELEASED
6303 RESET VECTOR FFFE
ACE9050 RESET IROM SELECTED (PORT4 [1]±1)
START IROM CODE
READ DATA FROM DTFG
ACE9030
ACE9030
ACE9030
SERV INPUT
INTERFACE MEMORY BANKING
interface logic responsible following: External Interface ACE9050 Data Address buses Creating chip selects external memory parallel devices. logic external banked addressing Emulation Mode: External control internal buses Fig. block diagram circuit. ACE9050 memory interface operate lower supply voltage than rest chip. This allows voltage memory parts. memory interface pads separate supply rail, which connected VDDM.
JUMP 1800H (START ROM)
WAIT
MAIN PROGRAM EXTERNAL RESET PORT4
INTERRUPT VECTOR TABLE
RESET TRAP 0FFE 0FEE 0FFC 0FFA 0FF8 0FF6 0FF4 0FF2 0FF0
LOAD EITHER MOTOROLA S-FORMAT BINARY FILE CODE INTO AREA FROM FILE PASS CONTROL PROGRAM
External Pins
EMUL Emulation mode (pin This input changes function external data address buses. Emulation mode (EMUL internal Address Data buses constructed from external stimuli internal 6303.
IMPLEMENTED
Figure Data flow internal
Advance Information
INTERNAL DATA [7:0] NORMAL:D[7:0] EMUL:D[7:0] A[7:0] INPUT
ACE9050
ID[7:0] (DISABLED EMULATION MODE) TRANSPARENT LATCH
LATCH ENABLE
ACE9050 6303 KERNEL
AD[15:0] (DISABLED EMULATION MODE)
[7:0] [13:8]
NORMAL:NOT USED EMUL:AS INPUT A7:0 NORMAL:A[13:8] OUTPUT EMUL:A[13:8] INPUT NORMAL:NOT USED EMUL:A[15:14] INPUT
[15:14]
[15:14]
BA[17:14] CSEPN CSE2N NORMAL:R/W USED EMUL:R/W INPUT
MEMORY BANK SWITCHING
DATA INTERNAL EPROM CHIP SELECT INTERNAL ADDRESS [15:0]
INTERNAL READ /NOT WRITE
Figure Data Address configuration Address Strobe (pin This input used Emulation Mode only. external [7:0] will contain both data lower bits address bus.The Interface provides transparent latch required hold value address during latter part cycle. provided control Latch Enable. typical system this will directly connected emulating 6303 output. Read/Not Write (pin This output Normal mode, input Emulation Mode. processor Read/Not Write line. timing this output guaranteed same standard 6303 processor. Emulation mode will directly connected Emulating 6303 line. [7:0] Data (and Address Emulation mode) (Pins 18-25) Normal mode these pins provide bidirectional data transfer between ACE9050 6303 external memory. Emulation mode they provide directional data lower bits address into ACE9050. [7:0] Lower address bits (Pins 35-30) These outputs provide lower bits address external memory. This case both Normal Emulation modes. [13:8] Address Bits (pins 46-41) Normal mode these provide output ACE9050 6303 address bits addressing external devices. Emulation mode, A[13:8] provide input external 6303 address bus, address ACE9050 functions excluding 6303. [15:14] Emulation Address bits (pins These inputs only used Emulation mode. internal 6303 address A[15:14] banked address logic external pin. emulation mode host processor must drive complete 6303 internal address A[15:14] inputs provided. host processor will then drive entire internal bank select register, external memory access will same regardless Emulation Normal mode. [17:14] Banked address (pins ACE9050 expands external address bits. This allows 256K memory space. [17:14] outputs from bank select register. operation refister described further `Memory Banked Addressing', below. CSEPN Chip Select (pin This output provides active chip select accessing external program memory. reset entire external memory address space mapped CSEPN. Banked area memory programmer select either CSEPN CSE2N access Bank Select register. CSE2N Chip Select (pin This output provides active chip select accessing external memory other suitable device. Banked area memory programmer select either CSEPN CSE2N access Bank Select register. VDDM Supply Memory Interface (pin power supply memory interface, VDDM, provides power supply following pads: [13:0], [17:14], [7:0], CSEPN, CSE2N,
Memory Banked Addressing
ACE9050 provides circuitry create banked addressing system which will increase size programming space from (64K bytes) (256K Bytes) enable Chip Select lines programmed. This achieved using internal register select required page memory chip select line. banked addressing associated circuitry mandatory system using ACE9050. When using banked addressing external addresses generated thus system memory different from 6303 memory map. banked addressing functions same manner both Normal Emulation mode with external processor.
ACE9050
Associated register
Advance Information
processor memory thus split into distinct areas: Banked address (Root) Banked address: Banked address area (Root) A[17:14]: address lines A[17:16] address lines A[15:14] identical corresponding processor address lines. This means original area processor memory mapped external memory address space. CSE2N never active, regardless value Bank_Sel register access will with CSEPN. Banked Address area: A[17:14] These address lines same Bank register bits [3:0]. programmer theory select pages. This discussed more detail System Memory section. CSE2N: BANK determines whether this Chip select line enabled CSEPN. Table summarises operation areas. Address area Non-Banked A[17:16] A[15:14] Same Micro Chip Select Always CSEPN
BANK_SEL: Bank Select register (Write only) [7:5] Name Description used Chip Select: CSE2N CSEPN Banked Address (see Table Banked Address (see Table Banked Address (see Table Banked Address (see Table Table Bank_Sel 0000 0001 0010 0011 0100 0101 0110 0111 Page Base Address (Hex) 00000 04000 08000 0C000 10000 14000 18000 1C000 Bank_Sel 1000 1001 1010 1011 1100* 1101* 1110* 1111* Table banking configured occupy byte area processor memory address space. will thus create byte pages. This configured hardware cannot altered. achieved decoding upper bits processor Address bus. address range 8000H BFFFH which corresponds A[15:14] bank select circuit invoked. bank addressing circuit only affects upper four bits external data bus. A[17:16] completely new, next A[15:14] replacements processor A[15: bits. Fig. block diagram Bank Select circuitry.
AD15 AD14 CONTROL
Page Base Address (Hex) 20000 24000 28000 2C000 30000 34000 38000 3C000
Banked
Bank Select register bits [3:0] Table
*Refer System Memory section more details
Banked Address System Memory processor system memory become different because memory banking. system memory spit into pages original processor Memory re-targeted. Refer Fig.
SYSTEM ADDRESS
0XXXX BANK BANK BANK BANK 1XXXX BANK BANK
BANK BANK 2XXXX BANK BANK
A[17:14] ID[3:0]
ADDRESS 15:0 0000 REGISTERS
BANK
BANK 3XXXX
BA[17:14] 1000
[4:0]
BANK_SEL REGISTER
A[17:14] 8000 BANKED CSEPN C000 FE00 BOOT FFFF CSE2N 256K
EPROM SELECT
PROCESSOR MEMORY
SYSTEM MEMORY
Figure Banked Addressing block diagram
Figure Memory Banked Addressing
Advance Information
page addressing access 16316K pages Chip Select line theory; however original 6303 memory must also reside 256K CSEPN memory space. This system memory ACE9050 represents Pages example, 6303 address range C000H FFFFH will access same memory location 8000 BFFFH with bank select register This useful when programming FLASH memory device, care must exercised addressing time code. four pages system designer must decide whether access area page address direct (Root) address. original 6303 pages: Page (0000H-3FFFH) Page (30000H-33FFFH) This must used ROOT ROM, code will jump 1800H after reset. This means bottom page (0000H-17FFH) cannot used unless accessed banked address. does allow maximum possible (42K) memory area configured Banked. Page (40000H-7FFFH) Page (340000H-37FFFH) This page either used Root, banked. Page (8000H-BFFFH) Page (38000H-3BFFFH) This page banked definition. Page (C000H-FFFFH) Page (30000H-3FFFFH) final page could either accessed banked address Root address, however this contains Interrupts must Root. designer also allocate these further shadowed pages CSE2N chip select. system designer whether unique pages CSE2N shadow (CSEPN) page
ACE9050
occurs during this time IRQN line will driven ACE9050. When IRQN enabled 6303 processing, first interrupt 6303 will detect IRQN line re-enter interrupt handler routine. This will continue until pending interrup have been serviced when IRQN line will remain high. more than pending interrupt occurs software prioritise response, interrupt handler written. later interrupts must cleared IRQPRT0, software until they have been serviced. ACE9050 will detect more that pending interrupt from given source, i.e. will tell that IRQ-WS have been missed, only that IRQ-WS interrupt occured.
Internal Interrupt Control Port
internal interrupt control port facilitates resetting, masking reading seven potential internal interrupt sources three registers. Table describes possible sources. Name IRQ-TX IRQ-WS IRQ-BI-SAT IRQ-RX IRQ-REC IRQ-SEND IRQ-TO Description Modem: Data Transmitted Modem: Received Word synchronisation sequence Modem: Busy Idle updated Modem: Data registers updated Serial Interface Received data Serial Interface Sent data Time (ATO expired)
Table Internal interrrupt sources Associated Registers (Table IRQPRT0: Internal Interrupt Reset Register Writing zero data this register will reset corresponding interrupt source. IRQPRT1: Internal Interrupt Mask Register write this register will determine possible source interrupts. reset interrupts masked IRQPRT2: Internal Interrupt Read register Read from this register will determine interrupts source. IRQPRT0 Name Reset Description Reset change
INTERRUPTS
ACE9050 contains internal interrupt port, external interrupt port interrupt. This expands 6303 maskable interrupt (IRQN) into eight internal external interrupts. Interrupt control logic enables masking, reading resetting potential interrupt sources. Three registers associated with each interrupt control ports, IRQPRT internal IRQPRT external interrupts. Each Interrupt control port will generate Interrupt request line, will interrupt. These three lines NORed together produce 6303 IRQN input. Fig. block diagram Interrupt Section. source masked interrupt will generated corresponding Interrupt register. masked interrupt will generated correspondincg will interrupt register. Once interrupt generated, read IRQPRT2, section. both internal external interrupts enabled processor must read both IRQPRT2 however, only external internal interrupts enabled software need only read corresponding register. reset interrupt, write IRQPRT0 required with correspondin interrupts sources prioritised ACE9050. Handling interrupt covered separately Interface description, Section
IRQPRT1 IRQPRT2 [3:0] Source Source Interrupt Interrupt Should masked Interrupt Interrupt Table Mask Reset masked Enabled
Masking Interrupts
IRQN input 6303 level sensitive maskable interrupt line. This means that possible enable disable interrupts from ACE9050 6303. This useful avoid nested interrupt situations. several interrupts unmasked ACE9050, interrupt handler routine disable interrupt when dealing with interrupt 6303. another valid interrupt
ACE9050
Advance Information
DATA
IRQPRT0 RESET
IRQPRT1 MASK
TIME IRQSEND IRQREQ IRQRX IRQBISAT IRQWS IRQTX
LATCHING LOGIC DATA
IRQPRT2 READ COMBINING LOGIC
IRQPRT4 RESET
IRQPRT5 MASK
INRQ0 INRQ1
LATCHING LOGIC
IRQPRT6 READ COMBINING LOGIC
IRQN
6303
DATA
INP1 INP1 INP1 SERV TXPOW
PORT1 INPUT
INTERRUPT
ACE9050
Figure ACE9050 Interrupt configuration
External Interrupt Control Port
external interrupt control port facilitates resetting, masking reading potential external interrupt sources three registers. external interrupt inputs edge sensitive. Table describes possible sources Name Description regardless whether interrupt generated. INRQ1 (pin rising edge (zero transition) this line will generate INRQ1 interrupt associated mask register level this input also read Port1 regardless whether interrupt generated. Associated Registers (Table 32)Bit7: IRQPRT4: External Interrupt Reset Register. write this register will reset interrupts corresponding written data field. IRQPRT5: External Interrupt Mask Register. write this register will determine possible source interrupts. After reset interrupts masked. IRQPRT6: External Interrupt Read register. Read from this register will determine interrupts source.
INRQ1 External Interrupt (INRQ [1]) INRQ0 External Interrupt (INRQ [0])
Table External pins INRQ0 (pin rising edge (zero transition) this line will generate INRQ0 interrupt associated mask register level this input also read Port1
Advance Information
Name Reset Description IRQPRT4 Reset change IRQPRT5 Masked Enabled IRQPRT6 Interrupted Interrupted Table
ACE9050
2[6] (pin 76), OUT2[7] (pin Output pins High Current inverting output pins. used backlight drivers. Their state OUT_PORT2. Upon reset OUT_PORT 2[7:6] reset low. inverting nature outputs this means 2[7] 2[6] high. Associated Registers IN_PORT1: ACE9050 Input Port: Read Only Name POWDET SERV INP1 INP1 INP1 INRQ1 INRQ0 Description Logic Level TXPOW Input Logic Level SERV Input Read back Logic Level INP1 Logic Level INP1 Logic Level INP1 Logic Level INRQ1 Logic Level INRQ0 Table
Mask
Read
EXTERNAL PORTS MULTIPLEXER
ACE9050 contains external ports, addition 6303 Port1 Port2 which described section `ACE9050 6303R Description'. ports input register (IN_PORT1), other output (OUT_PORT2). Both 8-bit, bits accessible from outside ACE9050. bits from OUT_PORT2 multiplexer. This enables multiple functions share same external pin, thus reducing overall count. functions multiplexed with port Pulse Width Modulators serial Interface Latch2. Selection made ACE9050 control Port Further capability obtained using Keypad interface standard ports. This described `Keypad Interface' section data sheet.
OUT_PORT2: ACE9050 Output Port: Read Write Name OUTP2 OUTP2 OUTP2 OUTP2 OUTP2 OUTP2 OUTP2 Description High Current Inverting O/P* High Current Inverting O/P* used used used multiplexer with PWM2 Latch2) multiplexer (with PWM1) when CPUCL disabled
External Pins
INPUTS INRQ1, INRQ0: External Port Interrupt Input (pins logic level these external inputs read PORT1[1:0], regardless whether these inputs configured generate interrupts not. INP1[4], INP1[3], INP1[2]: External Port Inputs (pins 54,53,52) Uncommitted input. logic level these pins read IN_PORT1[4:2]. SERV: Service Input (pin state mode select line SERV read software IN_PORT1. function SERV described `Modes Operation' section. TXPOW: Power Detect input (pin TXPOW input goes Watchdog block, refer `Autonomous Timeout' section more details. state input read IN_PORT1. OUTPUTS OUTP2 [0]/CPUCL OUT_PORT2[0] CPUCL Clock (pin When CPUCL Clock Output disabled Clock Generator this driven OUT_PORT2 [0]. Refer `Clock Generator' section details CPUCL function. OUTP2 [1]/PWM1 (pin This either driven from OUT_PORT2[1] Pulse Width Modulator selection made Port5[0]. OUTP2 [2]/PWM2/Latch2 (pin This driven from: OUT_PORT 2[2], Pulse Width Modulator Serial Interface Latch2. selection made Port 5[5:4].
reset, these bits corresponding output pins
driven high.
Table
PORT5 [5:4]: OUTP2.2_SEL OUTP2 [2]/PWM2/LATCH2 function OUT_PORT2 (Reset state) Pulse width modulator Serial Interface Latch valid Table
PORT5 [0]: OUT2 [1]/PWM1 function Pulse width modulator OUT_PORT2 (Reset state) Table
ACE9050
Advance Information
Associated Registers Description TURBO: Port (Reset state) (Turbo) ENSIS: Port CPUCL pin: OUT2 (Reset state) CPUCL pin: CLKENAB: Port C1008 C1008 (Reset state) XOSC Port Oscillator active (Reset state) Oscillator power down Table
CLOCK GENERATOR
AC9050 provides clock generator with crystal oscillator circuit. This circuit generates chip clock frequencies which logic synchronised. Normal mode clocks generated from external source. Emulation mode Master clock ECLK which becomes input. TACS mobile handset applications input frequency must Emulation Mode input frequency Turbo mode, required ECLK pin. Note that, although ACE9050 will operate with lower frequencies, radio functions such Modem would then function correctly radio system. clock generator built-in oscillator which requires external crystal. Alternatively, oscillator powered down either 800mv peak-to-peak AC-coupled sinewave CMOS logic level applied used. ACE9030 being used this provides suitable output CLK8; coupling must used. main internal clock derived from clock, ECLK. This either Turbo mode. Turbo mode ECLK divided generate main clock. This gives correct functionality when Emulation mode, where ECLK frequency generated externally. clock generator produces clock with internal clock frequencies required ACE9050. Various frequencies also available externally external crystal used with Crystal Oscillator, Fig. shows external components required. Careful layout rules should applied external Crystal Circuit design. These include mounting components close possible ACE9050 avoiding running signal lines close oscillator circuit.
BAUD RATE GENERATOR
Baud Rate Generator provides standard baud rate clocks 6303 block. internally connected 6303 Port2 Emulation mode Baud Rate generator clock output available drive shadow 6303. Baud rate clock output times baud rate. This requirement standard 6303. Baud rates available shown Table higher baud rates 6303 transfer rate selected TRCSR register. these referenced ECLK they will non-standard rates.
External Pins
XOUT
470k 22pF typical (Refer Characteristics)
BAUDCLK: Baud rate clock output. (pin This output 83the baud rate. used emulation mode only shadow 6303. Associated Registers BRG: Baud rate Select port Write only Bits Description
Figure External crystal components
XXXX
Unused
External Pins
CPUCL Output (pin This output buffered crystal clock input frequency. After reset disabled, enabled software. Refer Associated Registers. C1008 Output (pln This output main clock divided eight. must always mobile phone application using chipset. intended drive Serial interface clock. enabled after reset, disabled software. Baud (Reset state) 1200 Baud 2400 Baud 4800 Baud 9600 Baud Table
EXTERNAL RESET WATCHDOG FUNCTION
ACE9050 contains Master reset circuit. Upon reset being applied, circuits reset registers into known state. These detailed Tables ACE9050 6303 registers respectively. mode selection 6303 also occurs automatically upon Master reset. external output (EXRESN) also asynchronously driven low. Master reset circuit activated means: external (Master Reset) being driven low. Watchdog Time out. Watchdog circuit provides automatic means reset processor gets stuck infinite loop, which would
ECLK Processor Clock (pin
This processor clock. output Normal mode, input Emulation. frequency 6MHz Turbo mode.
Crystal External source (pin
Input Crystal external source input. External source must AC-coupled CMOS levels.
XOUT Crystal Output (pin
external crystal used connect between XOUT. external source used this output should left unconnected.
Advance Information
caused software code entering illegal state. This could incorrect sequence being entered user glitch either data address causing wrong instruction executed. Watchdog 4-second counter which always counting when overflows system reset generated. This will reset ACE9050 drive external reset 100ms. will reset POFFN, phone will turn off. Refer `Autonomous Time (ATO)' section more details. prevent system reset Watchdog counter must cleared. This will prevent system reset seconds. following actions clear Watchdog counter: service mode counter permanently cleared, preventing system reset. clears Watchdog counter. counter thus starts when goes high. processor making write access Watchdog register. Thus normal operation software code must sure access Watchdog register once every seconds prevent reset.
ACE9050
External Pins
Master Reset (pin This active input completely resets ACE9050 Inte~rated circuit. prevents Watchdog timer from counting. ACE9050 will reset duration pulse plus additional 100ms. clock must running device reset correctly. EXRESN External Reset (pin This active output provided external reset function. active minimum 100ms case Watchdog reset. case reset EXRESN will duration being plus additional 100ms, shown Fig.
EXRESN
100ms
Figure EXRESN reset Associated Registers REWD write access this address will clear watchdog 4second counter.
INTERFACE General
ACE9050 provides interface between microprocessor. Details specification found Philips Components Technical Handbook. allows integrated circuits communicate directly with each other bidirectional 2-wire bus. Interfacing
devices system very simple because they connect directly lines: serial data line (SDA) serial clock line (SCL). prototype system final product version easily modified `clippinq' `unclipping' from bus. reliable, multi-Master with integrated addressing data transfer protocols. multi-Master capability very important, although many designs require Both lines connected positive supply pull-up resistor, remain high when busy. Each device recognised unique address, operate either transmitter receiver, depending upon function device. When data transfer takes place bus, device either Master Slave. device which initiates transfer, generates clock signals this transfer, Master. that time, device addressed considered Slave. important note that Master could either transmitter receiver; Master microcontroller send data EEPROM acting transmitter, then interrogate EEPROM contents acting receiver, both cases performing Master initiating transfer. same manner, Slave could both receiver transmitter. data transferred during each clock pulse. data line must remain stable during high period clock pulse order valid. Changes data line this time will interpreted control signals. high transition with high indicates Start condition, high transition whilst high defines Stop condition. considered busy after Start condition free certain time interval after Stop condition. These conditions always generated Master. Each byte transmitted serially with first. byte bits long followed acknowledge bit. clock pulse related acknowledge generated Master. device acknowledging must pull down line during this clock pulse, whilst transmitting device releases line (pulled high) during this pulse. Slave receiver must generate acknowledge after reception each byte. receiving device cannot receive data byte immediately, force transmitter wait holding line low. Each device unique address. address microcontoller fully programmable whereas peripheral devices usually have fixed programmable portions. Before data transmitted bus, Master transmits address Slave accessed. Slave should acknowledge Master's addressing. addressing done first byte transmitted Master after start condition. address network seven bits long, appearing most significant bits address byte. last direction (R/W) bit, with indicating that Master transmitting (WRITE) indicates that Master requesting data (READ). When address sent, each device system compares address with own. there match device will consider itself addressed send acknowledge. addition above `standard' addressing, protocol allows `general call' addressing interfacing CBUS devices. Fig. shows complete data transfer, comprised address byte indicating WRITE data bytes. also indicates Start Stop conditions
ACE9050
Advance Information
DATA DATA STOP CONDITION
ADDRESS START CONDITION
ENAB IFLG Table
Figure Data transfer
ACE9050
ACE9050 operate four modes: Master Transmit Master Receive Slave Transmit Slave Receive ACE9050 operate multi-Master systems (where there more than Master bus). ACE9050 will perform arbitration clock synchronisation. mobile handset where used interface serial PROM and/ display would sufficient have ACE9050 sole Master. interface consists (clock) (data) lines. These multiplexed with 6303 bidirectional Port1 pins reduce overall count. Selection made ACE9050 Port5. internal 6303 microprocessor interface consists five 8bit memory mapped registers processor interrupt line. interrupt connected 6303 IRQN interrupt, ACE9050 internal external Interrupt ports. Position Description Interrupt Enable Enable Master Mode Start Master Mode Stop Interrupt Flag Assert Acknowledge Read back only: Read back only:
ENAB Enable When ENAB ACE9050 will respond calls Slave address (SLA6-0) general call address I2C_ADDR register set. Start Master Mode When ACE9050 enters Master mode will send START condition when free. when already Master mode more bytes have been transmitted then repeated START condition will sent. when ACE9050 being accessed Slave mode then ACE9050 will complete data transfer Slave mode then enter Master mode when been released. After START condition been sent this will automatically cleared. Stop Master Mode When Master mode then STOP condition transmitted bus. Slave mode then ACE9050 will behave STOP condition been received, STOP condition will transmitted bus. both bits ACE9050 will first transmit STOP condition Master mode) then transmit START condition. automatically cleared: writing zero this effect. IFLG Interrupt Flag This gets interrupt condition occurs I2C; however interrupt will only generated Interrupt Enable (IEN) set. interrupt condition defined possible ACE9050 states being entered. only state that does IFLG state F8H. Refer STAT register more information states. When IFLG high then period clock line, SCL, stretched data transfer suspended. When IFLG reset zero interrupt reset clock line released.
External Pins
SCL/6303 Port (pin Bi-directional pin, used clock when selected. This requires external pull resistor when used SCL. value pull resistor depends system implementation. Refer specification. typical system resistor value would fall between 20k. SDA/6303 Port (pin Bidirectional pin, used data when selected. This requires external pull resistor when used SDA. value resistor should same line. Associated Registers SEL_I2C Port Name Description
SEL_I2C Reset, selected operational, selected Table
I2C_CNTR Control Register Read/Write This register used control ACE9050 I2C. program write read from register. hardware also change status bits this register (see Table 40). Note that this register cleared when reset. Interrupt Enable When interrupt will occur when IFLG set. This will cause interrupt 6303 IRQ. When cleared zero interrupt will disabled.
Advance Information
Assert Acknowledge. This used determine whether Acknowledge sent when Receives data. also indicates last byte transmit when Slave Transmit mode. one: acknowledge (low level SDA) will sent during acknowledge clock pulse when: Slave address been received. general call address been received ADDR registers one. data byte been received Master Slave mode. cleared zero: When data byte received Acknowledge (high level SDA) will sent, both Master Slave modes. Slave Transmitter mode then byte I2C_DATA register assumed `last byte'. After this byte been transmitted will enter state then return idle state. I2C_STAT Status Register Read This read only register contains 5-bit status code, shown Table Code (Hex) Name
ACE9050
Description
[7:3] STATUS State code [2:0] Read back zero Table There possible status codes. When I2C_STAT contains status code relevant status information available IFLG I2C_CNTR register set. other status codes correspond defined state ACE9050 When each these states entered corresponding status code appears this register IFLG I2C_CNTR register set. When IFLG cleared status code returns possible status codes shown Table illegal condition occurs then error state entered, status code recover from this state I2C_CNTR register must IFLG cleared. will then return idle state, STOP condition will transmitted bus. Status
error START condition transmitted Repeat START condition transmitted Address write transmitted, received Address write transmitted, received Data byte transmitted master mode, received Data byte transmitted master mode, received Arbitration lost address data byte Address read transmitted, received Address read transmitted, transmitted Data byte received master mode, transmitted Data byte received master mode, transmitted Slave address write received, transmitted Arbitration lost address master, slave address write received, transmitted General call address received, transmitted Arbitration lost address master, General call address received, transmitted Data byte received after slave address received, transmitted Data byte received after slave address received, transmitted Data byte received after General Call received, transmitted Data byte received after General Call received, transmitted STOP repeat START condition received slave mode Slave address read received, transmitted Arbitration lost address master, slave address read received, transmitted Data byte transmitted slave mode, received Data byte transmitted slave mode, received Last byte transmitted slave mode, received relevant status information, IFLG Table Possible values I2C_STAT Register
ACE9050
Advance Information
transmit mode byte sent first, receive mode first received will register. After each byte transmitted this register will contain byte that actually present bus. Therefore case lost arbitration this register will contain received byte. Clock Synchronisation another device drives clock line when ACE9050 master mode ACE9050 will synchronise clock clock. high period clock will determined device that generates shortest high clock period. period clock will determined device that generates longest clock period. slave stretch period clock slow down Master. period also stretched handshaking purposes. This done after each transfer each byte transfer. ACE9050 will stretch clock after each byte transfer until IFLG I2C_CNTR register cleared. Arbitration master mode ACE9050 will check that each transmitted logic appears logic another device overrules pulls line arbitration lost. arbitration lost during transmission data byte acknowledged received ACE9050 will return idle state. arbitration lost during transmission address ACE9050 will switch slave mode that recognise slave address general call address. Internal Clock Speeds defined clock speeds 100k bits/ clock speed generated ACE9050 master mode determined I2C_CCR register. signals within ACE9050 synchronised internal main clock (MCLK). frequency this clock given fMCLK Where: fMCLK MCLK (main clock) clock frequency, fCLK value stored I2C_CCR D[6: ACE9050 used systems where there other masters then frequency MCLK should less than prevent ACE9050 from missing START condition sent another master. fCLK (m11)
I2C_CCR Clock Control Register: Write This register write only, seven LSBs control clock frequency when master mode. register cleared when reset. Position Table frequency clock given fSCL Where: fSCL clock frequency, fCLK MHz, value stored D[6: value stored D[2:0] I2C_ADDR Slave Address: Read/Write This register sets slave address ACE9050 I2C. This only valid when Slave mode, allowing system designer select required Slave address prevent contentions. register cleared when ACE9050 reset. Position SLA6 SLA5 SLA4 SLA3 SLA2 SLA1 SLA0 Description Slave address Slave address Slave address Slave address Slave address Slave address Slave address General Call address enable fCLK 103(m11)32n
Table SLA6 SLA0 sets 7-bit address. SLA6 corresponds first received from after start condition. When ACE9050 receives this address after START condition will enter Slave mode. then will also recogonise General Call Address.(00H). I2C_DATA Data Register: Read/Write This register contains data byte transmitted data byte which just been received. Bits [7:0] Read [7:0] Write Name RXData TXData Description Data received Data transmit
Modes Operation
following section details operation ACE9050 four possible modes transfer, namely: Master Transmit, Master Receive, Slave Transmit Slave Receive. Master Transmit master transmit mode ACE9050 will transmit number bytes slave receiver. Before master transmit mode entered I2C_CNTR register should initialised shown Table where either
Table
Advance Information
Position ENAB IFLG Table Transmit Start Condition. master transmit mode entered settinq one. ACE9050 will then test will transmit START condition when free. When START condition been transmitted IFLG will status code STAT register will 08H. State
ACE9050
repeated START condition been transmitted then status code will instead 08H. Transmit Slave Address Write I2C_DATA register should loaded, with address slave written bits[7:1] bit[0] cleared zero specify Write. IFLG should cleared zero before transfer continue. When slave address write have been transmitted acknowledqe received IFLG will again. number status codes possible STAT register, shown Tables Transmit Data code been detected STAT, next byte placed I2C_DATA register first data byte, word address case some memory devices. IFLG then cleared. After each additional data byte been transmitted IFLG will three status codes will START register, shown Tables
Code
ACE9050 state Addr Write transmitted, received
Micro response WriteDATA, clear IFLG STA, clear IFLG STP, clear IFLG STP, clear IFLG
Next action Transmit data byte,receive Transmit repeated START Transmit STOP Transmit STOP then START code
Addr Write transmitted, received
code
Table Possible status codes after Slave address been transmitted with ACE9050 only Master ACE9050 state Arbitration lost Arbitration lost, Slave Addr Write received: transmitted Arbitration lost, GCA, transmitted Arbitration lost, Slave Addr Read received: transmitted Next action Return idle. Transmit START when free. Receive data byte, transmit Receive data byte, transmit code
Code
Micro response Clear IFLG STA, clear IFLG Clear IFLG: Clear IFLG: code
Write byte DATA, clear IFLG, Transmit last byte, receive Write byte DATA, clear IFLG, Transmit data byte, receive
Table Possible status codes after Slave address been transmitted with Multiple Masters Code ACE9050 state Data byte transmitted, received Micro response Next action
Write byte DATA, clear IFLG Transmit data byte,receive STA, clear IFLG STP, clear IFLG STP, clear IFLG Transmit repeated START Transmit STOP Transmit START then STOP code
Data byte transmitted, received
code
Table Possible status codes after Data been transmitted with ACE9050 only Master Code ACE9050 state Arbitration lost Micro response Clear IFLG STA, clear IFLG Next action Return idle Transmit START when free
Table Possible extra status codes after Data been transmitted with multiple Masters
ACE9050
Advance Information
IFLG will status code will I2C_STAT register. repeated START condition been transmitted then status code will instead Transmit Slave address Read I2C_DATA register should loaded with address Slave bits[7:1] bit[0] specify read. IFLG should cleared before transfer continue. When Slave address read have been transmitted acknowledge received, IFLG will again. number status codes possible STAT register; these shown Tables Receive Data code been detected assumed that Slave detected address when IFLG cleared ACE9050 will begin clock valid data line. After each data byte been received IFLG will set, require clearing. three status codes I2C_STAT register, shown Tables
Transmit Stop When bytes have been transmitted should set. ACE9050 will then transmit STOP condition, clear return idle state. Slave receiver cannot receive more data must indicate this Master generating Acknowledged condition. Master Receive Master receive mode ACE9050 will receive number bytes from Slave transmitter. sequence dissimilar that Transmit. some memory devices `dummy write' required transmit word address before read operation. Before master receiver mode entered I2C_CNTR register should initialised enterinq master transmit mode. Transmit Start Condition master receive mode entered setting one. ACE9050 will then test will transmit START condition when free. After START condition been transmitted
Code
ACE9050 state Addr Read transmitted, received Addr Write transmitted, received
Micro response Clear IFLG, Clear IFLG, STA, clear IFLG STP, clear IFLG
Next action Receive Data byte, transmit Receive Data byte, transmit Transmit repeated START Transmit STOP
STP, clear IFLG Transmit STOP then START Table Possible status codes after Slave address been transmitted with ACE9050 only Master
Code
ACE9050 state Master transmit
Micro response Master transmit
Next action Master transmit
Table Possible extra status codes after Slave address been transmitted with multiple Masters ACE9050 state Data byte received, transmitted Next action ReceiveData byte, transmit Receive Data byte, transmit Transmit repeated START Transmit STOP Transmit STOP then START
Code
Micro response Read Data, clear IFLG, Read Data, clear IFLG,
Data byte received, transmitted Read Data, STA, clear IFLG Read Data, STP, clear IFLG Read Data, STP, clear IFLG
Table Possible status codes after Data been received multi-Master system Code ACE9050 state Arbitration lost Micro response Master transmit Next action Master transmit
Table Possible status codes after Data been received multi-Master system
Advance Information
Transmit Stop When Master finished receiving data must signal data Slave transmitter generating acknowledge last byte that clocked Slave. Slave transmitter must release data line allow Master generate STOP condition. When bytes have been received I2C_STAT register should return 58H. microcontroller then free bit. ACE9050 I2Cwill transmit STOP condition, clear return idle state. Slave Transmit Slave transmit mode number bytes transmitted Master receiver. Slave transmitter control line must ensure bits correctly acknowledged. Before Slave transmit mode entered CNTR register should initialised shown Table where either Position ENAB IFLG Table Entering Stave Transmit Mode ACE9050 will enter Slave transmit mode when receives Slave address (SLA6-0) read (bit after START condition. ACE9050 will then transmit acknowledge IFLG I2C_CNTR register status code (Slave address read received, transmitted) will I2C_STAT register. Slave transmit mode also entered directly from Master mode arbitration lost Master mode during address byte, Slave address read were received. status code I2C_STAT register will then B0H. Sending Data data byte transmitted should then loaded into I2C_DATA register IFLG cleared. When ACE9050 transmitted byte received acknowledge IFLG will STAT register will contain B8H. Completing Transfer Slave Termination When last byte transmitted loaded into DATA register should cleared when, immediately before IFLG cleared. After that last been transmitted IFLG will usual STAT should contain C8H. When this IFLG flag cleared ACE9050 will then return idle state. must before Slave mode entered again. Master Termination acknowledge received after transmitting byte: line released allow Master generate, Stop condition IFLG will STAT register will contain C0H. When IFLG cleared ACE9050 will return idle state. STOP condition detected after acknowledge then ACE9050 will return idle state. State
ACE9050
Slave Receive Slave receive mode number data bytes received from Master transmitter. Before Slave receive mode entered CNTR register should initialised Slave transmit mode. Entering Slave Receive Mode ACE9050 will enter Slave receive mode when receives Slave address (SLA6-0) write (bit after START condition. ACE9050 will then transmit acknowledge IFLG I2C_CNTR register status code (Slave address1write received, Transmitted) will STAT register. ACE9050 will also enter Slave receive mode when receives general call address ADDR register set). status code will then 70H. Slave receive mode also entered directly from Master mode arbitration lost Master mode during address byte, Slave address write general call address were received. (For general call condition I2C_ADDR register must one) status code I2C_STAT register will then Slave address received general call address received. IFLG must cleared zero allow data transfer continue. Receiving Data I2C_CNTR register then after each byte received acknowledge (low level SDA) transmitted IFLG set, I2C_STAT register will contain status code Slave receive mode entered with general call address). received data byte read from I2C_DATA register IFLG must cleared allow transfer continue. Competing Transfer When STOP condition repeated START condition detected after acknowledge bit, then IFLG I2C_STAT register will contain status code A0H. cleared during transfer then ACE9050 will transmit acknowledge (high level SDA) after next byte received, IFLG bit. I2C_STAT register will contain status code slave receive mode entered with general call address). When IFLG been cleared ACE9050 will return idle state.
RADIO FUNCTIONS
ACE9050 provides following Radio Functions, which will typically required mobile phone implementation, which controlled internal configuration registers: Modem management, Serial Interface, counter, pulse width modulators, interface Tone generator. These functions described following sections
INTERNAL CONFIGURATION REGISTERS
ACE9050 contains internal configuration registers. These allow hardware configured software write instructions. function bits described relevant section more detail. This section provides overview internal configuration registers.
ACE9050
PORT3 Read/Write Name ENMOD ONRAD
Advance Information
PORT5 Read/Write (continued) Block Logic state action* Modem fully enabled Latch pulse generated* Latch counter reset* Enable counter POFFN POFFN Active* Sleep OUT2 [0]* Clock action* CSEPN lnactive address FFFFH period count* 2432 period count Name SEL_I2C Block Logic state Reset* Enabled, selected C1008 C1008 Enabled* OUT_PORT2 [1]*
Associated Registers
Modem serial interface counter Watchdog
CLKENAB
Clock
PWM1MUX Output
STIFC UPOFFN
*Reset state Normal mode
Table (continued)
MDMSLP Modem ENSIS SLEEP Clock Decoder
AMPS/TACS MODEM CONTROLLER General Description
Modem function supports both AMPS TACS mobile phone systems. Selection made software; external component changes necessary. Modem provides following hardware: interface Data Receiver Data Transmitter Decoder Transmitter Data Receiver contains Digital Discriminator, Data Decoder Word Sync Detector (see Fig. 20). Transmitter generates Manchester encoded data. receiver measures incoming signal. transmitter either retransmit received generate standard tones
IFFREQ
counter
*Reset state Normal mode
Table PORT4 Read/Write Name SINTSLP NOMPLL TURBO SATMUX IROM Block serial interface used used Modem (Data Clk) clock Modem (SAT Mux) Decoder used sync data* sync data TXSAT selected* RXSAT selected External Internal ROM* Logic state Active* Sleep
External Pins
AFC/RXDATA Data Input (pin Data into digital Discriminator this input pin. data composite Voice, Data modulated carrier mixed down either 54kHz kHz. signal must CMOS input levels described Characteristics section. ACE9030 provides such output AFCOUT pin. ACE9030 samples 450kHz with 504kHz clocked register produce 54kHz CMOS output. TXDATA Transmit Data Output (pin When enabled this output generates Manchester encoded Data appropriate data rate. This produces digital output which must filtered combined with other sources modulation. ACE9040 provides these functions DATI input. RXSAT Received Input (pin This input received which, must have been filtered give appropriate tone with CMOS level swings. ACE9040 provides filtering amplification provide suitable signal output. TXSAT Transmit output (pin This output provides CMOS level frequency output. source either Received SAT, totally independent tone generated locally ACE9050. This output which must filtered combined with other source modulation. ACE9040 provides these functions input.
*Reset state Normal mode
Table PORT5 Read/Write Name XOSC_PD Block used Clock Active Oscillator* Power down OUT2 [2]* Latch Logic state
[5:4] OUT2.2_SEL Output used Table
Advance Information
ACE9050
ACE9040
RXSAT
DECODER
TRANSMITTER
TXSAT
AFCIN 450kHz
DEMODULATOR
AUDIO
MICRO DATA CONTROL
DATA RECEIVER
AFC/RXDATA 54kHz 504kHz
WORD SYNC DATA DECODER DISCRIMINATOR
DATA TRANSMITTER
TXDATA
ACE9030
ACE9050
Figure AMPS/TACS Modem Controller Associated Registers Modem dedicated registers control data transfer. There also bits general registers PORT3 PORT4 which used Modem. bits described more detail relevant section. MDMSLP PORT3[3] (Table This determines whether modem active sleep mode. modem into sleep mode turning clock Modem associate circuitry. MDMSLP Active Sleep Table ENMOD PORT3[7] This used Modem. must software after reset before Modem used. should then remain SATMUX PORT4[2] (Table This used control source Transmitted signal. SATMUX Multiplexer output Locally generated RXSAT Table NOMPLL PORT4[4] (Table Data Decoder modem uses locally generated clock recover data. NOMPLL selects whether this clock forced lock extract Data clock not. Refer Data Decoder section more detail. NOMPLL Decoder clock Normal mode: Data clock locked incoming clock Free-running: Data clock unlocked Table LF1_2 SQLEV ENAMPI SYNDET ENWS VC_CCN Modem mode MODPRT0 (Table This dedicated read/write port used controlling Modem; Name MDRESN A_TN SCCTX [1:0] Function Reset Modem Modem enabled TACS Modem AMPS Modem [5:4] bits: generator transmitted output disabled output enabled Capture mode Sync mode Word sync disabled Receiver will re-synchronise Control channel Voice channel Table MODPRT1 This dedicated read/write port used controlling Modem. Write (Table Name MDMTST TXDINV RXDINV Function Must always Data inverted Data inverted Data inverted Data inverted Discriminator enabled Discriminator bypassed (Test) squelch threshold level Table
ACE9050
MODPRT1 (continued) Read (Table [5:4] SCCRX [1:0] Name
Advance Information
Interrupts
Function used Busy/idle Busy/idle Bits [5:4]: generator received Number Data bits word that have exceeded pre-set Squelch threshold Table IRQ-RX Bit3 This interrupt generated every time data (RXD [7:0]) squelch values (SQRX [3:0]) updated. This will approximately every 800µs AMPS TACS. busy/ idle bits extracted, these times will vary maximum period. IRQ-BI-SAT Bit5 This interrupt dual function, dependent whether Modem control channel voice channel. control channel interrupt occurs every time busy/ idle updated MODPORT1. This will occur nominally every AMPS system TACS. voice channel this interrupt indicates there updated value present SCCRX. This will occur every 12ms. IRQ-WS Bit6 This interrupt occurs every time 11-bit Barker code detected incoming data stream. Refer Word Sync Detector more details. IRQ-TX Bit7 This interrupt occurs every time first byte transmitted from Modem Transmitter. software must ensure that data valid prior this interrupt. When enabled will generate interrupt every 800µs AMPS TACS. Data transmission sequence discussed more detail Modem Transmitter section. modem interrupt lines which feed into Internal Interrupt Control block. interrupts read, reset individually masked this block
[3:0]
SQRX [3:0]
MODPRT2 This read/write port used data transfer Write (Table [7:0] Name [7:0] Function Data byte transmit Table Read (Table [7:0] Name [7:0] Function Received Data byte (note
NOTE 1.When VC_CCN ENWS busy/idle bits extracted from data stream present RXD.
Table
MODEM BLOCK DESCRIPTIONS
RE-SYNC
AFC/ RXDATA
DATA DECODER
C1008 MODPRT1 [4]: LF1_2 MODPRT1 [5]: RXDINV
504kHz DISCRIMINATOR ENABLE/BYPASS RXDATA INVERT/NOT INVERT
Fig. Modem discriminator
Control Block
Modem confiqured either AMPS TACS systems. Various clocks timing blocks configured depending whether data 10kHz 8kHz rate AMPS/TACS respectively. Modem also entirely reset under software control. Modem required clock associated circuitry stopped, thus reducing current consumption ACE9050. ACE9030 signal initially sampled 504kHz, which below Nyquist frequency, effectively mixing function occurs. 504kHz mixed with 450kHz gives frequency component 54kHz. Further sampling signal 504kHz ACE9050 then effect. signal then passed through delay line D-type flip-flops, clocked kHz, giving delay nominal 54kHz cycles. non-delayed delayed signals then EXORed together, which produces digital version analog equivalent demodulator: degree phase shifter mixer. ACE9030 contains similar discriminator, optimised speech content signal. ACE9030 data sheet contains full description operation such circuit.
Discriminator (Fig.
Discriminator uses digital delay technique. incominq signal first sampled 504kHz. This means input either 450kHz CMOS levels 54kHz output from ACE9030; makes difference operation discriminator.
Advance Information
Associated Register bits LF1_2 MODPRT 1[4] (Table Name LF1_2 Function Discriminator enabled Discriminator bypassed (test) Table test purposes discriminator bypassed. This achieved setting LF1_2. this case Modem requires 10kHz 8kHz Manchester encoded data, i.e. baseband data signal. RXDINV MODPRT 1[5] (Table Name RXDINV Function Data inverted Data inverted Table phase Data from Discriminator determined architecture receiver. data inverted cater both high side side architectures. Sync mode
ACE9050
digital tracking loop configured modes: Capture Sync, detailed Table Regenerated clock shift Mode TACS (125µs) (4µs) Table Capture mode regenerated clock shifted greater percentage cycle than Sync mode. This will allow regenerated clock slip over then acquire incoming clock phase faster. example, re-acquire phase AMPS system would take around with good signal levels. Sync mode regenerated clock shifted much, allowing more accurate data extraction over period. regenerated clock becomes phase this mode will course take longer re-acquire correct phase. example AMPS system, re-acquire phase would take around 10ms. clock rate circuit 504kHz, hence circuit works resolution which multiple cases. general, SYNDET should Capture mode until system design satisfied that Modem Word Sync. Then SYNDET should switched Sync mode before data reading begins. NOMPLL Nominal Port Digital Tracking loop's operation turned with NOMPLL bit, shown Table NOMPLL Mode Data Clock synchronising enabled Data Clock free-running Table NOMPLL will generally allow normal operation digital tracking loop clock synchronisation circuit. With NOMPLL regenerated clock will lock incoming data clock, will keep current phase. there short period time when data present advantageous NOMPLL bit. Digital trackinq loop will then prevented from `hunting' non-existent data clock. When data then reappears, regenerated clock should still phase data immediately decoded without need re-synchronise. This facility systems where receiver power down short periods time Standby mode, thus reducing overall current consumption phone unit. SQLEV MODPRT1 [3:0] software `squelch level' incoming data. This sets number samples that have `correct' approved. Data Decoder sets flag period squelch level been reached. Word Sync Detector then sums number approved bits that occur byte updates SQRX register same time data register. Four bits used determine squelch threshold, giving different levels. number samples AMPS TACS systems respectively. Table following page shows number samples required meet level set, percentage total number samples both AMPS TACS settings that this represents. AMPS (100µs) (10µs) (2µs)
Capture mode (12µs)
Data Decoder
Data Decoder responsible clock data extraction from discriminated baseband Manchester encoded data stream. Manchester encoded data inherently contains clock. Data Decoder extracts clock timing from incoming data stream regenerates appropriately phased clock. circuit then EXORs extracted clock with data. This yields period data phase, data phase. then samples output from EXOR 504kHz. Thus, nominally samples taken period AMPS TACS respectively. data decoder will then decide state with highest number samples. number `correct' samples over certain threshold then flag set. required threshold software referred squelch level. flag passed Word Sync Detector along with value bit. Data Decoder uses digital transition tracking loop regenerate correctly phased clock. clock degrees data extraction clock integrate-and-dump function used. This degree clock again EXORed with incoming data stream. result this into up/down counter. output counter, along with value, will determine whether phase incoming clock early late. phase clock over next period will altered pull clock appropriate direction. This process repeats every period. amount clock pulled determined SYNDET bit. Manchester encoded data transitions occur boundaries well centre bit. This especially true string There chance clock will lock these, degrees phase. word structure contains dotting sequence; this 1010. pattern which devoid incorrect transitions. hardware recognise error condition during this time automatically correct clock phase. Associated Registers SYNDET MODPRT (Table Name SYNDET Function Capture mode Sync mode Table
ACE9050
SQLEV Samples [3:0] 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111
Advance Information
AMPS samples) TACS samples) ENWS Description Data will reframe Barker code detected Data will reframe Barker code detected
NOTE: Regardless setting ENWS IRQ-WS will generated detection Barker code.
Table RXD[7:0] MODPRT2 Read (Table This register contains data from forward channel (FVC FOCC) segmented into 8-bit chunks. Name Function
RXD[7:0] Data byte received Table first received goes most significant register. Control channel Busy/Idle bits extracted. other data Control channel data voice channel will present registers. This includes dotting Barker sequences. IRQ-RX interrupt occurs when registers have been updated. SQRX[3:0] MODPRT1[3:0] Read (Table These four bits contain number bits present received byte that have surpassed Squelch threshold set. will thus contain number between This register updated same time register. SQRX [3:0] 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1111 Number bits surpassing Squelch level valid
Table Squelch level settings
Word Sync Detector
Word Sync Detector contains hardware detect Barker code, synchronise received bytes incoming data frame, extract Busy/Idle bits update SQRX registers. also generates IRQ-WS, IRQ-RX IRQ-BI-SAT interrupts. hardware four modes operation which selected software. Barker code sequence used achieving frame synchronisation incoming data word boundaries. occurs message after dotting sequence before first data word. hardware detection circuit 11-bit serial shift register with appropriate asynchronous decode logic detect Barker code (11100010010). action upon detecting word sync depends mode hardware. Word Sync Detector contains parallel register, into which incoming data, RXD, clocked. When hardware appropriate mode Busy/Idle bits removed from data sequence before being Data Receive (RXD) register. Word Sync Detector also tallies number times Squelch level flag eight-bit byte stores this SQRX register. Word Sync Detector contains byte frame counters which generate IRQ-RX interrupt when data squelch registers updated. software must ensure these registers read within suitable time frame after IRQ-WS avoid losing data. Associated Registers VC_CCN Voice/Control Channel MODPRT0 bit0 (Table This allows software control mode Word Sync Detector between Control channel Voice channel. also operates conjunction with ENWS bit; VC_CCN must reflect category current channel. VC_CCN Control channel Voice channel Table ENWS Enable Word Sync MODPRT (Table This allows software control mode Word Sync Detector between `Sync Barker' Sync Barker'. also operates conjunction with VC_CCN bit. Mode
Table Possible Squelch readings MODPRT1[6] Read (Table This extracted Busy/Idle from Control channel data stream. Note that IRQ-BI-SAT interrupt occurs when this updated. Table Modes Operation Word Sync Detector four modes operation. modes affect Busy/Idle bits handled, function IRQ-BI-SAT interrupt action Word Sync Detector upon finding Barker code incoming data stream. modes selected VC_CCN ENWS bits, shown Table Busy/Idle
Advance Information
VC_CCN ENWS Mode Control channel syncronised Description Data reframe disabled IRQ-BI-SAT Busy/Idle Busy/Idle bits extracted Data reframe enabled IRQ-BI-SAT Valid Busy/Idle bits extracted Data reframe disabled IRQ-BI-SAT update Data reframe enabled IRQ-BI-SAT update Table Control Channel When Control channel software must decide when switch between synchronised unsynchronised modes. Modem does give direct indication that synchronisation been achieved; however, IRQ-WS provides indication that Barker code been detected. system designer look IRQ-WS being generated regularly suitable time window corresponding frame time, RSSI levels squelch levels, before determining Modem synchronisation. Once software determined that Modem synchronisation ENWS must zero. Word Sync Detector will then remove Busy/Idle bits from incoming data stream re-synchronise Barker codes. software must disable ENWS before first Busy/Idle occurs after Barker Code control channel frame. time this AMPS TACS systems. software does then have re-enable ENWS unless synchronisation lost. number bits frame divisible eight Word Sync Detector circuit uses frame counters realign data subsequent frames instead Barker codes. This ensures spurious Barker codes occurring data upset synchronisation Modem. this action Barker codes will appear distorted when read registers. dotting Barker code will appear following three consecutive bytes: AAH, 12H. Once synchronisation, software must ensure that IRQ-WS still occur within time window number IRQ-WS missed, software must assume Modem become unsynchronised take appropriate action. system designer decide threshold number IRQ-WS dropped, other type software averaging Table shows typical sequence locking onto data when Control channel. Voice Channel Data continuous stream Voice channel, Control channel. data sequence also does contain Busy/Idle bits. software designer determine when valid data present voice channel. IRQ-WS interrupt timinq cannot used this purpose, data stream continuous. Also IRQ-WS interrupts will occur sporadically, even when data present, probability incoming signal beinq decoded valid Barker code. voice channel data sequence begins with long dottinq sequence. software monitor data present registers, when these reliably yield pattern assumed data sequence beinq transmitted. software should then ensure IRQ-WS occurs indicate valid data beinq received. Other system parameters such RSSI, audio level also measured software. ENWS left enabled, disabled after synchronisation. there Busy/Idle bits frame divisible eight critical hardware operation. Function
ACE9050
Control channel unsynchronised
Voice channel Voice channel
Description ENMOD MDMSLP MDMRESN LF1_2 RXDINV Setup system NOMPLL SQLEV[3:0] required A_TN Required Disable Modem Interrupts VC_CCN SYNDET ENWS Enable IRQ-WS interrupt Ensure IRQ-WS interrupts occurring correct time window. system designer determine exact criteria. When this occurs set: ENWS within SYNDET Enable IRQ-RX interrupt within 800µs. Read Squelch interrupt Ensure IRQ-WS occurs correct time window. data registers should contain AAH, frame.
Initialise
Acquire Verify
Lock
Read Data Check
Table Data sychronisation acquisition sequence
Data Transmitter
Modem transmitter considerably simpler than receiver. contains data register writing data bits time Manchester encoding circuitry. also contains timing interrupt circuitry. Data transmitted written byte time TXD[7:0]. This data then transmitted next IRQ-TX interrupt, output enabled. (most significant) transmitted first. Data Transmitter generates IRQ-TX interrupts correct rate chosen system (800µs AMPS 1000µs TACS) regardless whether transmitter enabled not. Transmitter encodes data into Manchester format before transmission. This achieved generating square wave rate EXORing generated clock with relevant bit, period. output then inverted, this required system
ACE9050
Advance Information
IRQTX
LOAD DATA
DATA
REGISTER
8-BIT SHIFT REGISTER
TXDATA TXDATIN MODPRT1 ENAMPI MODPRT0
AMPS 100µs TACS 125µs CLOCK
Figure Modem Transmitter block diagram
IRQTX IRQTX IRQTX IRQTX IRQTX IRQTX IRQTX
ENABLE INTERRUPT
WRITE DATA BYTE REGISTER
ENABLE ENAMPI (1st DATA BYTE TRANSMITTED) WRITE DATA BYTE
WRITE DATA BYTE (2nd DATA BYTE TRANSMITTED)
WRITE LAST DATA BYTE (LAST DATA BYTE TRANSMITTED)
LAST DATA BYTE TRANSMITTED
DISABLE ENAMPI
Figure Modem transmission sequence designer. block diagram shown Fig. data manipulation made encoder hardware. software must generate dotting Word sync patterns coding. Transmitter enabled contents register will transmitted IRQ-TX interrupt, regardless whether this register been updated. This enables generation tone with overhead processor, other than timing required duration. software must simply write TXD. Associated Registers (Tables MODPRT2 This read/write port used data transfer Write Name Function Data transmission sequence Table Fig. describe correct sequence transmitting Data message. Note that step (Set ENAMPI high quickly) latency between IRQ-TX setting ENAMPI will cause part first byte transmitted. This byte will always part dotting sequence, this will cause degradation data, however desirable reduce this time minimum. Step Action Enable IRQ-TX interrupt Wait IRQ-TX interrupt Write Data byte Wait IRQ-TX interrupt ENAMPI high quickly Write Data byte Wait IRQ-TX interrupt Repeat steps until last byte Write last byte Wait IRQ-TX interrupt Wait IRQ-TX interrupt Disable ENAMPI Table Modem transmission sequence Table TXDINV MODPRT True Data output Inverse Data output Table Function MANAGEMENT Management circuitry consists detector, generator multiplexer. Refer External Pins section General Description details external pins: RXSAT TXSAT Detector Detector measures frequency signal RXSAT input. When Modem configured Voice channel (VC_CCN high) measurement will occur every receiver measures duration cycles depending result determines value.
TXD[7:0] Data byte transmit (bit transmitted first) Table ENAMPI MODPRT output disabled output enabled Function
Advance Information
Further software filtering required. result measurement will reside MODPRT1 bits IRQBI-SAT interrupt masked IRQ-Bl-SAT interrupt will occur each measurement period, after MODPRT1 been updated. Associated Register SCCRX [1:0] MODPRT1 [5:4] Read SCCRX [1:0] tone (Hz) 5970 6000 6030 Limits (Hz) 5955-5984 5985-6014 6015-6045 5955 6045
ACE9050
buses used data transfer between that have appropriate interface logic; however, system using Chips following words valid ACEBus: ACE9030 Sleep Word Normal (ADC Values Read) Set-up Synth Word Synth Word Synth Word Synth Word Synth Dummy word (Low Noise Mode) ACE9040 Operating mode Initialising Mode Initialising Mode Handsfree more information refer ACE9030 ACE9040 data sheets. ACEBus consists clock, bidirectional data line latch outputs. clock data lines common, while latch outputs connected follows: Latch Control (ACE9040, LEN) Latch Radio interface section (ACE9030, LATCHB) Latch Internally connected Latch Synthesiser section (ACE9030, LATCHC) Valid data transmitted stream continuous bits. last relevant latch activated. This will latch data into target device. data line will become tristate after data transfer that data received from driver. block contains eight ACE9050 registers. Three serial data transmit, three receive control. block also contains interrupt generating circuitry. SynthBus contains data line Synthdata, clock line Synthclk associated Latch2, which multiplexed with OUT2[2] PWM2. clock Serial Interface block disabled reduce overall power consumption ACE9050. Turning this clock will disable Serial Interface will turn C1008 clock.
Table Transmitter ACE9050 on-chip generator which generate 6kHz, signals. selection made bits SCCTX [1:0] MODPRT0. Alternatively received looped around re-transmitted. ACE9050 provides multiplexer either source selected under software control SATMUX PORT4. generator circuit consists series preset counters running from system clock. ACE9050 makes allowance varying phase regenerated tone this requirement current AMPS TACS protocols. When Received looped around ACE9050 only buffers incoming signal RXSAT before feeding TXSAT output pin. Associated Registers SCCTX[1:01 MODPRT0 [5:4] Write SCCTX [1:0] Generated tone (Hz) 5970 6000 6030 generated Table SATMUX PORT 4[2] SATMUX source Internally generated Table
External Pins
C1008 (pin Refer Clock Generator Section. This clock used data transfer. ACE9030 ACE9040 also used clocking other functions care must exercised turning this clock off. DTFG (pin Bidirectional data line. ACE9050 clocks data loaded into registers. Data clocked ACE9050 falling edge C1008. LATCH (pin Latch pulse used target data transfer. system using chip Latch0 connected input ACE9040. latch nominally 500ns pulse. LATCH (pin Latch pulse used target data transfer. system using chip Latch1 connected ACE9030 Radio Interface (LATCHB). latch nominally 500ns pulse. LATCH (pin Latch pulse used target data transfer optimise performance synthesiser. system using chip
SERIAL INTERFACE BLOCK General Description
Serial Interface contains serial interfaces: ACEBus SynthBus. ACEBus used distribute data from chipset. SynthBus redundant when using chipset. ACE9050 contains Master Transmitter/Receiver unit ACEBus. ACE9040 ACE9030 contain slave units. used programming devices into required state. This will required when phone powered during phone operation. ACE9030 also transmit ADCs values ACE9050 ACEBus.
ACE9050
Advance Information
LSICOM (continued) Name used used Latch Latch Function Must Must Latch enabled data transfer Latch enabled data transfer Table (continued) Name Function data transfer Begin data transfer Must
Latch3 connected LATCHC input ACE9030 Synthesiser. lenqth latch varied latch permanently high. Latch used with SynthBus, fixed 500ns. SYNTHCL (pin SynthBus clock line nominally 126kHz. This continuous clock. only activated when data transfer required. SYNTHDAT (pin SynthBus Data line. Contains valid data from ACE9050, zero.
Transmitter Section
transmitter consists five write registers, interrupt latch generating logic, clock divider timer, three shift registers connected series. These form 24-bit message that sent DTFG. most significant LSICOM transmitted first (refer Fig. Associated Registers Write Register LSICOM LSICOM LSICOM SINTSLEEP Port Name Function Bits Description First byte transmit Second byte transmit Third byte transmit Table
used Must used Must Latch Latch Latch enabled data transfer Latch enabled data transfer
used Must used Must Table Valid fields SynthBus
SINTSLEEP Serial Interface enabled Serial Interface powered down
Table STR_WIDTH Write pulse width Latch programmable between with increments. This register only works with ACEBus, Synthbus. Bits Description Pulse duration increments C1008 periods. This register decremented when pulse generated. Writing value this register terminates pulse. Table LSICOM Write This register control register. This used define mode data transfer, select which latch activate also used initiate transfer. Name Function data transfer Begin data transfer Must Answer request Answer request
Sending Data begin transmitting sequence appropriate word written LSICOM Latch required ACEBus non-zero value must written STR_WIDTH prior writing control word LSICOM When LSICOM 3[7] (GO) set, clock serial shift registers enabled. Data from LSICOM clocked falling edge C1008. After data bits have been clocked out, appropriate latch generated next fallinq edge C1008. same time latch IRQ-SEND interrupt generated internally. This interrupt control block where masked. LSICOM will then reset, ready next data transfer.
Receiver Section
receiver consists three serial registers which read LSICOM also contains counter, clocking interrupt generating circuitry. Associated Registers Read Register LSICOM LSICOM LSICOM Bits Description First byte received (ACE9030 preamble) Second byte received (ACE9030 result Third byte received (ACE9030 result Table Receiving Data order receive, LSICOM 3[5] (ANS) must set. After transmission sequence, data DTFG line clocked into receiver falling edge C1008. This process begins fifth negative clock edge after latch pulse, allow response time from slave (Fig. After clock cycles complete word will have been clocked into ACE9050. data shift registers latched into three read registers. same time IRQREC interrupt generated. IRQ-SEND interrupt generated receive sequence with relevant latch same transmit only sequence.
used Must Table Valid fields ACEBus data transfer
Advance Inf
Other recent searches
TES1V - TES1V TES1V Datasheet
S29GL-P - S29GL-P S29GL-P Datasheet
S29GL01GP - S29GL01GP S29GL01GP Datasheet
S29GL512P - S29GL512P S29GL512P Datasheet
S29GL256P - S29GL256P S29GL256P Datasheet
S29GL128P - S29GL128P S29GL128P Datasheet
DS31400 - DS31400 DS31400 Datasheet
DS1865 - DS1865 DS1865 Datasheet
2SC3123 - 2SC3123 2SC3123 Datasheet
1N5802CB - 1N5802CB 1N5802CB Datasheet
1N5804CB - 1N5804CB 1N5804CB Datasheet
1N5806CB - 1N5806CB 1N5806CB Datasheet
1N5807CB - 1N5807CB 1N5807CB Datasheet
1N5809CB - 1N5809CB 1N5809CB Datasheet
1N5811CB - 1N5811CB 1N5811CB Datasheet
1N5802CBUS - 1N5802CBUS 1N5802CBUS Datasheet
1N5804CBUS - 1N5804CBUS 1N5804CBUS Datasheet
1N5806CBUS - 1N5806CBUS 1N5806CBUS Datasheet
1N5807CBUS - 1N5807CBUS 1N5807CBUS Datasheet
1N5809CBUS - 1N5809CBUS 1N5809CBUS Datasheet
1N5811CBUS - 1N5811CBUS 1N5811CBUS Datasheet
1N5802US - 1N5802US 1N5802US Datasheet
1N5804US - 1N5804US 1N5804US Datasheet
1N5806US - 1N5806US 1N5806US Datasheet
1N5807US - 1N5807US 1N5807US Datasheet
1N5809US - 1N5809US 1N5809US Datasheet
1N5811US - 1N5811US 1N5811US Datasheet
Privacy Policy | Disclaimer
© 2012 Datasheet Archive
