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MICROCONTROLLER USER'S MANUAL
UM001600-Z8X0599
©1999 ZiLOG, Inc. rights reserved. Information this publication concerning devices, applications, technology described intended suggest possible uses superseded. ZiLOG, INC. DOES ASSUME LIABILITY PROVIDE REPRESENTATION ACCURACY INFORMATION, DEVICES, TECHNOLOGY DESCRIBED THIS DOCUMENT. ZiLOG ALSO DOES ASSUME LIABILITY INTELLECTUAL PROPERTY INFRINGEMENT RELATED MANNER INFORMATION, DEVICES, TECHNOLOGY DESCRIBED HEREIN OTHERWISE. Except with express written approval ZiLOG, information, devices, technology critical components life support systems authorized. licenses conveyed, implicitly otherwise, this document under intellectual property rights. UM001600-Z8X0599
USER'S MANUAL
TABLE CONTENTS
Chapter Title Subsections Page
Chapter Product Overview
Family Overview Product Line Features Product Development Support
Chapter Address Space
Introduction Standard Register File .2-1 General-Purpose Registers Protect Working Register Groups Error Conditions Expanded Register File Control Peripheral Registers Standard Registers Expanded Registers Program Memory 2-10 External Memory 2-11 External Data Memory 2-11 STACKS 2-12
Chapter Clock
Clock Frequency Control Clock Control SCLK/TCLK Divide-By-16 Select (D0) External Clock Divide-By-Two (D1) Oscillator Control
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Microcontrollers Table Contents Chapter Title Subsections
ZiLOG Page
Chapter Clock (Continued)
Oscillator Operation Layout Indications Unreliable Design Circuit Board Design Rules Crystals Resonators Oscillator Oscillator
Chapter Timer
Reset Reset Pin, Internal Operation Watch-Dog Timer (WDT) Power-On-Reset (POR)
Chapter Ports
Ports Mode Registers Input Output Registers Port General Mode Read/Write Operations Handshake Operation Port General Mode Read/Write Operations Handshake Operations PORT General Port Read/Write Operations 5-12 Handshake Operation 5-12 PORT 5-13 General Port 5-13 Read/Write Operations 5-18 Special Functions 5-18 Port Handshake 5-19 Port Reset Conditions 5-24 Full Reset 5-24
Chapter Ports
Analog Comparators 5-26
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Microcontrollers Table Contents Page 5-26 5-28 5-29 5-29 5-29 5-29 5-29 5-29 5-30 5-30 5-31 5-32
Comparator Description Comparator Programming Comparator Operation Interrupts Comparator Definitions Mode HALT Mode STOP Mode Open-Drain Configuration Emission Input Protection CMOS Auto Latches
Chapter Counter/Timers
Introduction Prescalers Counter/Timers Counter/Timer Operation Load Enable Count Bits Prescaler Operations TOUT Modes Modes External Clock Input Mode Gated Internal Clock Mode Triggered Input Mode 6-10 Retriggerable Input Mode 6-11 Cascading Counter/Timers 6-11 Reset Conditions 6-12
Chapter Interrupts
Introduction Interrupt Sources External Interrupt Sources Internal Interrupt Sources Interrupt Request (IRQ) Register Logic Timing Interrupt Initialization Interrupt Priority Register (IPR) Initialization Interrupt Mask Register (IMR) Initialization Interrupt Request (IRQ) Register Initialization Software Interrupt Generation
Chapter Interrupts (Continued)
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Vectored Processing Vectored Interrupt Cycle Timing 7-11 Nesting Vectored Interrupts 7-12 Polled Processing 7-12 Reset Conditions 7-12
Chapter Power-Down Modes
Introduction HALT Mode Operation STOP Mode Operation STOP-Mode Recovery Register (SMR)
Chapter Serial
UART Introduction UART Bit-Rate Generation UART Receiver Operation Receiver Shift Register Overwrites Framing Errors Parity Transmitter Operation Overwrites Parity UART Reset Conditions Serial Peripheral Interface (SPI) Operation Compare Clock Receive Character Available Overrun 9-11
Chapter External Interface
Introduction Descriptions RESET XTAL1, XTAL2 10-1 10-2 10-2 10-2 10-2 10-2 10-2 10-2 10-2 10-2
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Microcontrollers Table Contents Page
External Addressing Configuration 10-3 External Stacks 10-4 Data Memory 10-4 Operation 10-5 Address Strobe 10-6 Data Strobe 10-6 Extended Timing 10-7 Instruction Timing 10-9 Reset Conditions 10-10
Chapter Addressing Modes
Introduction Addressing Modes Register Addressing Indirect Register Addressing (IR) Indexed Addressing Direct Addressing (DA) Relative Addressing (RA) Immediate Data Addressing (IM) 11-1 11-1 11-2 11-3 11-5 11-6 11-7 11-8
Chapter Instruction
Functional Summary 12-1 Processor Flags.12-2 Condition Codes .12-5 Notation Binary Coding.12-6 Instruction Summary .12-8 Instruction Description Formats.12-11
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LIST FIGURES
Figure Title Page
Chapter Product Overview
Block Diagram .1-2
Chap[ter Address Space
16-Bit Register Addressing Accessing Individual Bits (Example) .2-2 Working Register Addressing Examples .2-3 Register Pointer .2-4 Expanded Register File Architecture .2-5 Register Pointer (FDH) Example .2-6 Program Memory .2-10 External Memory .2-11 Stack Pointer .2-12 Stack Operations .2-12
Chapter Clock
Clock Circuit .3-1 Stop-Mode Recovery Register (Write-Only Except Which Read-Only) .3-1 External Clock Circuit .3-2 Port Configuration Register (PCON) (Write-Only) .3-2 Pierce Oscillator with Internal Feedback Circuit .3-3 Circuit Board Design Rules .3-4 Crystal/Ceramic Resonator Oscillator .3-5 Clock .3-5
Chapter Clock (Continued)
External Clock .3-5
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Clock .3-6
Chapter Timer
Reset Timing .4-2 Example External Power-On Reset Circuit .4-3 Example Reset with /RESET Pin, WDT, SMR, .4-5 Example Reset with WDT, SMR, .4-6 Example Watch-Dog Timer Mode Register (Write-Only) .4-7 Example with Simple .4-8
Chapter Ports
Ports Mode Registers .5-1 Ports Generic Block Diagram .5-2 Port Configuration with Open-Drain Capability, Auto Latch, Schmitt-Trigger .5-3
Port Configuration with Level Shifter .5-4
Port Operation .5-5 Port Handshake Operation .5-5 Port Configuration with Open-Drain Capability, Auto Latch, Schmitt-Trigger .5-6 Port Configuration with Level Shifter .5-7 Port Operation .5-8 Handshake Operation .5-8 Port Mode Configuration .5-9 Port Configuration with Open-Drain Capability, Auto Latch, Schmitt-Trigger .5-9 Port Configuration with Level Shifter .5-10 Port Configuration with Open-Drain Capability, Auto Latch, Schmitt-Trigger .5-11 Port Handshake Configuration .-12 Port Handshaking .5-12 Port Block Diagram .5-13 Port Configuration with Comparator, Auto Latch, Schmitt-Trigger .5-14 Port Configuration with Comparator .5-15
Chapter Ports (Continued)
Port Configuration with Comparator Outputs Using .5-16 Port Configuration with Level Shifter Auto Latch .5-17 Port Mode Register Configuration .5-18 Input Handshake .5-20
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Microcontrollers List Figures Page
Output Handshake .5-21 Output Strobed Handshake Port .5-23 Input Strobed Handshake Port .5-23 Port Reset .5-24 Port Reset .5-25 Port Mode Reset .5-25 Port Input Analog Selection .5-26 Port Comparator Output Selection .5-26 Port Configuration Comparator Inputs P31, P32, .5-27 Port Configuration .5-28 Port Configuration .5-30 Port Configuration Register (PCON) (Write-Only) .5-30 Diode Input Protection .5-31 Diode Input Protection .5-31 Simplified CMOS Circuit .5-32
Auto Latch Equivalent Circuit .5-33
Effect Pulldown Resistors Auto Latches .5-33
Chapter Counter/Timers
Counter/Timer Block Diagram .6-1 Counter/Timer Register .6-2 Prescaler Register .6-2 Prescaler Register .6-2 Counter Timer Registers .6-2 Timer Mode Register .6-3 Starting Count .6-3 Counting Modes .6-3 Timer Mode Register (TOUT Operation) .6-5 Port Mode Register (TOUT Operation) .6-5 Output Through TOUT .6-6
Chapter Counter/Timers (Continued)
Internal Clock Output Through TOUT Timer Mode Register (TIN Operation) .6-7 Prescaler Register (TIN Operation) .6-7 External Clock Input Mode .6-8 Gated Clock Input Mode .6-9 Triggered Clock Mode .6-10 Cascaded Counter/Timers .6-11 Counter/Timer Reset .6-12 Prescaler Register Reset .6-12
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Prescaler Reset .6-12 Timer Mode Register Reset .6-12
Chapter Interrupts
Interrupt Control Registers .7-1 Interrupt Block Diagram .7-1 Interrupt Sources IRQ0-IRQ2 Block Diagram .7-2 Interrupt Source IRQ3 Block Diagram .7-3 Register Logic .7-4 Interrupt Request Timing .7-4
Interrupt Priority Register .7-5
Interrupt Mask Register .7-6 Interrupt Request Register .7-7 Reset Functional Logic Diagram .7-8 Effects Interrupt STACK .7-9 Interrupt Vectoring .7-10 Interrupt Acknowledge Timing .7-11
Chapter Power-Down Modes
STOP-Mode Recovery Register (Write-Only Except Which Read-Only) .8-3 STOP-Mode Recovery Source .8-4
Chapter Serial
UART Block Diagram .9-1 Port Mode Register (P3M) Bit-Rate Generation .9-2
Rate Divide Chain .9-2
Prescaler Register (PRE0) Bit-Rate Generation .9-3 Timer Mode Register (TMR) Rate Generation .9-4 Receiver Timing .9-4
Receiver Data Formats .9-5
Port Mode Register (P3M) Parity .9-5 Transmitter Data Formats .9-6 Register Reset .9-7 Register Reset .9-7 Control Register (SCON) .9-8 System Configuration .9-10 Timing .9-11 Logic .9-12 Data In/Out Configuration .9-13 Clock Slave Select Output Configuration .9-14 UM001600-Z8X0599
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Microcontrollers List Figures Page
Chapter External Interface
External Interface Pins .10-1 External Address Configuration .10-3 Stack Selection .10-4 Port Data Memory Operation .10-4 External Instruction Fetch Memory Read Cycle .10-5 External Memory Write Cycle .10-6 Extended External Instruction Fetch Memory Read Cycle .10-7 Extended External Memory Write Cycle .10-8 Extended Timing .10-8 Instruction Cycle Timing (One-Byte Instructions) .10-9 Instruction Cycle Timing (Two Three Byte Instructions) .10-10
Chapter Addressing Modes
8-Bit Register Addressing .11-2 4-Bit Register Addressing .11-2 4-Bit Register Addressing .11-3 Indirect Register Addressing Program Data Memory .11-4 Indexed Register Addressing .11-5 Direct Addressing .11-6 Relative Addressing .11-7 Immediate Data Addressing .11-8
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USER'S MANUAL
LIST TABLES
Table Title Page
Chapter Product Overview
ZiLOG General-Purpose Microcontroller Product Family
Chapter Address Space
Standard Register File Working Register Groups Bank Address Expanded Register File Bank Layout Expanded Register File Register Bank Group Expanded Register File Bank Group Expanded Register File Bank Group
Chapter Timer
Sample Control Peripheral Register Reset Values (ERF Bank Expanded Register File Bank Reset Values RESET Sample Expanded Register File Bank Reset Values Sample Expanded Register File Bank Reset Values Time-Out Period
Chapter Ports
Port Line Functions 5-19
Chapter Interrupts
Interrupt Types, Sources, Vectors Interrupt Priority Interrupt Group Priority Register Configuration
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Chapter Power-Down Modes
STOP-Mode Recovery Source
Chaper Serial
UART Register Rates Configuration
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CHAPTER
PRODUCT OVERVIEW
FAMILY OVERVIEW
ZiLOG microcontroller (MCU) product line continues expand with product introductions. ZiLOG products targeted cost-sensitive, high-volume applications including consumer, automotive, security, HVAC. includes ROM-based products geared highvolume production (where software stable) one-time programmable (OTP) equivalents prototyping well volume production where time market code flexibility critical (Table 1-1). variety packaging options available including plastic DIP, SOIC, PLCC, QFP. generalized MCU® block diagram shown Figure 1-1. same on-chip peripherals used across product line with primary differences being amount ROM/RAM, number lines present, packaging/temperature ranges available. This allows code written device easily ported another family member.
1.1.1 Product Line Features
General-Purpose Register (GPR) File: Every register acts like accumulator, speeding instruction execution maximizing coding efficiency. Working register groups allow fast context switching. Flexible I/O: byte, nibble, and/or programmable inputs outputs. Outputs software programmable open-drain push-pull port basis. Inputs Schmitt-triggered with auto latches hold unused inputs known voltage state. Analog Inputs: Three input pins software programmable digital analog inputs. When analog mode, comparator inputs provided with common reference input. These inputs ideal variety common functions, including threshold level detection, analog-to-digital conversion, short circuit detection. Each analog input provides unique maskable interrupt input. Timer/Counter(T/C): consists programmable 6-bit prescaler 8-bit downcounter, with maskable interrupt upon end-of-count. Software controls load/start/stop, countdown read time fly), maskable end-of-count interrupt. Special functions available include (external counter input, external gate input, external trigger input) TOUT (external access timer output internal system clock.) These special functions allow accurate hardware input pulse measurement output waveform generation. Interrupts: There vectored interrupt sources with software-programmable enable priority each sources. Watch-Dog Timer (WDT): internal circuit included fail-safe mechanism that software strays outside bounds normal operation, will timeout reset MCU. maximize circuit robustness reliability, default clock source internal circuit (isolated from device clock source). Auto Reset/Low-Voltage Protection: family devices have internal Power-On Reset. devices low-voltage protection. Low-voltage protection ensures known state times active mode RESET) without external hardware device reset pin). Low-EMI Operation: Mode programmable software mask option. This option provides reduced radiated emission clock output drive circuit changes.
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FAMILY OVERVIEW (Continued)
Low-Power: CMOS with standby modes; STOP HALT. Full Instruction Set: Forty-eight basic instructions, supported addressing modes with ability operate bits, nibbles, bytes, words.
Output
Input
XTAL R//W /RESET
Port
Machine Timing Instruction Control RESET, WDT,
Counter/ Timers FLAG
Interrupt Control
Prg. Memory 512/K 8-Bit Register Pointer Register File 8-Bit
Analog Comparators
Program Counter
Port
Port
Port
(Bit Programmable)
Address/Data (Byte Programmable)
Address (Nibble Programmable)
Figure 1-1. Block Diagram
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Microcontrollers Product Overview
1.1.2 Product Development Support
product line fully supported with range cross assemblers, compilers, ICEBOX emulators, single gang OTP/EPROM programmers, software simulators. Z86CCP01ZEM low-cost CCPreal-time emulator/programmer designed specifically support products outlined Table 1-1.
Table 1-1. ZiLOG General-Purpose Microcontroller Product Family PRODUCT Z86C03 Z86E03 Z86C04 Z86E04 Z86C06 Z86E06 Z86C08 Z86E08 Z86C30 Z86E30 Z86C31 Z86E31 Z86C40 Z86E40 ROM/RAM 512/60 512/60 1K/124 1K/124 1K/124 1K/124 2K/124 2K/124 4K/236 4K/236 2K/124 2K/124 4K/236 4K/236
SPEED (MHz)
COUNT 40/44 40/44
Note: Z86Cxx signify devices; 86xx signify EPROM devices; fixed; programmable
Z86CCP01ZEM comes with: Evaluation Board Power Cable ZiLOG Developer's Studio (ZDS) CD-ROM Including Windows-Based1 Host Software 1999 ZiLOG Technical Library User's Manual
Emulator Accessory (Z8CCP00ZAC) also available provides RS-232 cable power cable along with sockets 40pin target connector cables required emulate/program 28/40 devices.
Windows trademark Microsoft Corporation.
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CHAPTER
ADDRESS SPACE
INTRODUCTION
Four address spaces available MCU®: Standard Register File contains addresses peripheral, control, general-purpose, port registers. This default register file specification. Expanded Register File (ERF) contains addresses control data registers additional peripherals/features. External Program Memory contains addresses memory locations having executable code and/or data. External Data Memory contains addresses memory locations that hold data only, whether internal external.
STANDARD REGISTER FILE
Standard Register File totals consecutive bytes (Registers). register file consists ports (00H-03H), General-Purpose Registers (04H-EFH), control registers (F0H-FFH). Table shows layout register file, including register names, locations, identifiers. Table 2-1. Standard Register File Address Register Description Stack Pointer Byte Stack Pointer High Byte Register Pointer Program Control Flags Interrupt Mask Register Interrupt Request Register Interrupt Priority Register Port Mode Register Port Mode Register Port Mode Register Prescaler Timer/Counter Prescaler Timer/Counter Timer Mode Register Identifier FLAGS P01M PRE0 PRE1 Table 2-1. Standard Register File Address Register Description Serial General-Purpose Registers (GPR) Register Identifier R239
Port Port Port Port
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STANDARD REGISTER FILE (Continued)
Registers accessed either 8-bit 16-bit registers using Direct, Indirect, Indexed Addressing. general-purpose registers referenced modified instruction that accesses 8-bit register, without need special instructions. Registers accessed bits treated even-odd register pairs (there valid pairs). this case, data's Most Significant Byte (MSB) stored even numbered register, while Least Significant Byte (LSB) goes into next higher numbered register (Figure 2-1).
2.2.1 General-Purpose Registers
General-Purpose Registers (GPR) undefined after device powered registers keep their last value after reset, long reset occurs voltage-specified operating range. will keep last state from reset drops below 1.8v. Note: Registers Bank E0-EF only accessed through working register indirect addressing modes. Direct access cannot used because 4-bit working register address mode already uses format dst], where represents working register number from
Rn+1
2.2.2 Protect
upper portion register file address space (excluding control registers) protected from reading writing. Protect option mask-programmable selected customer when code submitted. After mask option selected, user activates this feature from internal code turn off/on Protect loading either into register, enables Protect. Only devices that registers offer this feature.
Even Address
Figure 2-1. 16-Bit Register Addressing using logical instruction mask, individual bits within registers accessed set, clear, complement, test operations. example, instruction R15, MASK performs clear operation. Figure shows this example.
2.2.3 Working Register Groups
MASK
instructions access 8-bit registers register pairs (16-bit words) using either 4-bit 8-bit address fields. 8-bit address fields refer actual address register. example, Register accessed calling upon 8-bit binary equivalent, 01011000 (58H). With 4-bit addressing, register file logically divided into Working Register Groups registers each, shown Table 2-2. These registers known Working Registers. Register Pointer (one control registers, FDH) contains base address active Working Register Group. high nibble Register Pointer determines current Working Register Group. When accessing Working Registers, 4-bit address Working Register combined within upper four bits (high nibble) Register Pointer, thus forming 8-bit actual address. Figure illustrates this operation. Since working registers typically specified short format instructions, there fewer bytes code needed, which reduces execution time. addition, when processing interrupts changing tasks, Register Pointer speeds context switching. special Register Pointer (SRP) instruction sets contents Register Pointer.
R15,
;Clear Working Register
Figure 2-2. Accessing Individual Bits (Example) When instructions executed, registers read when defined sources written when defined destinations. General-Purpose Registers function accumulators, address pointers, index registers, stack areas, scratch memory.
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ZiLOG Table 2-2. Working Register Groups Register Pointer (FDH) High Nibble 1111(B) 1110(B) 1101(B) 1100(B) 1011(B) 1010(B) 1001(B) 1000(B) 0111(B) 0110(B) 0101(B) 0100(B) 0011(B) 0010(B) 0001(B) 0000(B) Working Register Group (HEX) Actual Registers (HEX) F0-FF E0-EF D0-DF C0-CF B0-BF A0-AF 90-9F 80-8F 70-7F 60-6F 50-5F 40-4F 30-3F 20-2F 10-1F 00-0F
Microcontrollers Address Space
Register Pointer (FHD), Standard Register File
(Instruction, Short Format)
Actual Register Address (76H)
Figure 2-3. Working Register Addressing Examples
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STANDARD REGISTER FILE (Continued)
R253 (Register Pointer)
upper nibble register file address, provided register pointer, specifies active working-register group. Working Register Group
Specified Working Register Group
lower nibble register file address (provided instruction) points specified register.
Working Register Group Working Register Group Ports
Figure 2-4. Register Pointer
Note: full register file shown. Please refer selected device product specification actual file size.
2.2.4 Error Conditions
Registers Standard Register File must correctly used because certain conditions produce inconsistent results should avoided. Registers F5H-F9H write-only registers. attempt made read these registers, returned. Reading write-only register will return FFH. When register (Register Pointer) read, least significant four bits (lower nibble) will indicate current Expanded Register File Bank. (Example: 0000 indicates Standard Register File, while 1010 indicates Expanded Register File Bank When Ports defined address outputs, registers will return each address location when read. Writing bits that defined timer output, serial output, handshake output will have effect. instruction DJNZ uses general-purpose working register counter. Logical instructions such require that current contents operand read. They therefore will function properly write-only registers. WDTMR register must written within first internal system clocks (SCLK) operation after reset.
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Microcontrollers Address Space
EXPANDED REGISTER FILE
standard register file been expanded form Expanded Register File (ERF) Banks (Figure 2-5). Each Bank consists registers (the same amount Standard Register File) that then divided into Working Register Groups. This expansion allows access additional feature/peripheral control data registers.
Expanded Register File Bank Register Pointer Working Register Group Pointer Expanded Register Group Pointer Register File WDTMR Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved PCON Expanded Register File Bank Expanded Register File Bank Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved SCON RXBUF SCOMP
Figure 2-5. Expanded Register File Architecture
Note: fully implemented register file shown. Please refer specific product specification actual register file architecture implemented.
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EXPANDED REGISTER FILE (Continued)
Currently, three possible sixteen Banks have been implemented. Bank also known Standard Register File, bytes defined (Figure 2-1). Only Working Register Group (register addresses 0FH) have been defined Bank Bank (Table 2-4). other working register groups Banks well remaining thirteen Banks, implemented. reserved future use. When Bank selected, register addresses access those sixteen Bank registers effect replacing first sixteen locations Standard Register File. example, Bank selected, Standard Registers through longer accessible. Registers through registers from Bank Working Register Group other Standard Registers effected since only Working Register Group implemented Bank Access accomplished through Register Pointer (FDH). lower nibble Register Pointer determines Bank while upper nibble determines Working Register Group within register file (Figure 2-6). Table 2-3. Bank Address Register Pointer (FDH) Nibble 0000(B) 0001(B) 0010(B) 0011(B) 0100(B) 0101(B) 0110(B) 0111(B) 1000(B) 1001(B) 1010(B) 1011(B) 1100(B) 1101(B) 1110(B) 1111(B)
Register File Standard Register File Expanded Register File Bank Expanded Register File Bank Expanded Register File Bank Expanded Register File Bank Expanded Register File Bank Expanded Register File Bank Expanded Register File Bank Expanded Register File Bank Expanded Register File Bank Expanded Register File Bank Expanded Register File Bank Expanded Register File Bank Expanded Register File Bank Expanded Register File Bank Expanded Register File Bank
Note: Standard Register File equivalent Expanded Register File Bank
0111 Working Register Group
1100 Expanded Register Bank
Select Bank C(H) Working Register Group 7(H)
Figure 2-6. Register Pointer (FDH) Example value lower nibble Register Pointer (FDH) corresponds Bank identification. Table shows lower nibble value register file assigned
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ZiLOG upper nibble register pointer selects which group bytes Register File, full 256, will accessed working registers. example: (See Figure 2-4) R253 ;ERF Bank Working Reg. Group Port Port Port Port ;ERF Bank Working Reg. Group PCON Reserved Reserved WDTMR ;ERF Bank Working Reg. Group PCON 01H= Reserved 02H= Reserved WDTMR
Microcontrollers Address Space Table 2-4. Expanded Register File Bank Layout Expanded Register File Bank F(H)
PCON, SMR, WDT, (00H, 0BH, 0FH), Working Register Group only implemented. Implemented (Reserved) Implemented (Reserved) Registers: SCOMP, RXBUF, SCON (00H, 01H, 02H), Working Register Group only implemented. Implemented (Reserved) Implemented (Reserved) Implemented (Reserved) Implemented (Reserved) Implemented (Reserved) Implemented (Reserved) Implemented (Reserved) Implemented (Reserved) Implemented (Reserved) Implemented (Reserved) Implemented (Reserved) Ports General-Purpose Registers EFH, control registers FFH.
E(H) D(H) C(H)
R253
B(H) A(H) 9(H) 8(H) 7(H) 6(H) 5(H) 4(H) 3(H) 2(H) 1(H) 0(H)
R253
Since enabling Bank only changes register addresses 0FH, working register pointer used access either selected Bank (Bank Working Register Group Standard Register File (ERF Bank Working Register Groups through Note: When Bank other than Bank enabled, first bytes Standard Register File (I/O ports Groups longer accessible (the selected Bank, Registers accessed instead). important re-initialize Register Pointer enable Bank when these registers required use. register mapped into Bank Access easily done using following example: #0CH R2,#xx #00H ;Select Bank working ;register group access. ;access SCON ;access RXBUF ;Select Bank ports ;are again accessible.
Please refer specific product specification determine above registers implemented.
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CONTROL PERIPHERAL REGISTERS 2.4.1 Standard Registers
standard control registers govern operation CPU. instruction which references register file access these control registers. Available control registers are: Interrupt Priority Register (IPR) Interrupt Mask Register (IMR) Interrupt Request Register (IRQ) Program Control Flags (FLAGS) Register Pointer (RP) Stack Pointer High-Byte (SPH) Stack Pointer Low-Byte (SPL)
2.4.2 Expanded Registers
expanded control registers govern operation additional features peripherals. instruction which references register file access these registers. contains control registers WDT, Port Control, Serial Peripheral Interface (SPI), functions. Figure shows layout Register Banks ERF. Register Bank consists registers SPI. Table shows registers within Bank Working Register Group Table 2-5. Expanded Register File Register Bank Group Register Register Function Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Control (SCON) Tx/Rx Data (Roxburgh) Compare (SCOMP) Working Register
uses 16-bit Program Counter (PC) determine sequence current program instructions. addressable register. Peripheral registers used transfer data, configure operating mode, control operation onchip peripherals. instruction that references register file access peripheral registers. peripheral registers are: Serial (SIO) Timer Mode (TMR) Timer/Counter (T0) Prescaler (PRE0) Timer/Counter (T1) Prescaler (PRE1) Port Mode (P01M) Port Mode (P2M) Port Mode (P3M)
addition, four port registers (P0-P3) considered peripheral registers.
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ZiLOG Working Register Group Bank consists registers General-Purpose Registers ports. Table shows registers within this group. Table 2-6. Expanded Register File Bank Group Register Register Function General-Purpose Register General-Purpose Register General-Purpose Register General-Purpose Register General-Purpose Register General-Purpose Register General-Purpose Register General-Purpose Register General-Purpose Register General-Purpose Register General-Purpose Register General-Purpose Register Port Port Port Port Working Register
Microcontrollers Address Space Working Register Group Bank consists control registers STOP mode, WDT, port control. Table shows registers within this group. Table 2-7. Expanded Register File Bank Group Register Register Function WDTMR Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved PCON Working Register
functions applications control peripheral registers described subsequent sections this manual.
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PROGRAM MEMORY
first bytes Program Memory reserved interrupt vectors (Figure 2-7). These locations contain 16-bit vectors that correspond available interrupts. Address maximum address consists on-chip mask-programmable ROM. product data sheet exact program, data, register memory size, address range available. addresses outside internal ROM, executes external program memory fetches through Port Port Address/Data mode devices with Port Port featured. Otherwise, program counter will continue execute NOPs address FFFFH, roll over 0000H, continue fetch executable code (Figure 2-7). internal program memory one-time programmable (OTP) mask programmable dependent specific device. protect feature prevents dumping contents inhibiting execution LDC, LDCI, LDE, LDEI instructions Program Memory modes. look-up tables cannot used with this feature. Protect option mask-programmable, selected customer when code submitted. ROM, Protect option programming option.
65535 External 4096 4095 Location First Byte Instruction Executed After RESET Interrupt Vector (Lower Byte) Interrupt Vector (Upper Byte) IRQ5 IRQ5 IRQ4 IRQ4 IRQ3 IRQ3 IRQ2 IRQ2 IRQ1 IRQ1 IRQ0 IRQ0 Chip
Figure 2-7. Program Memory
2-10
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EXTERNAL MEMORY
some cases, capability access external program memory with 16-bit Program Counter. access external program memory offers multiplexed address/data lines (AD7-AD0) Port address lines (A15-A8) Port This feature only applies devices that offer Port Port maximum external address FFFF. This memory interface supported control lines (Address Strobe), (Data Strobe), (Read/Write). origin external program memory starts after last address internal ROM. Figure shows example external program memory
2.6.1 External Data Memory (/DM)
some cases, address Kbytes external data memory beginning location 4096. External Data Memory included with, separated from, external Program Memory space. optional function that programmed appear P34, used distinguish between data program memory space. state signal controlled type instruction being executed. opcode references Program inactive) Memory, instruction references Data active Low) Memory. user must configure Port Mode Register (P3M) bits this mode.
65535
External Memory
4096 4095 Addressable
Figure 2-8. External Memory
Note: additional information using external memory, Chapter this manual. exact memory addressing options available, device product specification.
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STACKS
Stack operations occur either Standard Register File external data memory. Under software control, Port Mode register (F8H) selects stack location. Only General-Purpose Registers used stack when internal stack selected. register pair form 16-bit Stack Pointer (SP), that used stack operations. stack address stored with (Figure 2-9). stack address decremented prior PUSH operation incremented after operation. stack address always points data stored stack. stack return stack CALL instructions interrupts, well data stack. During CALL instruction, contents saved stack. restored during RETURN instruction. Interrupts cause contents Flag registers saved stack. IRET instruction restores them (Figure 2-10). When configured internal stack (using Standard Register File), register serves Stack Pointer. value ignored. used general-purpose register this case only. overflow underflow occur when stack address incremented decremented during normal stack operations. programmer must prevent this occurrence unpredictable operation will result.
LOWER Byte Stack Pointer
UPPER Byte Stack Pointer High
Figure 2-9. Stack Pointer
Stack
Stack
FLAGS
Stack Contents After Call Instruction
Stack Contents After Interrupt Cycle
Figure 2-10. Stack Operations
2-12
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CLOCK
CLOCK
MCU® derives timing from on-board clock circuitry connected pins XTAL1 XTAL2. clock circuitry consists oscillator, divide-by-two shaping circuit, clock buffer. Figure illustrates clock circuitry. oscillator's input XTAL1 output XTAL2. clock driven crystal, ceramic resonator, clock, external clock source. flop bypassed such that XTAL clock frequency equal internal system clock frequency. this mode, maximum frequency XTAL clock MHz. Please refer specific product specification availability options output drive characteristics.
3.1.1 Frequency Control
some cases, EPROM/OTP option Mask option bypass divide-by-two flip flop Figure 3-1. This feature used conjunction with option. When selected, device output drive oscillator drive reduced approximately percent standard drive divide-by-two flip
XTAL1 XTAL2
Buffer
Internal Clock
Figure 3-1. Clock Circuit
CLOCK CONTROL
some cases, offers software control internal system clock programming register bits. bits located Stop-Mode Recovery Register Expanded Register File Bank Register 0BH. This register selects clock divide value determines mode StopMode Recovery (Figure 3-2). Please refer specific product specification availability this feature/register.
SCLK/TCLK Divide External Clock Divide Mode SCLK/TCLK XTAL/2* SCLK/TCLK XTAL
Default setting after RESET. **Default setting after RESET STOP-Mode Recovery.
Figure 3-2. Stop-Mode Recovery Register (Write-Only Except Which Read-Only)
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3.2.1 SCLK/TCLK Divide-By-16 Select (D0)
This controls divide-by-16 prescalar SCLK/TCLK. purpose this control selectively reduce device power consumption during normal processor execution (SCLK control) and/or HALT mode (where TCLK sources counter/timers interrupt logic).
OSCILLATOR CONTROL
some cases, offers software control oscillator select drive standard drive. selection done programming Port Configuration (PCON) register (Figure 3-4). PCON register located Expanded Register File Bank Register 00H. configures oscillator with standard drive, while configures oscillator with drive. This only affects drive capability oscillator does affect relationship XTAL clock frequency internal system clock (SCLK).
PCON (FH) Oscillator Standard
3.2.2 External Clock Divide-By-Two (D1)
This eliminate oscillator divide-by-two circuitry. When this SCLK (System Clock) TCLK (Timer Clock) equal external clock frequency divided two. SCLK/TCLK equal external clock frequency when this Using this bit, together with PCON, further helps lower (PCON) (SMR) default setting Maximum frequency with D1=1 (Figure 3-3).
(SMR)
Figure 3-4. Port Configuration Register (PCON) (Write-Only)
(SMR)
External Clock
Figure 3-3. External Clock Circuit
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Microcontrollers Clock
OSCILLATOR OPERATION
uses Pierce oscillator with internal feedback (Figure 3-5). advantages this circuit cost, large output signal, low-power level crystal, stability with respect temperature, impedances (not disturbed stray effects). draw back need high gain amplifier compensate feedback path losses. oscillator amplifies noise start-up until settles frequency that satisfies gain/phase requirements where V0/VI gain amplifier VI/V0 gain feedback element. total phase shift around loop forced zero (360 degrees). Since must phase with itself, amplifier/inverter provides degree phase shift feedback element forced provide other degrees phase shift. resistive component placed from output input amplifier. purpose this feedback bias amplifier linear region provide start-up transition. Capacitor combined with amplifier output resistance provides small phase shift. will also provide some attenuation overtones. Capacitor combined with crystal resistance provides additional phase shift. affect start-up time they increase dramatically size. increase, start-up time increases until oscillator reaches point where does start more. recommended fast reliable oscillator start-up (over manufacturing process range) that load capacitors sized possible without resulting overtone operation.
XTAL1
XTAL2
Figure 3-5. Pierce Oscillator with Internal Feedback Circuit
3.4.1 Layout
Traces connecting crystal, caps, oscillator pins should short wide possible. This reduces parasitic inductance resistance. components (caps, crystal, resistors) should placed close possible oscillator pins traces from oscillator pins ground side lead caps should guarded from other traces (clock, VCC, address/data lines, system ground) reduce cross talk noise injection. This usually accomplished keeping other traces system ground trace planes away from oscillator circuit placing device ground ring around traces/components. ground side oscillator lead caps should connected single trace (GND) pin. should shared with other system ground trace components except device pin. This prevent differential system ground noise injection into oscillator (Figure 3-6).
3.4.2 Indications Unreliable Design
There major indicators that used working designs determine their reliability over full temperature variations. They are: Start-up Time. start time excessive, varies widely from unit unit, there probably gain problem. C1/C2 needs reduced; amplifier gain adequate frequency, crystal large. Output Level. signal amplifier output should swing from ground VCC. This indicates there adequate gain amplifier. oscillator starts signal amplitude grows until clipping occurs, which point loop gain effectively reduced unity constant oscillation achieved. signal less than volts peak-topeak indication that gain problem. Either should made smaller low-resistance crystal should used.
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ZiLOG internal system clock output should separated much possible. power lines should separated from clock oscillator input circuitry. Resistivity between XTAL1 XTAL2 other pins should greater than Mohms.
3.4.3 Circuit Board Design Rules
following circuit board design rules suggested: prevent induced noise crystal load capacitors should physically located close possible. Signal lines should parallel clock oscillator inputs. particular, crystal input circuitry
XTAL1 XTAL2 Clock Generator Circuit Signals
Signal Line Layout Should Avoid High Lighted Areas
(Parallel Traces Must Avoided) Signal Board Design Example (Top View)
(Connection System Group Must Avoided)
Figure 3-6. Circuit Board Design Rules
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3.4.4 Crystals Resonators
Crystals ceramic resonators (Figure 3-7) should have following characteristics ensure proper oscillator operation: Crystal Mode Crystal Capacitance Load Capacitance Resistance (crystal only) Parallel, Fundamental Mode <7pF 10pF typical ohms most cases, Ohms infinite. determined specified crystal/ceramic resonator manufacturer. increased decrease amount drive from oscillator output crystal. also used adjustment avoid clipping oscillator signal reduce noise. used improve start-up crystal/ceramic resonator. oscillator already internal shunt resistor parallel crystal/ceramic resonator.
Depending operation frequency, oscillator require addition capacitors (shown Figures 3-7). capacitance values dependent manufacturer's crystal specifications.
XTAL1
XTAL1 XTAL2
XTAL2
Figure 3-9. External Clock recommended Figures 3-7, 3-8, connect load capacitor ground trace directly (GND) Z8®. This ensures that system noise injected into clock. This trace should shared with other components except some cases, XTAL1 also functions EPROM high-voltage mode programming pins special factory test pin. this case, applying above XTAL1 will cause device enter these modes. Since this accepts high voltages enter these respective modes, standard input protection diode XTAL1. recommended that applications where exposed much system noise, diode from XTAL1 used prevent accidental enabling these modes. This diode will affect crystal/ceramic resonator operation. Please note that parallel resonant crystal resonator data sheet will specify load capacitor value that series combination including parasitics (PCB holder).
Figure 3-7. Crystal/Ceramic Resonator Oscillator
XTAL1 XTAL2
Figure 3-8. Clock
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ZiLOG Simple series capacitance calculated using following equation:
OSCILLATOR
oscillator network generate XTAL clock (Figure 3-8). frequency stays stable over temperature. oscillation frequency determined equation: (LCT)1/2
Frequency
where total inductance including parasitics total series capacitance including parasitics.
Sample calculation capacitance 5.83 frequency inductance value 5.83 (10^6) 27.6 Thus 55.2 55.2 [2.7 (10-6)
OSCILLATOR
some cases, oscillator option. Please refer specific product specification availability. oscillator requires resistor across XTAL1 XTAL2. additional load capacitor required from XTAL1 input (Figure 3-10).
XTAL1
XTAL2
Figure 3-10. Clock
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RESET-WATCH-DOG TIMER
RESET
This section describes MCU® reset conditions, reset timing, register initialization procedures. Reset generated Power-On Reset (POR), Reset Pin, Watch-Dog Timer (WDT), Stop-Mode Recovery. system reset overrides other operating conditions puts into known state. initialize chip's internal logic, RESET input must held least XTAL clock cycles. control register ports reset their default conditions after POR, reset from RESET pin, Watch-Dog Timer timeout while mode HALT mode. control registers ports reset their default conditions after StopMode Recovery timeout while STOP mode. While RESET Low, output internal clock rate, forced Low, R//W remains High. program counter loaded with 000CH. ports control registers configured their default reset state. Resetting does effect contents general-purpose registers.
RESET PIN, INTERNAL OPERATION
some cases, hardware RESET initializes control peripheral registers, shown Tables 4-1, 4-3, 4-4. Specific reset values shown while bits whose states unknown indicated letter Tables 4-1, 4-2, 4-3, show reset conditions generic Note: register file reset state device dependent. Please refer selected device product specifications register availability reset state.
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RESET PIN, INTERNAL OPERATION (Continued)
Table 4-1. Sample Control Peripheral Register Reset Values (ERF Bank Register (HEX) Register Name Serial Timer Mode Counter/Timer1 Prescaler Counter/Timer0 Prescaler Port Mode Port Mode Port Mode Interrupt Priority Interrupt Request Interrupt Mask Flags Register Pointer Stack Pointer (High) Stack Pointer (Low) Bits
Comments Counter/Timers Stopped Single-Pass Count Mode, External Clock Source
Single-Pass Count Mode Inputs Port Open-Drain, P33-P30 Input, P37-P34 Output Internal Stack, Normal Memory Timing Interrupts Cleared Interrupts Disabled
Program execution starts clock cycles after internal RESET returned High. initial instruction fetch from location 000CH. Figure shows reset timing.
First Machine Cycle Clock
SCLK
RESET
Hold SCLK Periods (Minimum)
First Instruction Fetch
Figure 4-1. Reset Timing
UM001600-Z8X0599
ZiLOG After reset, first routine executed should that initializes control registers required system configuration. RESET input Schmitt-triggered circuit. Resetting will initialize port control registers their default states. form internal reset line, output trigger synchronized with internal clock. clock must therefore running RESET function. requires internal system clocks after reset detected reset internal circuitry. internal pull-up, combined with external capacitor provides enough time properly reset (Figure 4-2). some cases, internal timer circuit that holds reset mode duration (TPOR) before releasing device reset. these devices, internally generated reset drives reset time. devices driving reset line must open-drained order avoid damage from possible conflict during reset conditions. This reset time allows on-board clock oscillator stabilize. avoid asynchronous noisy reset problems, equipped with reset filter four external clocks (4TpC). external reset signal less than 4TpC duration, reset occurs. fifth clock after reset detected, internal signal latched held internal register count external clocks,
Microcontrollers Reset-Watch-Dog Timer ration external reset, whichever longer. During reset cycle, held active while cycles rate internal system clock. Program execution begins location 000CH, 5-10 cycles after RESET released. internal Power-On Reset, reset output time specified TPOR. Please refer specific product specifications actual values.
/RESET
Figure 4-2. Example External Power-On Reset Circuit
Table 4-2. Expanded Register File Bank Reset Values RESET Register (HEX) Register Name Port Port Port Port Bits
Comments Input mode, output push-pull Input mode, output push-pull Input mode, output open drain Standard Digital input output Z86L7X Family Device Port P34-P37 (Except Z86L70/71/75) other Undefined
04-EF
GeneralPurpose Registers 04-EF
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RESET PIN, INTERNAL OPERATION (Continued)
Table 4-3. Sample Expanded Register File Bank Reset Values Register (HEX) Register Name Compare (SCOMP) Receive Buffer (RxBUF) Control (SCON) Bits
Comments
Table 4-4. Sample Expanded Register File Bank Reset Values Register (HEX) Register Name Port Configuration (PCON) Bits Comments Comparator outputs disabled Port Port output push-pull Port oscillator with standard output drive Clock divide XTAL divide External Reset Stop delay Stop recovery level low, STOP flag time out, runs during STOP
STOP-Mode Recovery (SMR)
Watch-Dog Timer Mode (WDTMR)
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Microcontrollers Reset-Watch-Dog Timer
/RESET
Clock Filter
Clear
Clock RESET Generator
RESET Internal RESET
Select (WDTMR) Source Select (WDTMR) XTAL OSC.
SELECT
1024
4096
WDT/POR Counter Chain
2.6V
2.6V Operating Voltage Det.
/WDT
From Stop Mode Recovery Source
Stop Delay Select (SMR)
Figure 4-3. Example Reset with RESET Pin, WDT, SMR,
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RESET PIN, INTERNAL OPERATION (Continued)
Clock Filter
CLEAR Clock RESET Generator
RESET Internal RESET
Select (WDTMR) Source Select (WDTMR) XTAL Internal OSC.
SELECT
15ms
25ms
100ms
WDT/POR Counter Chain
Operating Voltage Det.
From Stop Mode Recovery Source
Stop Delay Select (SMR)
Figure 4-4. Example Reset with WDT, SMR,
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Microcontrollers Reset-Watch-Dog Timer
WATCH-DOG TIMER (WDT)
retriggerable one-shot timer that resets reaches terminal count. When operating HALT modes, reset functionally equivalent hardware reset. initially enabled executing instruction refreshed subsequent executions instruction. cannot disabled after been initially enabled. Permanently enabled WDTs always enabled instruction used refresh circuit driven on-board oscillator external oscillator from XTAL1 pin. clock source selected with Watch-Dog Timer Mode register (WDTMR). some cases, that offers does have WDTMR register, fixed timeout uses board oscillator only clock source. Please refer specific product specifications selectability timeout, during HALT STOP modes, source clock, availability permanently-on option. Note: Execution instruction affects (zero), (sign), (overflow) flags. WDTMR located Expanded Register File Bank register 0FH. control bits described follows: Time Select (D1, D0). Bits control circuit that determines time-out period. Table shows different values that obtained. default value respectively.
Table 4-5. Time-Out Period Time-Out Typical Time-Out Internal
Clock 256TpC 512TpC 1024TpC 4096TpC
WDTMR TAP* 01** 2048
Notes: XTAL clock cycle default reset values given 5.0V. device product specification exact WDTMR time select options available.
During HALT (D2). This determines whether active during HALT mode. indicates active during HALT. default time during HALT mode will reset control register ports their default reset conditions. During STOP (D3). This determines whether active during STOP mode. Since XTAL clock stopped during STOP Mode, unless specified below, on-board must selected clock source counter. indicates active during STOP. default bits both only, driven external clock during STOP mode. This feature makes possible wake from STOP mode from internal source. Please refer specific product specifications conditions control port registers when comes STOP mode. time during STOP mode will reset control registers. reset conditions ports from STOP mode time same recovered using other STOP mode sources.
During HALT During STOP XTAL1/INT Select On-Board XTAL Reserved (Must Must Z86C03 Default setting after RESET
Figure 4-5. Example Watch-Dog Timer Mode Register (Write-Only) Note: WDTMR register accessible only during first processor cycles from execution first instruction after Power-On Reset, Watch-Dog Reset Stop-Mode Recovery. After this point, register cannot modified means, intentional otherwise. WDTMR write-only register. UM001600-Z8X0599
Microcontrollers Reset-Watch-Dog Timer Clock Source (D4). This determines which oscillator source used clock internal counter chain. internal oscillator bypassed clock source driven from external pin, XTAL1. default configuration this which selects internal oscillator. Bits These bits reserved.
ZiLOG
Voltage Comparator. on-board voltage comparator checks that required level insure correct operation device. Reset globally driven below specified voltage. This feature available select devices. device product specification feature availability operating range.
POWER-ON-RESET (POR)
timer circuit clocked dedicated on-board oscillator used Power-On Reset (POR) timer (TPOR) function. time allows oscillator circuit stabilize before instruction execution begins. timer circuit one-shot timer triggered three conditions: Power fail Power status (cold start). STOP-Mode Recovery SMR=1). timeout. time specified TPOR. devices that feature Stop-Mode Recovery register (SMR), selects whether timer used after Stop-Mode Recovery by-passed. then timer used. then timer by-passed. this case, Stop-Mode Recovery source must held recovery state crystal clocks pass reset signal internally. This option used when clock provided with RC/LC clock. device product specification timing details. (cold start) will always reset control port registers their default condition. register, warm start will reset indicate POR.
(Cold Start) (Stop Mode) Delay Line TPOR
XTAL
Reset Filter
Chip Reset
Figure 4-6. Example with Simple
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PORTS
PORTS
lines dedicated input output. These lines grouped into four 8-bit ports known Port Port Port Port Port nibble programmable input, output, address. Port byte configurable input, output, address/data. Port programmable either inputs outputs, with without handshake SPI. Port programmed provide timing, serial parallel input/output, comparator input/output. ports have push-pull CMOS outputs. addition, push-pull outputs Port turned open-drain operation.
5.1.1 Mode Registers
Each port associated Mode Register that determines port's functions allows dynamic change port functions during program execution. Port Mode Registers mapped into Standard Register File shown Figure 5-1.
instruction which addresses register address ports. Data directly accessed Port Register, with extra moves.
5.1.2 Input Output Registers
Each Ports have input register, output register, associated buffer, control logic. Since there separate input output registers associated with each port, writing bits defined inputs stores data output register. This data cannot read long bits defined inputs. However, bits reconfigured outputs, data stored output register reflected output pins then read. This mechanism allows user initialize outputs prior driving their loads (Figure 5-2). Since port inputs asynchronous internal clock, READ operation could occur during input transition. this case, logic level might uncertain (somewhere between logic eliminate this meta-stable condition, latches input data clock periods prior execution current instruction. input register uses these clock periods stabilize legitimate logic level before instruction reads data. Note: following sections describe generic function ports. additional features ports such SPI, C/T, Stop-Mode Recovery covered their section.
Register Port Mode Port Mode Port Mode
Identifier P01M
Port Port Port Port
Figure 5-1. Ports Mode Registers Because their close association, Port Mode Registers treated like other general-purpose register. There special instructions port manipulation. UM001600-Z8X0599
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PORT
This section deals with only operation Port port's external memory interface operation covered later this manual. Figure shows block diagram Port This diagram also applies Ports
Port Lines
Input Register Read Port Internal Timing
Input Buffer
Handshake Selected Write Port Handshake Handshake Logic Logic RDY//DAV /DAV/RDY
Output Register
Output Buffer
Output Enable Internal
Figure 5-2. Ports Generic Block Diagram
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Microcontrollers Ports
5.2.1 General Mode
Port 8-bit, bidirectional, CMOS compatible port. These eight lines configured under software control nibble port (P03-P00 input/output P07-P04 input/output), address port interfacing external memory. input buffers Schmitttriggered, level shifted, single-trip point buffer nibble programmed. Either nibble output globally programmed push-pull open-drain. output buffers some cases globally programmed software, program option, mask option. some, Auto Latches hardwired inputs. Please refer specific product specifications exact input/output buffer type features that available (Figures 5-4).
Port (I/O AD15 AD08) Handshake Controls /DAV0 RDY0 (P32 P35)
OPEN-DRAIN
2.3V Hysteresis
Auto Latch
Figure 5-3. Port Configuration with Open-Drain Capability, Auto Latch, Schmitt-Trigger
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PORT (Continued)
Level Shifter
Figure 5-4. Port Configuration with Level Shifter
5.2.2 Read/Write Operations
nibble Mode, Port accessed general-purpose register (00H) with Bank port written specifying instruction's destination register. Writing port causes data stored port's output register. port read specifying source register instruction. When output nibble read, data external pins returned. Under normal loading conditions this equivalent reading output register. However, Port outputs defined open-drain, data returned value forced output external system. This same data output register. Reading nibble defined input also returns data external pins. However, input bits under handshake control return data latched into input register input strobe.
Port Mode resister bits D1D0 D7D6 used configure Port nibbles. lower nibble (P00-P03) defined inputs setting bits outputs setting both Likewise, upper nibble (P04-P07) defined inputs setting bits outputs setting both (Figure 5-5).
5.2.3 Handshake Operation
When used port, Port placed under handshake control programming Port Mode register this configuration, handshake control lines DAV0 (P32) RDY0 (P35) when Port input port, RDY0 (P32) DAV0 (P35) when Port output port. (See Figure 5-6) Handshake direction determined configuration (input output) assigned Port upper nibble, P04-P07. lower nibble must have same configuration upper nibble under handshake control. Figure illustrates Port upper lower nibbles associated handshake lines Port
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Microcontrollers Ports
PORT
This section deals only with operation. port's external memory interface operation discussed later this manual. Figure shows block diagram Port
Register (P01M) Port Mode Register (P01M) (Write-Only) Mode Output Input Mode Output Input
5.3.1 General Mode
Port 8-bit, bidirectional, CMOS compatible port with multiplexed Address (A7-A0) Data (D7-D0) ports. These eight lines byte programmed inputs outputs configured under software control Address/Data port interfacing external memory. input buffers Schmitt-triggered, level- shifted, single-point buffer. some cases, output buffers globally programmed either push-pull open-drain. Low-EMI output buffers globally programmed software, program option, Mask Option. some cases, Z8can have auto latches hardwired inputs. Please refer specific product specifications exact input/output buffer-type features available (Figures 5-8).
Figure 5-5. Port Operation
Register Port Mode Register (P3M) (Write-Only) Input Output DAV0/RDY0 RDY0/DAV0
Figure 5-6. Port Handshake Operation
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PORT (Continued)
Port (I/O AD0)
Handshake Controls /DAV1 RDY1 (P33 P34)
OPEN-DRAIN
2.3V Hysteresis
Auto Latch
Figure 5-7. Port Configuration with Open-Drain Capability, Auto Latch, Schmitt-Trigger
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Microcontrollers Ports
Port (I/O AD0)
Handshake Controls DAV1 RDY1 (P33 P34)
Level Shifter
Figure 5-8. Port Configuration with Level Shifter
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ZiLOG
5.3.2 Read/Write Operations
byte input byte output mode, port accessed General-Purpose Register (01H). port written specifying instruction's destination register. Writing port causes data stored port's output register. port read specifying source register instruction. When output read, data external pins returned. Under normal loading conditions, this equivalent reading output register. However, Port outputs defined open-drain, data returned value forced output external system. This same data output register. When Port defined input, reading also returns data external pins. However, inputs under handshake control return data latched into input register input strobe. Using Port Mode Register, Port configured output port setting bits input port setting (Figure 5-8).
R248 P01M Port Mode Register (F8, Write-Only)
5.3.3 Handshake Operations
When used port, Port placed under handshake control programming Port Mode register bits both this configuration, handshake control lines DAV1 (P33) RDY1 (P34) when Port input port, RDY1 (P33) DAV1 (P34) when Port output port. Figures 5-10. Handshake direction determined configuration (input output) assigned Port example, Port output port then handshake defined output.
R247 Port Mode Register (F7, Write-Only)
Input Input Input DAV1/RDY1 Output RDY1/DAV1
Figure 5-10. Handshake Operation
Mode Byte Output Byte Output AD0-AD7 High Impedance AD0- AD7, R/W, A11,
Figure 5-9. Port Operation
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Microcontrollers Ports
PORT
Port general-purpose port. Figure shows block diagram Port Each lines independently programmed input output Port Mode Register (F6H) seen Figure 5-11. configures corresponding Port input, while configures output line.
Register Port Mode Register (P2M) (Write-Only) Port Mode Output Input
Figure 5-11. Port Mode Configuration
OPEN-DRAIN P21-P26 P21-P26
P21-P26 P21-P26 2.3V Hysteresis 5.0V
Auto Latch
Figure 5-12. Port Configuration with Open-Drain Capability, Auto Latch, Schmitt-Trigger
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ZiLOG
PORT (Continued)
Open-Drain
Level Shifter
Figure 5-13. Port Configuration with Level Shifter
5-10
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Microcontrollers Ports
OPEN-DRAIN
Auto Latch OPEN-DRAIN Standard Active Standard
SCON Enable *SPI must enabled with
Auto Latch
Figure 5-14. Port Configuration with Open-Drain Capability, Auto Latch, Schmitt-Trigger
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5-11
Microcontrollers Ports
ZiLOG returned. Under normal loading conditions, this equivalent reading output register. However, Port defined open-drain output, data returned value forced output external system. This same data output register. Reading input bits Port also returns data external pins. However, inputs under handshake control return data latched into input register input strobe.
5.4.2 Read/Write Operations
Port accessed General-Purpose Register (02H). Port written specifying instruction's destination register. Writing Port causes data stored output register Port reflected externally configured output. Port read specifying source register instruction. When output read, data external
5.4.3 Handshake Operation
Port placed under handshake control programming Port Mode Register (Figure 5-15). this configuration, Port lines used handshake control lines DAV2 RDY2 input handshake, RDY2 DAV2 output handshake.
Handshake direction determined configuration (input output) assigned Port Only those bits with same configuration will under handshake control. Figure 5-16 illustrates lines Port associated handshake lines Port
Register Port Mode Register (Write-Only) Port Handshaking Input (TIN) DAV2/RDY2
Output (TOUT) RDY2/DAV2
Figure 5-15. Port Handshake Configuration
Port (I/O)
Handshake Controls DAV2 RDY2 (P31 P36)
Figure 5-16. Port Handshaking
5-12
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Microcontrollers Ports
PORT 5.5.1 General Port
Port differs structurally from Port Port lines fixed four inputs (P33-P30) four outputs (P37-P34) Port does have input output register each bit. Instead, input lines have input register, output lines have output register. Port CMOS- TTL- compatible port. Under software control, lines configured special control lines handshake, comparator inputs, control, external memory status, lines on-board serial timer facilities. Figure 5-17 generic block diagram Port inputs Schmitt-triggered, level-shifted, single-trip point buffered. some cases, have auto latches hardwired certain Port inputs LowEMI capabilities outputs. Please refer specific product specifications exact input/output buffer type features. Please refer section counter/timers, Stop-Mode Recovery, serial I/O, comparators, interrupts more information relationships Port that feature.
Read Port Input Register Input Input Buffer Buffer
Port Input Lines
Interrupt Timer, Handshake Logic, Serial
Read Port
Output Data Return Buffer
Write Port Port Output Lines
Output Output Register Register Register
Output Output Buffer Buffer
Internal
From Timer, Handshake Logic, Serial
Figure 5-17. Port Block Diagram
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Microcontrollers Ports
ZiLOG
PORT (Continued)
Port (I/O Control)
Auto Latch
R247 Analog Digital Data Latch IRQ3
DIG. (AN1) IRQ2, TIN, Data Latch
(AN2) (REF)
IRQ0, Data Latch
From Stop-Mode Recovery Source
IRQ1, Data Latch
Figure 5-18. Port Configuration with Comparator, Auto Latch, Schmitt-Trigger
5-14
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(P33)
(P33)
PCON P34, Standard Output P34, Comparator Output
Figure 5-19. Port Configuration with Comparator
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5-15
Microcontrollers Ports
ZiLOG
PORT (Continued)
MSTR
MSTR
PCON P34, Standard Output P34, Comparator Output
Figure 5-20. Port Configuration with Comparator Outputs Using
5-16
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Port Output Configuration
Level Shifter Port Input Configuration
Auto Latch
Figure 5-21. Port Configuration with Level Shifter Auto Latch
5.5.2 Read/Write Operations
Port accessed General-Purpose Register (03H). Port written specifying instruction's destination register. However, Port outputs cannot written they used special functions. When writing Port data stored output register. Port read specifying source register instruction. When reading from Port data returned both data input pins output register.
5.5.3 Special Functions
Special functions Port defined programming Port Mode Register. writing through lines P37-P30 configured input/output pairs (Figure 5-22). Table shows available functions Port special functions indicated figure discussed detail their corresponding sections this manual. Port input lines P33-P30 always function interrupt requests regardless configuration specified Port Mode Register.
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5-17
Microcontrollers Ports
ZiLOG
Register Port Mode Register (Write-Only) Port Open-Drain Port Push-Pull P31, Digital Mode P31, Analog Mode Input Input Input Input Input Input Serial Party Party Output Output Output Output Serial
Figure 5-22. Port Mode Register Configuration Table 5-1. Port Line Functions Function Inputs Line Signal Input Input Input Input Output Output Output Output DAV0/RDY0 DAV1/RDY1 DAV2/RDY2 RDY0/DAV0 RDY1/DAV1 RDY2/DAV2 AN1-OUT AN2-OUT AN2-OUT Function Interrupt Requests Table 5-1. Port Line Functions Line External Memory Status Signal IRQ3 IRQ2 IRQ0 IRQ1 TOUT
Outputs
Port Handshake Input Port Handshake Input Port Handshake Input Port Handshake Output Port Handshake Output Port Handshake Output Analog Comparator Input
Serial Input (UART) Serial Output (UART) Slave Select Clock Counter/Timer
Analog Comparator Output
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Microcontrollers Ports
PORT HANDSHAKE
When Ports configured handshake operation, pair lines from Port used handshake controls. handshake controls interlocked properly time asynchronous data transfers between peripheral. control line (/DAV) functions strobe from sender indicate receiver that data available. second control line (RDY) acknowledges receipt sender's data, indicates when receiver ready accept another data transfer. input mode, data latched into Port's input register first /DAV signal, protected from being overwritten additional pulses occur /DAV line. This overwrite protection maintained until port data read. output mode, data written port protected overwritten during handshake sequence. avoid losing data, software must overwrite port until corresponding interrupt request indicates that external device latched data. software always read Port output input handshake lines, cannot write output handshake line. following recommended setup sequence when configuring Port handshake operation first time after reset: Load P01M configure port input/output. Load Output Handshake logic Load select Handshake Mode port.
Once data transfer begins, configuration handshake lines should changed until handshake completed. Figures 5-23 5-24 show detailed operation handshake sequence.
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Microcontrollers Ports
ZiLOG
PORT HANDSHAKE (Continued)
/DAV (Input
(Output From
Data Port (Input Valid Data
State State State State State
Port output High, indicating that device ready accept data. device puts data port then activates input. This causes data latched into port input register generates interrupt request. forces Ready (RDY) output Low, signaling device that data been latched. device returns line High response going Low. software must respond interrupt request read contents port order handshake sequence completed. line goes High only port been read High. This returns interface initial state.
Figure 5-23. Input Handshake
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ZiLOG
PORT HANDSHAKE (Continued)
(Input
(Output From
Data Port (Output From Valid Data
State State State State State
input High indicating that device ready accept data. Writes port register initiate data transfer. Writing port outputs data forces only High. device forces after latching data. causes interrupt request generated. write data responses going Low; however, data output until State output from driven High response going Low. goes High, device free raise High thus returning interface initial state.
Figure 5-24. Output Handshake
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Microcontrollers Ports applications requiring strobed signal instead interlocked handshake, satisfy this requirement follows: Strobed Input mode, data latched Port input register using input. data transfer rate must allow enough time software read Port before strobing next character. output ignored.
ZiLOG Strobed Output Mode, input should tied output.
Figures 5-25 5-26 illustrate strobed handshake connections.
P20-
Device
Figure 5-25. Output Strobed Handshake Port
P20- Device
Figure 5-26. Input Strobed Handshake Port
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Microcontrollers Ports
PORT RESET CONDITIONS 5.7.1 Full Reset
After hardware reset, Watch-Dog Timer (WDT) reset, Power-On Reset (POR), Port Mode Registers P01M, P2M, shown Figures 5-27 through 5-22. Port configured input operation bits open-drain (Figure 5-29). push-pull outputs desired Port outputs, remember configure them using P3M. Please note that time-out from StopMode Recovery does full reset. Certain registers that reset after Stop-Mode Recovery will reset. condition Ports after Stop-Mode Recovery, please refer specific device product specifications. some cases, P01M, P2M, control register back default condition after reset while others not. special functions Port inactive, with P33-P30 inputs P37-P34 outputs (Figure 5-29). Note: Because types amounts vary greatly among family devices, user advised review selected device's product specifications register default state after reset.
Register Port Mode Register (P01M) (Write-Only) Mode Output Input Stack Selection External Internal Mode Byte Output Byte Output High Impedance AD7, A15, External Memory Timing Normal Extended Mode Output Input
Figure 5-27. Port Reset
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ZiLOG
Register Port Mode Register (P2M) (Write-Only) Port Mode Output Input
Figure 5-28. Port Reset
Register Port Mode Register (P3M) (Write-Only) Port Open-Drain Port Push-Pull P31, Digital Mode P31, Analog Mode Input DAV0/RDY0 Input Input Input DAV1/RDY1 Output RDY0/DAV0 Output RDY1/DAV1 Output RDY2/DAV2 Output Serial
Input DAV2/RDY2 Input Serial Parity Parity
Figure 5-29. Port Mode Reset
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ZiLOG
ANALOG COMPARATORS (Continued) ANALOG COMPARATORS
Select devices include independent on-chip analog comparators. device product specification feature availability use. Port Pins each have comparator front end. comparator reference voltage, P33, common both comparators. Analog Mode, positive inputs comparators reference voltage supplied both comparators. Digital Mode, used register input IRQ1 source. P34, P35, output comparator outputs software-programming PCON Register
5.8.1 Comparator Description
on-board comparators process analog signals with reference voltage P33. analog function enabled programming Port Mode Register (P3M interrupt functions during analog mode, programmable rising, falling, both edge triggered interrupts (IRQ register bits Note: cannot generate external interrupt while this mode. only generate interrupts Digital Mode. Note: Port inputs must digital mode Port Stop-Mode Recovery source. analog comparator disabled STOP mode. used Analog Digital Modes, must referenced P33, when Analog Mode.
Register Port Mode Register (P3M) (Write-Only) Digital Mode P31, P32, Analog Mode P31, P32,
Figure 5-30. Port Input Analog Selection
Bank Register Port Configuration Register (PCON) (Write-Only) P34, P35, Standard Outputs P34, P35, Comparator Outputs
Figure 5-31. Port Comparator Output Selection
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Port (I/O Control)
Auto Latch
R247 Analog Digital Data Latch IRQ3
DIG. (AN1) IRQ2, TIN, Data Latch
(AN2) (REF)
IRQ0, Data Latch
From Stop-Mode Recovery Source
IRQ1, Data Latch
Figure 5-32. Port Configuration Comparator Inputs P31, P32,
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Microcontrollers Ports
(P33)
(P33) PCON P34, Standard Output P34, Comparator Output
Figure 5-33. Port Configuration
5.8.2 Comparator Programming
Example enabling analog comparator mode. P3M, #XXXX XX1XB Note: Binary Number
Example enabling analog comparator output. #%0FH ;Sets register pointer ;working register group ;and Expanded Register ;File Bank ;Enables comparator ;outputs using PCON ;Register programming.
#XXXX XXX1B
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ZiLOG 5.8.5.2 VOFFSET absolute value voltage between positive input reference input required make comparator output voltage switch input offset voltage (VOFFSET). 3.000V 3.001V when comparator output switches states then Voffset 1mV. 5.8.5.3 CMOS voltage comparator inputs, input offset current (IIO) leakage current CMOS input gate.
5.8.3 COMPARATOR OPERATION
After enabling Analog Comparator mode, becomes common reference input both comparators. (Ref) hard wired reference inputs both comparators cannot separated. always connected positive inputs comparators. positive input comparator while positive input comparator AN2. outputs comparators AN1-out AN2-out, respectively. comparator output reflects relationship between positive input reference input. Example: voltage higher than voltage then AN1-out will high state. voltage lower than voltage then AN2-out will state. this example, when Port register read, Bits comparator outputs enabled come P37, then Please note that previous data stored disturbed. Once comparator outputs de-selected stored values register bits will reflected these pins again.
5.8.6 Mode
available interrupt input during Analog Mode. valid interrupt inputs conjunction with (Ref) when Analog Mode. still used when analog mode selected. comparator outputs desired outputted Port outputs, please refer specific products specification priority mixing when other special features sharing those same Port pins.
5.8.7 HALT Mode
analog comparators functional during HALT Mode Analog Mode been enabled. P32, conjunction with (Ref) will able generate interrupts. Only cannot generate interrupt since input goes directly input comparators disconnected from interrupt sensing circuits.
5.8.4 Interrupts
example from Section 5.8.3, (AN2) will generate interrupt based result comparison being Interrupt Request Register (IRQ FAH) having bits D7=0 D6=0. D7=1 D6=0 then both would generate interrupts.
5.8.8 STOP Mode
analog comparators disabled during STOP Mode does current that time. P31, P32, used source Stop-Mode Recovery, Port Digital Mode must selected setting D1=0 Port Mode Register. Otherwise STOP Mode, P31, P32, cannot sensed. Analog Mode selected when entering STOP Mode, will still enabled after valid triggered reset.
5.8.5 Comparator Definitions
5.8.5.1 VICR usable voltage range both positive inputs reference input called common mode voltage range (VICR). comparator guaranteed work inputs outside VICR range.
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Microcontrollers Ports Port Open-Drain (D1). Port configured opendrain resetting this (D1=0) configured push-pull active setting this (D1=1). default value Port Open Drain (D2). Port configured opendrain resetting this (D2=0) configured push-pull active setting this (D2=1). default value
OPEN-DRAIN CONFIGURATION
configure Port provide open-drain outputs programming Port Mode Register (P3M) D0=0.
Register Port Mode Register (Write-Only)
Port Configuration Pull-Ups Open-Drain Pull-Ups Active
5.10 EMISSION
Some programmed operate Emission Mode using Port configuration register (PCON). PCON register allows oscillator ports programmed Low-EMI Mode independently. Other offer Mask programming option configure Ports oscillator globally Low-EMI mode (where XTAL frequency equal internal system clock frequency. feature results
Comparator Output Port P34, Standard Output* P34, Comparator Output Port Open Drain Port Push-pull Active Port Open Drain Port Push-pull Active Port Port Standard Port Port Standard Port Port Standard Port Port Standard Oscillator Standard
Figure 5-34. Port Configuration Other that have Port Configuration Register (PCON) that configure Port Port provide open-drain outputs. PCON Register located Expanded Register File (ERF) Bank Register 00H. Figure 5-35.
PCON (FH)
output pre-drivers slew rate reduced (typical). output drivers have resistance Ohms (typical). Oscillator. output drivers approximately percent standard drive. Internal SCLK/TCLK XTAL operation limited maximum cycle time, when Oscillator selected system clock (SCLK=XTAL, Reg. D1=1).
Default Setting After RESET
Figure 5-35. Port Configuration Register (PCON) (Write-Only)
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Microcontrollers Ports having PCON register feature, following bits control options: Port (D3). Port configured Port resetting this (D3=0) configured Standard Port setting this (D3=1). default value Port (D4). Port configured Port resetting this (D4=0) configured Standard Port setting this (D4=1). default value Port (D5). Port configured Port resetting this (D5=0) configured Standard Port setting this (D5=1). default value Port (D6). Port configured Port resetting this (D6=0) configured
ZiLOG Standard Port setting this (D6=1). default value (D7). This PCON Register controls oscillator. this location configures oscillator with standard drive, while configures oscillator with noise drive. LowEMI mode will reduce drive oscillator (OSC). default value XTAL/2 mode effected this bit.
Note: maximum external clock frequency when running oscillator mode. Please refer selected device product specification availability feature programming options.
5.11 INPUT PROTECTION
CMOS have pins with diode input protection. There diode from VSS. Figure 5-36. CMOS EPROM Z8s, Port inputs P31, P32, XTAL have only input protection diode from VSS. Figure 5-37.
Figure 5-37. Diode Input Protection high-side input protection diodes were removed these pins allow application +12.5V during various programming modes. better noise immunity applications that exposed system EMI, clamping diode from these pins required prevent entering programming mode prevent high voltage from damaging these pins.
Figure 5-36. Diode Input Protection
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Microcontrollers Ports
5.12 CMOS AUTO LATCHES
port bits that configurable inputs protected against open circuit conditions using Auto Latches. Auto Latch circuit which, event open circuit condition, latches input valid CMOS level. This inhibits tendency input transistors self-bias forward active region, thus drawing excessive supply current. simplified schematic CMOS circuit shown Figure 5-38.
Open-Drain
Data
Data Auto Latch
Figure 5-38. Simplified CMOS Circuit
operation Auto Latch circuit straight-forward. Assume input latched (logic inverter inverts bit, turning P-channel N-channel OFF. output circuit effectively shorted VDD, returning input. then disconnected from source, Auto Latch will hold input previous state. device powered with input floating, state Auto Latch will either supply, which state unpredictable. There four operating conditions which will activate Auto Latches. first, which occurs when input physically disconnected from source, most obvious. second occurs when input connected output device with tri-state capability.
Auto Latch will also activate when input voltage within microvolts either supply rail. this case, circuit will draw current, which significant compared operating current device, will increase ICC2 STOP Mode current device dramatically. fourth condition occurs when configured output. Referring output section Figure 538, there ways tri-stating port pin. first configuring port input, which disables signal turning both transistors off. second achieved output mode writing output port, then activating open drain mode. Both transistors again off, port high impedance state. Auto Latches then pull input section toward VDD.
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Auto Latch Model:
Auto Latch's equivalent circuit shown Figure 5-39. When input high, circuit consists resistance from (the P-channel transistor state) much greater resistance GND. Current flows from output. When input low, circuit modeled resistance from (the N-channel transistor state) much greater resistance VDD. Current flows from input ground. Auto Latch characterized with respect Iao, equivalent resistance calculated according (VDD-VIN)/IAO. worst case equivalent resistance (min) calculated worst case input voltage, VIH(min).
Data Logic
Data Logic
Figure 5-39. Auto Latch Equivalent Circuit
Design Considerations:
circuits which Auto Latch active, consideration should given loading constraints Auto Latches. example, with weak values VIN, close (min) (max), pullup pull-down resistances must calculated using R/Rp. best case STOP mode operation, inputs should within supply rails. output mode, port forced into tri-state condition, Auto Latches will force VDD. there external pulldown resistor pin, voltage switch Auto Latch. shown Figure 5-40, equivalent resistance Auto Latch external pulldown form voltage divider, external resistor large, voltage developed across will exceed Vil(max). worst case: VIL(max [Rext/(Rext+Rp)] Rext(max) 5.0V have Vih(max) =0.8V: REXT(max) (0.16/1M)/(1-0.16) ohms. increases rapidly with VDD, increased will relax requirement Rext. Figure 5-40. Effect Pulldown Resistors Auto Latches summary, CMOS Auto Latch inhibits excessive current drain devices latching open input either GND. effect Auto Latch characteristics device modeled current resistor whose value VDD/Iao.
(min.) REXT
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CHAPTER
COUNTER/TIMERS
INTRODUCTION
MCU® provides 8-bit counter/timers, each driven 6-bit prescaler, PRE0 PRE1 (Figure 6-1). Both counter/timers independent processor instruction sequence, that relieves software from time-critical operations such interval timing event counting. Some MCUs offer clock scaling using register. device product specification clock available options. following description typical. Each counter/timer operates either Single-Pass Continuous mode. end-of-count, counting either stops initial value reloaded counting continues. Under software control, values loaded immediately when end-of-count reached. Software also controls counting mode, counter/timer started stopped, lines. Both counter prescaler registers altered while counter/timer running.
Write (SMR) PRE0 Initial Value Register
Internal Data Write Initial Value Register Read Current Value Register
(SMR)
6-Bit Down Counter
8-Bit Down Counter
IRQ4
Internal Clock 6-Bit Down Counter 8-Bit Down Counter
TOUT IRQ5
Clock Logic
External Clock
Internal Clock Gated Clock Triggered Clock Write
PRE1 Initial Value Register Write
Initial Value Register Read
Current Value Register
Internal Data
Figure 6-1. Counter/Timer Block Diagram
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Microcontrollers Counter/Timers Counter/timers driven timer clock generated dividing internal clock four. divide-byfour stage, 6-bit prescaler, 8-bit counter/timer form synchronous 16-bit divide chain. Counter/timer also driven external input (TIN) using P31. Port line serve timer output (TOUT) through which internal clock output. timer output will toggle end-of-count. counter/timer, prescaler, associated mode registers mapped into register file shown Figure This allows software treat counter/timers general-purpose registers, eliminates need special instructions.
ZiLOG
R245 PRE0 Prescaler Register (%F5; Write-Only) Count Mode Single Pass Modulo-n Reserved (Must Prescaler Modulo (Range: 1-64 Decimal 01-00 HEX)
PRESCALERS COUNTER/TIMERS
prescalers, PRE0 (F5H) PRE1 (F3H), each consist 8-bit register 6-bit down-counter shown Figure 6-1. prescaler registers write-only registers. Reading prescalers returns value FFH. Figures show prescaler registers. most significant bits (D2-D7) PRE0 PRE1 hold prescalers count modulo, value from decimal. prescaler registers also contain control bits that specify counting modes. These bits also indicate whether clock source internal external. These control bits will discussed detail throughout this chapter. counter/timer registers, (F4H) (F2H), each consist 8-bit down-counter, write-only register that holds initial count value, read-only register that holds current count value (Figure 6-1). initial value range from decimal (01H,02H,.,00H). Figure illustrates counter/timer registers.
Figure 6-3. Prescaler Register
R243 PRE1 Prescaler Register (%F3; Write-Only) Count Mode Single Pass Modulo-n Clock Source Internal External (TIN) Prescaler Modulo (Range: 1-64 Decimal 01-00 HEX)
Figure 6-4. Prescaler Register
Port Mode Identifiers R242 Counter/Timer Register (%F2; Write/Read Only) R244 Counter/Timer Register (%F4; Write/Read Only) Initial value when written (Range 1-256 decimal, 01-00 HEX) current value when read
Prescaler Timer/Counter0 Prescaler Time/Counter1 Timer Mode
Figure 6-5. Counter Timer Registers Figure 6-2. Counter/Timer Register
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Microcontrollers Counter/Timers
COUNTER/TIMER OPERATION
Under software control, counter/timers started stopped Timer Mode Register (TMR,F1H) bits D0D3 (Figure 6-6). Each counter/timer associated with Load Enable Count bit. counter timers remain rest long Enable Count bits enable counting, Enable Count must Counting actually starts when Enable Count written instruction. first decrement occurs four internal clock periods after Enable Count been set. configured external clock, first decrement begins next clock period. Load Enable Count bits same time. example, using instruction: TMR,#03H sets both TMR. This loads initial values PRE0 into their respective counters starts count after M2T2 machine state after operand fetched (Figure 6-7).
6.3.1 Load Enable Count Bits
Setting Load transfers initial value prescaler counter/timer registers into their respective down-counters. next internal clock resets bits readying Load next load operation. values loaded into down-counters time. counter/timer running, continues starts count over with value. Therefore, Load actually functions software re-trigger.
R241 Timer Mode Register Read/Write) Function Load Disable Count Enable Count Function Load Disable Count Enable Count
R243 PRE1 Prescaler Register Write-Only) R245 PRE0 Prescaler Register Write-Only) Count Mode Single Pass Modulo-n
Figure 6-7. Starting Count Figure 6-6. Timer Mode Register
First Decrement Occurs Four Clock Periods Later Written, Counter/Timer Loaded #03H Fetched
Figure 6-8. Counting Modes
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6.3.2 Prescaler Operations
During counting, programmed clock source drives 6-bit Prescaler Counter. counter counted down from value specified bits corresponding Prescaler Register, PRE0 (bit PRE1 (bit (Figures 6-3, 6-4). When Prescaler Counter reaches end-of-count, initial value reloaded counting continues. prescaler never actually reaches example, prescaler divide-by-three, count sequence 3-2-1-3-2-1-3-2-1-3. Each time prescaler reaches count carry generated, that allows Counter/Timer decrement next timer clock input. When Counter/Timer prescaler both reach end-of-count, interrupt request generated (IRQ4 IRQ5 T1). Depending counting mode selected, Counter/Timer will either come rest with value (Single-Pass Mode) initial value will automatically reloaded counting will continue (Continuous Mode). counting modes controlled PRE0 PRE1. (Figure 6-8). written this configures counter Single-pass counting mode, while written this configures counter Continuous mode. Counter/Timer stopped time setting Enable Count restarted setting back Counter/Timer will continue count value time stopped. current value Counter/Timer read time without affecting counting operation. Note: prescaler registers write-only cannot read. initial values written prescaler Counter/Timer registers time. These values will transferred their respective down counters next load operation. Counter/Timer mode continuous, next load occurs timer clock following end-ofcount. initial values should written before desired load operation, since prescalers always effectively operate Continuous count mode. time interval until end-of-count, given equation: =tXpXv which: four times internal clock period. internal clock frequency defaults external clock source (XTAL, ceramic resonator, others) divided Some microcontrollers allow this divisor changed Stop-Mode Recovery register. product data sheet available clock divisor options. Note that equal eight divided-by-XTAL frequency external clock source (external clock mode only). prescaler value minimum prescaler count achieved loading 000001xx. maximum prescaler count achieved loading 111111xx. Counter/Timer value (1-256) Minimum duration achieved loading prescaler output count), maximum duration achieved loading (256 prescaler outputs counts). prescaler counter/timer true divide-by-n counters.
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Microcontrollers Counter/Timers
TOUT MODES
Timer Mode Register (F1H) (Figure 6-9), used conjunction with Port Mode Register (F7H) (Figure 6-10) configure TOUT operation order TOUT function, must defined output line setting Output controlled counter/timers internal clock.
Register F1HR Timer Mode Register (TMR) (Read/Write) Function Load Disable Count Enable Count TOUT Modes: TOUT T1OUT Internal Clock
Figure 6-9. Timer Mode Register (TOUT Operation)
Register Port Mode Register (P3M) (Write-Only) Input (TIN) DAV2/RDY2 Output (TOUT) RDY2/DAV2
Figure 6-10. Port Mode Register (TOUT Operation)
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TOUT MODES (Continued)
counter/timer output selected selected drive TOUT line setting Likewise, selected setting respectively. counter/timer TOUT mode turned setting both freeing data output line. TOUT initialized logic whenever Load (bit TOUT configuration timer load, Timer Enable Count bits counter/timer driving TOUT same time. example, using instruction: TMR,#43H Configures drive TOUT (P36). Sets TOUT logic level. Loads initial PRE0 levels into their respective counters starts counter after M2T2 machine state after operand fetched. end-of-count, interrupt request line (IRQ4 IRQ5), clocks toggle flip-flop. output this flip-flop drives TOUT line, P36. cases, when selected counter/timer reaches end-of-count, TOUT toggles opposite state (Figure 6-11). example, counter/timer Continuous Counting Mode, Tout will have percent duty cycle output. This duty cycle easily controlled varying initial values after each end-of-count. internal clock selected output instead setting both internal clock (XTAL frequency/2) then directly output (Figure 6-12). While programmed TOUT, cannot modified write port register However, software examine current output reading port register.
IRQ4 End-of-Count)
IRQ5 End-of-Count)
TOUT
Figure 6-11. Output Through TOUT
Internal Clock
TOUT
Figure 6-12. Internal Clock Output Through TOUT
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Microcontrollers Counter/Timers
MODES
Timer Mode Register (F1H) (Figure 6-13) used conjunction with Prescaler Register PRE1 (F3H) (Figure 6-14) configure TIN. used conjunction with four modes: External Clock Input Gated Internal Clock Triggered Internal Clock Retriggerable Internal Clock counter/timer clock source must configured external setting PRE1 Register Timer Mode Register then used select desired operation. start counting result input, Enable Count (bit TMR) must When using external clock gate input, initial values must loaded into down counters setting Load (bit TMR) before counting begins. descriptions that follow, assumed programmer performed these operations. Initial values automatically loaded Trigger Retrigger modes software loading unnecessary.
Note: mode restricted with timer only. enable mode selected (via bits PRE1 must
Register Timer Mode Register (TMR) (Read/Write) Modes: External Clock Input Gate Input Trigger Input (Non-retriggerable) Trigger Input (Retriggerable)
Figure 6-13. Timer Mode Register (TIN Operation)
Register Prescaler Register (PRE1) (Write-Only) Clock Source External Enable Mode Internal Disable Mode
Figure 6-14. Prescaler Register (TIN Operation)
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Microcontrollers Counter/Timers suggested that configured input line setting Register although still functional configured handshake input. Each High-to-Low transition generates interrupt request IRQ2, regardless selected mode
ZiLOG enabled/disabled state IRQ2 must therefore masked enabled according needs application.
6.5.1 External Clock Input Mode
External Clock Input Mode (TMR both supports counting external events, where event considered High-to-Low transition (Figure 6-15). Note: product data sheet minimum allowed external clock input period TIN).
IRQ5 PRE1
Clock
Internal Clock
IRQ2
Figure 6-15. External Clock Input Mode
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Microcontrollers Counter/Timers
6.5.2 Gated Internal Clock Mode
Gated Internal Clock Mode (TMR respectively) measures duration external event. this mode, prescaler driven internal timer clock, gated High level (Figure 616). counts while High stops counting while Low. Interrupt request IRQ2 generated High-to-Low transition signalling gate input. Interrupt request IRQ5 generated reaches end-of-count.
Internal Clock
PRE1
IRQ5
Gate
IRQ2
Figure 6-16. Gated Clock Input Mode
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6.5.3 Triggered Input Mode
Triggered Input Mode (TMR bits respectively) causes start counting result external event (Figure 6-17). then loaded clocked internal timer clock following first High-to-Low transition input. Subsequent transitions affect Single-Pass Mode, Enable reset whenever reaches end-of-count. Further transitions will have effect until software sets Enable Count again. Continuous mode, once triggered counting continues until software resets Enable Count bit. Interrupt request IRQ5 generated when reaches end-of-count.
Internal Clock
Edge Trigger Trigger
PRE1
IRQ5
IRQ2
Figure 6-17. Triggered Clock Mode
6-10
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Microcontrollers Counter/Timers
6.5.4 Retriggerable Input Mode
Retriggerable Input Mode (TMR bits causes load start counting every occurrence High-to-Low transition (Figure 6-17). Interrupt request IRQ5 will generated programmed time interval (determined prescaler counter/timer register initial values) elapsed since last High-to-Low transition TIN. Single-Pass Mode, end-of-count resets Enable Count bit. Subsequent transitions will cause load start counting until software sets Enable Count again. Continuous Mode, counting continues once triggered until software resets Enable Count bit. When enabled, each High-to-Low transition causes reload restart counting. Interrupt request IRQ5 generated every end-of-count.
CASCADING COUNTER/TIMERS
some applications, necessary measure time interval greater than single counter/timer measure. this case, TOUT used cascade single unit (Figure 6-18). should configured operate Continuous mode drive TOUT. should configured external clock input wired back TOUT. every other end-of-count, TOUT undergoes High-to-Low transition that causes count. operate either Single-Pass Continuous mode. When end-of-count reached, interrupt request IRQ5 generated. Interrupt requests IRQ2 (TIN High-toLow transitions) IRQ4 end-of-count) also generated most likely importance this configuration should disabled.
PRE0
TOUT
PRE1
IRQ5
IRQ4
IRQ2
Figure 6-18. Cascaded Counter Timers
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Microcontrollers Counter/Timers
ZiLOG
RESET CONDITIONS
After hardware reset, counter/timers disabled contents counter/timer prescaler registers undefined. However, counting modes configured Single-Pass clock source external.
R242 Counter/Timer Register (%F2; Write/Read Only) R244 Counter/Timer Register (%F4; Write/Read Only) R245 PRE0 Prescaler Register (%F5; Write-Only) Count Mode Single Pass Modulo-n Reserved (Must Prescaler Modulo (Range: 1-64 Decimal 01-00 HEX)
Initial value when written (Range 1-256 decimal, 01-00 HEX) current value when read
Figure 6-21. Prescaler Reset
Figure 6-19. Counter Timer Reset External Clock mode, TOUT mode off. Figures 6-19 through 6-22 show binary reset values Prescaler, Counter/Timer, Timer Mode registers.
R241 Timer Mode Register Read/Write) Function Load Disable Count Enable Count
R243 PRE1 Prescaler Register (%F3; Write-Only) Count Mode Single Pass Modulo-n Clock Source Internal External (TIN) Prescaler Modulo (Range: 1-64 Decimal 01-00 HEX)
Function Load Disable Count Enable Count Modes: External Clock Input Gate Input Trigger Input (Non-retriggerable) Trigger Input (Retriggerable) TOUT Modes: TOUT T1OUT Internal Clock
Figure 6-20. Prescaler Register Reset
Figure 6-22. Timer Mode Register Reset
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CHAPTER
INTERRUPTS
INTRODUCTION
MCU® allows different interrupts from variety sources; four external inputs, on-chip Counter/Timer(s), software, serial peripherals. These interrupts masked their priorities using Interrupt Mask Interrupt Priority Registers. interrupts globally disabled resetting master Interrupt Enable, Interrupt Mask Register, with Disable Interrupt (DI) instruction. Interrupts globally enabled setting with Enable Interrupt (EI) instruction. There three interrupt control registers: Interrupt Request Register (IRQ), Interrupt Mask register (IMR), Interrupt Priority Register (IPR). Figure shows addresses identifiers interrupt control registers. Figure block diagram showing Interrupt Mask Interrupt Priority logic. family supports both vectored polled interrupt handling. Details vectored polled interrupts found later this chapter.
Register
Identifier
IRQ0 IRQ5
Interrupt Mask Interrupt Request Interrupt Priority Global Interrupt Enable
Figure 7-1. Interrupt Control Registers
Interrupt Request Priority Logic
Vector Select
Figure 7-2. Interrupt Block Diagram Note: selected MCU's product specification exact interrupt sources supported.
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ZiLOG
INTERRUPT SOURCES
Table presents interrupt types, sources, vectors available family processors. Table 7-1. Interrupt Types, Sources, Vectors Name IRQ0 IRQ1 IRQ2 Sources DAV0, IRQ0, Comparator DAV1, IRQ1 DAV2, IRQ2, TIN, Comparator IRQ3 Serial IRQ5 Serial Vector Location 10,11 Comments External (P32), Edge Triggered; Internal External (P33), Edge Triggered; Internal External (P31), Edge Triggered; Internal External (P30) (P32), Edge Triggered; Internal Internal Internal Internal Internal
7.2.1 External Interrupt Sources
External sources involve interrupt request lines IRQ0IRQ3. IRQ0, IRQ1, IRQ2 generated transition corresponding Port (P32, P33, correspond IRQ0, IRQ1, IRQ2, respectively). Figure block diagram interrupt sources IRQ0, IRQ1, IRQ2. Note: interrupt sources trigger conditions device dependent. device product specification determine available sources (internal external), triggering edge options, exact programming details.
Multiple Input Signal Conditioning Circuitry
IRQm 0,1,2
System Clock (Internal)
Figure 7-3. Interrupt Sources IRQ0-IRQ2 Block Diagram
UM001600-Z8X0599
ZiLOG When Port (P31, P32, P33) transitions, first flip-flop set. next flip-flops synchronize request internal clock delay internal clock periods. output last flip-flop (IRQ0, IRQ1, IRQ2) goes corresponding Interrupt Request Register. IRQ3 generated from external source only Serial enabled. Otherwise, source internal. external request generated edge signal shown Figure 7-4. Again, external request synchronized delayed before reaching IRQ3. Some
Microcontrollers Interrupts products replace with external source IRQ3. this case, IRQ3 interrupt generation follows logic illustrated Figure 7-3. Note: Although interrupts edge triggered, minimum interrupt request High times must observed proper operation. device product specification exact timing requirements external interrupt requests (TWIL, TWIH).
P3M6
(IRQ3 Serial
IRQ3 Clock IRQ3 External Source IRQ3 Internal Source Serial Receiver
Figure 7-4. Interrupt Source IRQ3 Block Diagram
7.2.2 Internal Interrupt Sources
Internal sources involve interrupt requests IRQ0, IRQ2, IRQ3, IRQ4, IRQ5. Internal sources ORed with external sources, either internal external source trigger interrupt. Internal interrupt sources trigger conditions device dependent. device product specification determine available sources, triggering edge options, exact programming details. more details internal interrupt sources, refer chapters describing Counter/Timer, ports, Serial I/O.
UM001600-Z8X0599
Microcontrollers Interrupts
ZiLOG
INTERRUPT REQUEST REGISTER LOGIC TIMING
Figure shows logic diagram Interrupt Request (IRQ) Register. leading edge request will first flip-flop, that will remain until interrupt requests sampled. Requests sampled internally during last clock cycle before opcode fetch (Figure 7-6). External requests sampled internal clocks earlier, synchronizing flip-flops shown Figures 7-4. sample time request transferred second flipflop Figure 7-5, that drives interrupt mask priority logic. When interrupt cycle occurs, this flip-flop will reset only highest priority level that enabled. user direct access second flip-flop reading writing Register. read specifying source register instruction written specifying destination register.
IRQ0 IRQ5
Mask Priority Logic
Sample Clock From Priority Logic
Figure 7-5. Register Logic
Interrupt Request Sampled Internally External Interrupt Request Sampled
Figure 7-6. Interrupt Request Timing
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ZiLOG
Microcontrollers Interrupts
INTERRUPT INITIALIZATION
After reset, interrupts disabled must initialized before vectored polled interrupt processing begin. Interrupt Priority Register (IPR), Interrupt Mask Register (IMR), Interrupt Request Register (IRQ) must initialized, that order, start interrupt process. interrupts.) interrupt levels IRQ0-IRQ5 divided into three groups interrupt requests each. group contains IRQ3 IRQ5. second group contains IRQ0 IRQ2, while third group contains IRQ1 IRQ4. Priorities both within between groups shown Tables 7-3. Bits define priority individual members within three groups. Bits encoded define priority orders between three groups. Bits reserved.
7.4.1 Interrupt Priority Register (IPR) Initialization
(Figure 7-7) write-only register that sets priorities vectored interrupts order resolve simultaneous interrupt requests. (There sequence possibilities
Register Interrupt Priority Register (IPR) (Write-Only)
Interrupt Group Priority Bits Priority Reserved C>A>B A>B>C A>C>B B>C>A C>B>A B>A>C Reserved
Group (IRQ1 IRQ4 Priority) IRQ1 IRQ4 IRQ4 IRQ1 Group (IRQ0 IRQ2 Priority) IRQ2 IRQ0 IRQ0 IRQ2 Group (IRQ3 IRQ5 Priority) IRQ5 IRQ3 IRQ3 IRQ5 Reserved (Must
Figure 7-7. Interrupt Priority Register
Table 7-2. Interrupt Priority Group Value Priority Highest IRQ1 IRQ4 IRQ2 IRQ0 IRQ5 IRQ3 Lowest IRQ4 IRQ1 IRQ0 IRQ2 IRQ3 IRQ5
Table 7-3. Interrupt Group Priority Pattern Group Priority High Medium Used Used
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Microcontrollers Interrupts
ZiLOG
INTERRUPT INITIALIZATION (Continued) 7.4.2 Interrupt Mask Register (IMR) Initialization
individually globally enables disables interrupt requests (Figure 7-8). When corresponding interrupt requests enabled. master enable must before individual interrupt requests recognized. Resetting globally disables interrupt requests. reset instructions. automatically reset during interrupt service routine following execution Interrupt Return (IRET) instruction. Note: must reset instruction before contents Interrupt Mask Register Interrupt Priority Register changed except: Immediately after hardware reset. Immediately after executing interrupt service routine before been instruction.
Register Interrupt Request Register (IMR) (Read/Write) Disables IRQ0 Enables IRQ0 Disables IRQ1 Enables IRQ1 Disables IRQ2 Enables IRQ2 Disables IRQ3 Enables IRQ3 Disables IRQ4 Enables IRQ4 Disables IRQ5 Enables IRQ5 Disables Protect Enables Protect Disables Interrupt Enables Interrupt
Figure 7-8. Interrupt Mask Register Note: Protect option selected mask submission time EPROM program time. selected available option, this reserved must
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ZiLOG
Microcontrollers Interrupts
7.4.3 Interrupt Request (IRQ) Register Initialization
(Figure 7-9) read/write register that stores interrupt requests both vectored polled interrupts. When interrupt made six, corresponding position register assigned interrupt requests IRQ0 IRQ5, respectively. Whenever Power-On Reset (POR) executed, resister reset disabled. Before register will accept requests, must enabled executing ENABLE INTERRUPTS (EI) instruction. Note: Setting Global Interrupt Enable Interrupt Mask Register (IMR, will enable IRQ. Execution instruction required (Figure 710). polled processing, must still initialized instruction. pro
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