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Reliability Testing
purpose reliability testing ensure that products properly designed assembled subjecting them stress conditions that accelerate potential failure mechanisms. Reliability test methods defined many industrial standards, such MIL-STD-883, main source methods applied reliability testing Winbond. this report, reliability tests have been divided into three categories: process-related reliability tests, package-related reliability tests, device reliability tests. purpose high-temperature operating life (HTOL) test determine reliability Products accelerating thermally activated failure mechanisms subjecting samples extreme temperatures under biased operating conditions. test used predict long-term failure rates terms FITs (failures time), with representing failure device hours. test samples screened directly after final electrical testing. oven temperature HTOL test Testing performed with dynamic signals applied
Process-Related Reliability Tests
Dynamic Early Fail Study (EFR) purpose dynamic early fail study (EFR) estimate infant mortality failure rate that occurs within first year normal device operation accelerating infant mortality failure mechanisms. Typical stress temperature nominal voltage (6.5 SRAM EPROM; 3.3V SRAM; 3.3V DRAM). duration hours.
vice, typical maximum operating voltage.
High-Temperature Storage Life Test (HTSL) (MIL-STD-883; 1008) high-temperature storage life test measures device resistance high-temperature environment that simulates storage environment. stress temperature accelerate effect temperature test samples. test, voltage bias applied devices
High-Temperature
Operating
Life
Test
(HTOL) (MIL-STD-883; 1005)
Bias Life Test (BLT)
(MIL-STD-883; 1005.8 EIAJ-ED4701-D323) Bias life test detect possible defects passivation (contamination, surface inversion,
Package-Related Reliability Tests
Preconditioning purpose preconditioning measure resistance surface mount devices storage environment customer site thermal stress created reflow vapor phase reflow. Before they undergo temperature-hu-
un-stable characteristics film), junction (junction degradation), oxide film (mobile ions, interface states), bonding (open moralization, bonding defect). test temperature duration 1000 hours. pins devices combination biased.
midity-bias test, temperature cycle test, thermal shock test, pressure cooker test highly-accelerated temperature humidity stress test, surface mount devices subjected preconditioning must then pass final
Electrostatic Discharge (ESD) Test
electrostatic discharge test measures sensitivity each device electrostatic discharges that might occur during handling. Winbond, evaluated using human body model (MIL-STD-883, Method 3015) with through human contact. simulate discharge
electrical test. steps precondition
SRAM,non-volatile logic:
Step1: Temperature Cycle Test (-65 /150
°C), cycles.
Step Bake hours Step Soak hours C/RH60%. (JEDEC LEVEL III) Step Execute (215 Sec. Peak)
Latch-Up Test
latch-up test special test used with CMOS processes detect parasitic bipolar circuits that short power ground nodes when they activated. Winbond adopts JEDEC-JC-78 standards: current applied each steps while power supply current monitored. current into test must rise minimum without latch-up occurring. DRAM
Reflow, passes. Step1: Temperature Cycle Test (-65 /150
°C), cycles.
Step Bake hours Step Soak hours C/RH60%. (JEDEC LEVEL Step Execute Reflow, passes.
Temperature-Humidity-Bias Test (THB) (EIAJ-IC-121-17) temperature-humidity-bias test environmental test designed measure corrosion moisture resistance plastic-encapsulated circuits. nominal reverse bias applied device create electrolytic cells necessary accelerate corrosion metallization bond pads without heating device. duration test 1000 hours, with readouts (final electrical tests) hours hours during test. stress temperature humidity 85%. bias maximum operating voltage. Samples surface mount devices must undergo preconditioning pass final electrical test prior test Thermal Shock Test (TST) (MIL-STD-883; 1011) Thermal shock testing similar temperature cycle testing, except that thermal shock tests additional stress provided: sudden change temperature rapid transfer time. Thus test detect failure mechanisms caused Temperature Cycle Test (TCT) (MIL-STD-883; 1010) purpose temperature cycle testing study effect thermal expansion mismatch among different components within specific packaging system. cycling test system cold dwell dwell employs circulating environment ensure rapid stabilization specified temperature. During temperature cycle testing, devices inserted into cycling test system held cold dwell minutes, then devices heated dwell minutes. cycle includes duration both temperature transients temperature gradients. cycling test system fluorocarbon bath other fluorocarbon bath During thermal shock testing, devices inserted into cycling test system held cold dwell minutes then heated dwell minutes. cycle includes duration both extreme temperatures transition times. transition period less than seconds test duration cycles. Samples surface mount devices must undergo preconditioning pass final electrical test prior thermal shock test. extreme temperatures transition times. transition period less than minute test duration cycles SRAM, non-volatile, logic cycles DRAM. Samples surface mount devices must first undergo preconditioning pass final electrical test prior temperature cycle test.
Pressure Cooker Test (PCT) (EIAJ-IC-121-18) pressure cooker test environmental test that measures device resistance moisture penetration effect galvanic corrosion. stress conditions pressure cooker test employed Winbond SRAM, non-volatile logic) DRAM), 100% relative humidity. duration test hours. Samples surface mount devices subjected preconditioning final electrical test prior pressure cooker test. After pressure cooker test, leads test samples cleaned then baked hour before final electrical test. humidity stress test. stress conditions HAST test employed Winbond maximum operating voltage combination bias. duration test hours SRAM, nov-volatile, logic hours DRAM.
Device Reliability Tests
Electromigration (EM) Test Electromigration motion interconnect metallization momentum exchange from electron current. convergence metallic flux lead hillock formation, which result short circuits adjacent overlaying
Highly-Accelerated Temperature Humidity Stress Test (HAST) (JESD22-A110) highly accelerated temperature humidity stress test performed purpose evaluating reliability non-hermetic packaged solid-state device environment with high humidity. employs severe condition temperature, humidity, bias, which accelerate penetration moisture through external protective material (encapsulated seal) along interface between external protective material metallic conductor, which pass through Samples surface mount devices subjected preconditioning final electrical test prior highly-accelerated temperature
conductors. divergence metallic flux lead void formation, which result open circuit failure. electromigration test, specially designed test structures stressed high-current densities high temperature accelerate electromigration process. stress temperature SRAM, LOGIC EPROM process DRAM process, respectively. stress current density about Amp/cm test sample defined failure resistance variation more than initial resistance. Regression analysis used find best lognormal distribution data calculate
median time-to-failure(MTF) under stress conditions. Then, multiplying temperature current acceleration factors, find electromigration under condition. Lifetime() specified 0.1% 100K hours @130° SRAM, LOGIC, EPROM process 1ppm year @85°C DRAM process. Carrier Effect (HCE) Test carrier effects occur most transistors when lateral electric field drain depletion region channel becomes large that major carriers channel gain energy
from electric field faster. These carriers gain enough energy (1.5 impact-ionize create hole-electron pairs, which results
Stress Migration (SM) Test test performed DRAM process only. purpose test stress cause inadmissible resistance variation. stress temperature 225°C criterion specified <10% after 1000Hrs stress.
measurable substrate current consisting carriers with opposite charge major carriers channel. carriers further gain enough energy (3-4 eV), they overcome Si-SiO2 barrier injected into oxide layer. test, test transistors divided into three groups, which DC-stressed under three different values higher than maximum
Bias Temperautre(BT) Test test performed DRAM process only. purpose test investigate degradation during bias temperature stress ionic contamination increased positive charge. stress condition +/-3.75V 140°C criterion specified <50mV after 100Hrs stress.
operating voltage. Three different values before becomes infinity increases chosen three stress voltages. gates test transistors biased value such that Isub maximum value Isub NFET maximum value PFET, repectively. stress temperature room temperature. test sample defined failure variation Idsat more than lifetime
initial value NFET, variation more than 50mV PFET. specified year SRAM, LOGIC, EPROM process year DRAM process, respectively.
Charge Breakdown (QBD) Test purpose test measure breakdown charge density gate oxide. test, constant current density applied test sample until breaks down. stress current density Amp/cm pass test, breakdown charge density test sample must larger than Coul/cm
Test test, breakdown electric field gate oxide measured applying stepwise voltages test sample until breaks down. voltage step V/step. pass test, breakdown electric field test sample must larger than MV/cm.
TDDB Test oxide will only allow finite amount charge pass before breakdown. purpose TDDB testing characterize when this breakdown occurs evaluate oxide lifetime. Regression analysis used find best Weibull distribution data calculate median time-to-failure(MTF) under stress conditions(here Vuse@85C/140C normal operation conditions. lifetime criterion specified 1ppm year @85°C under normal operation voltage.
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