Operating voltage: 2.2V~5.5V input lines bidirectional lines external

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Operating voltage: 2.2V~5.5V input lines bidirectional lines external

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HT49C50-1 8-Bit Microcontroller
Operating voltage: 2.2V~5.5V input lines bidirectional lines external interrupt input 8-bit programmable timer/event counter with (programmable frequency divider) function driver with segments program memory data memory Real Time Clock (RTC) 8-bit prescaler Watchdog Timer
Buzzer output On-chip crystal, 32768Hz crystal oscillator HALT function wake-up feature reduce power consumption 6-level subroutine nesting manipulation instruction 15-bit table read instruction 0.5ms instruction cycle with 8MHz system clock powerful instructions instructions machine cycles 48-pin SSOP, 100-pin package
General Description
HT49C50-1 8-bit high performance single chip microcontroller. single cycle instruction two-stage pipeline architecture make suitable high speed applications. device suited multiple power applications among which calculators, clock timers, games, scales, leisure products, other hand held products, battery system particular.
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Block Diagram
ifte
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Assignment
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Assignment
substrate should connected layout artwork.
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Description
Name PA0/BZ PA1/BZ PA3/PFD PA4~PA7 Options Wake-up Pull-high None CMOS NMOS Description PA0~PA7 constitute 8-bit bidirectional input/output port with Schmitt trigger input capability. Each port configured wake-up input options. PA0~PA3 configured CMOS output NMOS input/output with without pull-high resistor options. PA4~PA7 always pull-high NMOS input/output. eight bits, PA0~PA1 pins buzzer outputs options. output also options. PB0~PB7 constitute 8-bit Schmitt trigger input port. Each port pull-high resistor. eight bits, input pins external interrupt control pins (INT0) (INT1) respectively, software application. input timer/event counter input TMR0 TMR1 also software application. PC0~PC3 constitute 4-bit bidirectional input/output port with Schmitt trigger input capability. port, such configured CMOS output NMOS input/output with without pull-high resistor options. Negative power supply, ground power supply Voltage pump SEG32 segment common output driver panel options. COM2~COM0 outputs panel plate. driver outputs panel segments
PB0/INT0 PB1/INT1 PB2/TMR0 PB3/TMR1 PB4~PB7
PC0~PC3 VLCD V1,V2,C1,C2 SEG32/COM3 COM2~COM0 SEG31~SEG0 OSC4 OSC3
Pull-high None CMOS NMOS Duty
Real time clock oscillators. OSC3 OSC4 connected 32768Hz crystal oscillator timing purposes system System Clock clock source (depending options). built-in capacitor Positive power supply
OSC2 OSC1
OSC1 OSC2 connected network crystal options) internal system clock. case eration, OSC2 output terminal system clock. Crystal system clock come from oscillator. system clock comes from RTCOSC, these pins cannot floating. Schmitt trigger reset input, active
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Absolute Maximum Ratings
Supply Voltage .VSS-0.3V 5.5V Input Voltage.VSS-0.3V VDD+0.3V Storage Temperature .-50°C 125°C Operating Temperature .-25°C 70°C
Note: These stress ratings only. Stresses exceeding range specified under Maximum cause substantial damage device. Functional operation this device other conditions beyond those listed specification implied prolonged exposure extreme conditions affect device reliability.
D.C. Characteristics
Symbol IDD1 IDD2 IDD3 ISTB1 Parameter Operating Voltage Operating Current (Crystal OSC) Operating Current OSC) Operating Current (fSYS=32768Hz) Standby Current (*fS=T1) Standby Current (*fS=32.768kHz OSC) Standby Current (*fS=WDT OSC) Standby Current (*fS=32.768kHz OSC) Standby Current (*fS=32.768kHz OSC) Standby Current (*fS=WDT OSC) Test Conditions Conditions Min.
Ta=25°C Typ. Max. Unit
load, fSYS=4MHz load, fSYS=4MHz load
load, system HALT HALT load, system HALT HALT, type load, system HALT HALT, type load, system HALT HALT type, bias load, system HALT HALT type, bias load, system HALT HALT type, bias
ISTB2
ISTB3
ISTB4
ISTB5
ISTB6
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Symbol Parameter Standby Current (*fS=WDT OSC) Input Voltage Ports, Input High Voltage Ports, Input Voltage (RES) Input High Voltage (RES) Port Sink Current Port Source Current Pull-high Resistance Ports INT0, INT1 Voltage Reset Voltage Voltage Detector Voltage Test Conditions Conditions load, system HALT HALT type, bias Min. 0.7VDD 0.7VDD 0.9VDD 0.9VDD Typ. Max. Unit 0.3VDD 0.3VDD 0.4VDD 0.4VDD
ISTB7
VIL1 VIH1 VIL2 VIH2 VLVR VLVD
VOL=0.1VDD VOL=0.1VDD VOH=0.9VDD VOH=0.9VDD voltage 3.3V option voltage 3.3V option
Note: tSYS=1/fSYS
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A.C. Characteristics
Symbol fSYS1 Parameter System Clock (Crystal OSC) Test Conditions fSYS2 fSYS3 fRTCOSC fTIMER tWDTOSC tRES tSST tINT System Clock OSC) System Clock (32768Hz Crystal OSC) Frequency Timer Frequency (TMR0/TMR1) Watchdog Oscillator External Reset Pulse Width System Start-up Timer Period Interrupt Pulse Width Conditions Wake-up from HALT Min. Typ. Max. 32768 32768 1024 4000 8000 4000 8000 4000 8000 Ta=25°C Unit tSYS
Note: tSYS=1/fSYS
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Functional Description
Execution flow system clock derived from either crystal oscillator 32768Hz crystal oscillator. internally divided into four non-overlapping clocks. instruction cycle consists four system clock cycles. Instruction fetching execution pipelined such that fetch takes instruction cycle while decoding execution takes next instruction cycle. pipelining scheme causes each instruction effectively execute cycle. instruction changes value program counter, cycles required complete instruction. Program counter program counter (PC) bits wide controls sequence which instructions stored program executed. contents specify maximum 4096 addresses. After accessing program memory word fetch instruction code, value incremented one. then points memory word containing next instruction code. When executing jump instruction, conditional skip execution, loading register, subroutine call, initial reset, internal interrupt, external interrupt, returning from
subroutine, manipulates program transfer loading address corresponding each instruction. conditional skip activated instructions. Once condition met, next instruction, fetched during current instruction execution, discarded dummy cycle replaces proper instruction; otherwise proceed with next instruction. lower byte (PCL) readable writeable register (06H). Moving data into performs short jump. destination within locations. When control transfer takes place, additional dummy cycle required. Program memory program memory (ROM) used store program instructions which executed. also contains data, table, interrupt entries, organized into 4096 bits which addressed table pointer. Certain locations reserved special usage:
Location 000H
Location 000H reserved program initialization. After chip reset, program always begins execution this location.
Execution flow
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Location 004H
itia
Location 004H reserved external interrupt service program. INT0 input activated, interrupt enabled, stack full, program begins execution location 004H.
Location 008H
Location 008H reserved external interrupt service program also. INT1 input activated, interrupt enabled, stack full, program begins execution location 008H.
Location 00CH
Timer/Event Counter interrupt service program. timer interrupt results from Timer/Event Counter overflow, interrupt enabled stack full, program begins execution location 00CH.
Location 010H
Program memory Timer/Event Counter overflow, interrupt enabled stack full, program begins execution location 010H. Program Counter
Timer/Event Counter interrupt service program. timer interrupt results from Mode Initial Reset External Interrupt External Interrupt Timer/Event Counter overflow Timer/Event Counter overflow Time Base Interrupt Interrupt Skip Loading Jump, Call Branch Return From Subroutine
PC+2
Program counter Note: *11~*0: Program counter bits #11~#0: Instruction code bits S11~S0: Stack register bits @7~@0: bits
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Location 014H
Location 014H reserved Time Base interrupt service program. Time Base interrupt occurs, interrupt enabled, stack full, program begins execution location 014H.
Location 018H
Stack register STACK stack register special part memory used save contents stack organized into levels neither part data part program, neither readable writeable. activated level indexed stack pointer (SP) neither readable writeable. commencement subroutine call interrupt acknowledgment, contents pushed onto stack. subroutine interrupt routine, signaled return instruction (RET RETI), contents restored previous value from stack. After chip reset, will point stack. stack full non-masked interrupt takes place, interrupt request flag recorded acknowledgment still inhibited. Once decremented RETI), interrupt serviced. This feature prevents stack overflow, allowing programmer structure easily. Likewise, stack full, subsequently executed, stack overflow occurs first entry lost (only most recent return addresses stored). Data memory data memory (RAM) designed with bits, divided into functional groups, namely special function registers general purpose data memory, most which readable/writeable, although some read only. Table Location
Location 018H reserved real time clock interrupt service program. real time clock interrupt occurs, interrupt enabled, stack full, program begins execution location 018H.
Table location
location used look-up table. instructions (the current page, page=256 words) (the last page) transfer contents lower-order byte specified data memory, contents higher-order byte TBLH (Table Higher-order byte register) (08H). Only destination lower-order byte table well-defined; other bits table word transferred lower portion TBLH, remaining read TBLH read only, table pointer (TBLP) read/write register (07H), indicating table location. Before accessing table, location should placed TBLP. table related instructions require cycles complete operation. These areas function normal depending upon requirements.
Instruction(s) TABRDC TABRDL
Table location Note: *11~*0: Table location bits @7~@0: Table pointer bits P11~P8: Current program Counter bits
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Status register (STATUS;0AH), Interrupt control register (INTC0;0BH), Timer/Event Counter (TMR0;0DH), Timer/Event Counter control register (TMR0C;0EH), Timer/Event Counter (TMR1;10H), Timer/Event Counter control register (TMR1C;11H), registers (PA;12H, PB;14H, PC;16H), Interrupt control register (INTC1;1EH). other hand, general purpose data memory, addressed from FFH, used data control information under instruction commands. areas directly handle arithmetic, logic, increment, decrement, rotate operations. Except some dedicated bits, each reset They also indirectly accessible through Memory pointer register (MP0;01H) Memory pointer register (MP1;03H). Indirect addressing register Location indirect addressing registers that physically implemented. read/write operation [00H] [02H] accesses pointed (01H) MP1(03H) respectively. Reading location indirectly returns result 00H. While, writing indirectly leads operation. function data movement between indirect addressing registers supported. memory pointer registers, MP1, both 8-bit registers used access combining corresponding indirect addressing registers. only applied data memory, while applied data memory display memory. Accumulator accumulator (ACC) related operations. also mapped location capable operating with immediate data. data movement between data memory locations must pass through ACC.
mapping types functional groups, special function registers consist Indirect addressing register (00H), Memory pointer register (MP0;01H), Indirect addressing register (02H), Memory pointer register (MP1;03H), Bank pointer (BP;04H), Accumulator (ACC;05H), Program counter lower-order byte register (PCL;06H), Table pointer (TBLP;07H), Table higher-order byte register (TBLH;08H), Real time clock control register (RTCC;09H),
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Arithmetic logic unit This circuit performs 8-bit arithmetic logic operations provides following functions:
Arithmetic operations (ADD, ADC, SUB,
SBC, DAA)
Logic operations (AND, XOR, CPL) Rotation (RL, RLC, RRC) Increment Decrement (INC, DEC) Branch decision (SZ, SNZ, SIZ, etc.)
ations related status register, however, yield different results from those intended. flags only changed Watchdog Timer overflow, chip power-up, clearing Watchdog Timer executing instruction. flags reflect status latest operations. entering interrupt sequence executing subroutine call, status register will automatically pushed onto stack. contents status important, subroutine likely corrupt status register, programmer should take precautions save properly. Interrupts HT49C50-1 provides external interrupts, internal timer/event counter interrupts, internal time base interrupt, internal real time clock interrupt. interrupt control register (INTC0;0BH) interrupt control register (INTC1;1EH) both contain interrupt control bits that used enable/disable status interrupt request flags. Function
only saves results data operation also changes status register. Status register STATUS status register (0AH) bits wide contains, carry flag (C), auxiliary carry flag (AC), zero flag (Z), overflow flag (OV), power down flag (PD), watchdog time-out flag (TO). also records status information controls operation sequence. Except flags, bits status register altered instructions similar other registers. Data written into status register does alter flags. OperLabels Bits
operation results carry during addition operation borrow does take place during subtraction operation; otherwise cleared. also affected rotate through carry instruction. operation results carry nibbles addition borrow from high nibble into nibble subtraction; otherwise cleared. result arithmetic logic operation zero; otherwise cleared. operation results carry into highest-order carry highest-order bit, vice versa; otherwise cleared. cleared either system power-up executing instruction. executing instruction. cleared system power-up executing instruction. time-out. Unused bit, read Status register
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Once interrupt subroutine serviced, other interrupts blocked clearing bit). This scheme prevent further interrupt nesting. Other interrupt requests take place during this interval, only interrupt request flag will recorded. certain interrupt requires servicing within service routine, corresponding INTC0 INTC1 order allow interrupt nesting. Once stack Register INTC0 (0BH) INTC1 (1EH) Label EEI0 EEI1 ET0I EIF0 EIF1 ET1I ETBI ERTI full, interrupt request will acknowledged, even related interrupt enabled, until decremented. immediate service desired, stack should prevented from becoming full. these interrupts support wake-up function. interrupt serviced, control transfer occurs pushing contents onto stack followed branch subFunction Control master (global) interrupt (1=enabled; 0=disabled) Control external interrupt (1=enabled; 0=disabled) Control external interrupt (1=enabled; 0=disabled) Control Timer/Event Counter interrupt (1=enabled; 0=disabled) External interrupt request flag (1=active; 0=inactive) External interrupt request flag (1=active; 0=inactive) Internal Timer/Event Counter request flag (1=active; 0=inactive) Unused bit, read Control Timer/Event Counter interrupt (1=enabled; 0=disabled) Control time base interrupt (1=enabled; 0:disabled) Control real time clock interrupt (1=enabled; 0:disabled) Unused bit, read Internal Timer/Event Counter request flag (1=active; 0=inactive) Time base request flag (1=active; 0=inactive) Real time clock request flag (1=active; 0=inactive) Unused bit, read INTC register
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routine specified location ROM. Only contents pushed onto stack. contents register status register (STATUS) altered interrupt service program which corrupts desired control sequence, contents should saved advance. External interrupts triggered high transition INT0 INT1, related interrupt request flag (EIF0; INTC0, EIF1; INTC0) well. After interrupt enabled, stack full, external interrupt active, subroutine call location occurs. interrupt request flag (EIF0 EIF1) bits cleared disable other interrupts. internal Timer/Event Counter interrupt initialized setting Timer/Event Counter interrupt request flag (T0F; INTC0), which normally caused timer overflow. After interrupt enabled, stack full, set, subroutine call location occurs. related interrupt request flag (T0F) reset, cleared disable further interrupts. Timer/Event Counter operated same manner related interrupt request flag (bit INTC1) subroutine call location 10H. time base interrupt initialized setting time base interrupt request flag (TBF; INTC1), that caused regular time base signal. After interrupt enabled, stack full, set, subroutine call location occurs. related interrupt request flag (TBF) reset cleared disable further interrupts. real time clock interrupt initialized setting real time clock interrupt request flag (RTF; INTC1), that caused regular real time clock signal. After interrupt enabled, stack full, set, subroutine call location occurs. related interrupt request flag (RTF) reset cleared disable further interrupts. During execution interrupt subroutine, other interrupt acknowledgments held
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until instruction executed related interrupt control both stack full). return from interrupt subroutine, invoked. RETI sets enables interrupt service, does not. Interrupts occurring interval between rising edges consecutive pulses serviced latter pulses corresponding interrupts enabled. case simultaneous requests, priorities following table apply. These masked resetting bit. Interrupt Source Priority External interrupt External interrupt Timer/event counter overflow Timer/event counter overflow Time base interrupt Real time clock interrupt Vector
Timer/Event Counter interrupt request flag (T0F), external interrupt request flag (EIF1), external interrupt request flag (EIF0), enable Timer/Event Counter interrupt (ET0I), enable external interrupt (EEI1), enable external interrupt (EEI0), enable master interrupt (EMI) make Interrupt Control register (INTC0) which located RAM. real time clock interrupt request flag (RTF), time base interrupt request flag (TBF), Timer/Event Counter interrupt request flag (T1F), enable real time clock interrupt (ERTI), enable time base interrupt (ETBI), enable Timer/Event Counter interrupt (ET1I) other hand, constitute Interrupt Control register (INTC1) which located RAM. EMI, EEI0, EEI1, ET0I, ET1I, ETBI, ERTI used control enable/disable status interrupts. These bits
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prevent requested interrupt from being serviced. Once interrupt request flags (RTF, TBF, T0F, T1F, EIF1, EIF0) set, they remain INTC1 INTC0 respectively until interrupts serviced cleared software instruction. recommended that program within interrupt subroutine. because interrupts often occur unpredictable manner require serviced immediately some applications. this time, only stack left, enabling interrupt well controlled, operation interrupt subroutine damage original control sequence. Oscillator configuration HT49C50-1 provides oscillator circuits system clocks, i.e., oscillator crystal oscillator, determined mask option. matter what type oscillator selected, signal used system clock. HALT mode stops system oscillator ignores external signal conserve power. oscillators, oscillator used, external resistor between OSC1 required, range resistance should from 51kW 1MW. system clock, divided available OSC2 with pull-high resistor, which used synchronize external logic. oscillator provides most cost effective solution. However, frequency oscillation vary with VDD, temperature, chip itself process variations. therefore, suitable timing sensitive operations where accurate
illa
illa
System oscillator oscillator frequency desired. other hand, crystal oscillator selected, crystal across OSC1 OSC2 needed provide feedback phase shift required oscillator, other external components required. resonator connected between OSC1 OSC2 replace crystal frequency reference, external capacitors OSC1 OSC2 required. There another oscillator circuit designed real time clock. this case, only 32.768kHz crystal oscillator applied. crystal should connected between OSC3 OSC4, external capacitors along with external resistor required oscillator circuit order stable frequency. oscillator circuit controlled oscillate quickly setting (bit RTCC). recommended turn quick oscillating function upon power turn after seconds. oscillator free running on-chip oscillator, external components required. Although system enters power down mode, system clock stops, oscillator still works with period approximately 78ms. oscillator disabled mask option conserve power.
32768Hz crystal/RTC oscillator
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Watchdog Timer clock source implemented dedicated oscillator (WDT oscillator) instruction clock (system clock/4) real time clock oscillator (RTC oscillator). timer designed prevent software malfunction sequence from jumping unknown location with unpredictable results. disabled mask option. disabled, executions related lead operation. time-out period fixed fS/216. clock source chooses internal oscillator, time-out period vary with temperature, VDD, process variations. other hand, clock source selects instruction clock instruction executed, stop counting lose protecting purpose, logic only restarted external logic. When device operates noisy environment, using on-chip oscillator (WDT OSC) strongly recommended, since HALT stop system clock. overflow under normal operation initializes sets status HALT mode, overflow initializes only reset zero. clear contents WDT, there three methods adopted, i.e., external reset level RES), software instruction, instruction. There types software instructions; other these types instruction, only type instruction active time depending mask option times selection selected (i.e., times equal one), execution instruction clears WDT. case that chosen (i.e., times equal two), these instructions have executed clear WDT; otherwise, reset chip time-out. Multi-function timer HT49C50-1 provides multi-function timer WDT, time base with different time-out periods. multi-function timer consists 7-stage divider 8-bit prescaler, with clock source coming from instruction clock (i.e., system clock divided multi-function timer also provides selectable frequency signal (ranges from fS/22 fS/28) driver circuits, selectable frequency signal (ranges from fS/22 fS/29) buzzer output mask option. recommended select near 4kHz signal driver circuits proper display.
Watchdog Timer
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Time base time base offers periodic time-out period generate regular internal interrupt. time-out period ranges from fS/212 fS/215 selected mask option. time base time-out occurs, related interrupt request flag (TBF; INTC1) set. interrupt enabled, stack full, subroutine call location occurs. time base time-out signal also applied clock source Timer/Event Counter getting longer timer-out period. Real time clock real time clock (RTC) operated same manner time base that used supply regular internal interrupt. time-out period ranges from fS/28 fS/215 software programming Writing data RT2, (bit2, RTCC;09H) yields various time-out periods. time-out occurs, related interrupt request flag (RTF;
INTC1) set. interrupt enabled, stack full, subroutine call location occurs. real time clock time-out signal also applied clock source Timer/Event Counter getting longer time-out period. Clock Divided Factor 210* 211*
Note: recommended used
Time base
Real time clock
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Power down operation HALT HALT mode initialized instruction results following.
system oscillator turns
enabled stack full, program resumes execution next instruction. interrupt enabled, stack full, regular interrupt response takes place. When interrupt request flag before entering status, system cannot awaken using that interrupt. wake-up events occur, takes 1024 tSYS (system clock period) resume normal operation. other words, dummy period inserted after wake-up. wake-up results from interrupt acknowledgment, actual interrupt subroutine execution delayed more than cycle. However, Wake-up results next instruction execution, execution will performed immediately after dummy period finished. minimize power consumption, pins should carefully managed before entering HALT status. Reset There three ways which reset occur.
reset during normal operation reset during HALT time-out reset during normal
oscillator keeps running oscillator real time clock selected). contents on-chip registers remain unchanged. cleared start recounting clock source from oscillator real time clock oscillator). ports maintain their original status.
flag flag cleared. driver still running
selected).
system quits HALT mode external reset, interrupt, external falling edge signal port overflow. external reset causes device initialization, overflow performs After examining flags, reason chip reset determined. flag cleared system power-up executing instruction, executing instruction. other hand, flag time-out occurs, causes wake-up that only resets (Program Counter) leaves others their original state. port wake-up interrupt methods considered continuation normal execution. Each port independently selected wake-up device mask option. Awakening from port stimulus, program resumes execution next instruction. other hand, awakening from interrupt, sequences occur. related interrupt disabled interrupt
operation
time-out during HALT differs from other chip reset conditions, perform that resets only leaves other circuits their original state. Some registers remain unaffected during other reset conditions. Most registers reset once reset conditions met. Examining flags, program distinguish between different
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Interrupt
000H Disabled Cleared Cleared. After master reset, starts counting Input mode Points stack
Prescaler, Divider WDT, RTC, Time base Timer/event counter Input/output ports
Reset circuit RESET Conditions reset during power-up reset during normal operation Wake-up HALT time-out during normal operation Wake-up HALT
Note: means guarantee that system oscillator started stabilized, (System Start-up Timer) provides extra-delay 1024 system clock pulses when system awakes from HALT state during power Awaking from HALT state system power-up, delay added. extra delay added during power-up period, wake-up from HALT enable only delay. functional unit chip reset status shown below.
Reset timing chart
Reset configuration
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states registers summarized below: Register TMR0 TMR0C TMR1 TMR1C Program Counter TBLP TBLH STATUS INTC0 INTC1 RTCC Note: Reset (Power xxxx xxxx 0000 1-xxxx xxxx 0000 1-000H xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx -xxx xxxx xxxx -000 0000 -000 -000 0111 1111 1111 1111 1111 xxxx 1111 refers warm reset means means Time-out (Normal Operation) uuuu uuuu 0000 1-uuuu uuuu 0000 1-000H uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu -uuu uuuu uuuu -000 0000 -000 -000 0111 1111 1111 1111 1111 xxxx 1111 Reset (Normal Operation) uuuu uuuu 0000 1-uuuu uuuu 0000 1-000H uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu -uuu uuuu uuuu -000 0000 -000 -000 0111 1111 1111 1111 1111 xxxx 1111 Reset (HALT) uuuu uuuu 0000 1-uuuu uuuu 0000 1-000H uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu -uuu uuuu uuuu -000 0000 -000 -000 0111 1111 1111 1111 1111 xxxx 1111 Time-out (HALT)* uuuu uuuu uuuu u-uuuu uuuu uuuu u-000H uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu -uuu uuuu uuuu -uuu uuuu -uuu -uuu uuuu uuuu uuuu uuuu uuuu xxxx uuuu
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Timer/Event Counter timer/event counters implemented HT49C50-1. Both them contain 8-bit programmable count-up counter. timer/event count clock source come from system clock system clock/4 time-out signal external source. System clock source system clock/4 selected mask option. timer/event count clock source come from TMR0 overflow system clock time base time-out signal system clock/4 external source, three former clock source selected mask option. external clock input allows user count external events, measure time intervals pulse widths, generate accurate time base. timer/event counters operated almost same manner, except clock source related registers. There registers related Timer/Event Counter i.e., TMR0 ([0DH]) TMR0C ([0EH]), registers related Timer/Event Counter i.e., TMR1 ([10H], TMR1C ([11H]). There also physical registers mapped TMR0 (TMR1) location; writing TMR0 (TMR1) places starting value timer/event counter preload register, while reading yields contents timer/event counter. TMR0C TMR1C
timer/event counter control registers used define some options. bits define operation mode. event count mode used count external events, which means that clock source from external (TMR0, TMR1) pin. timer mode functions normal timer with clock source coming from internal selected clock source. Finally, pulse width measurement mode used count high level duration external signal (TMR0, TMR1), counting based internal selected clock source. event count timer mode, timer/event counter starts counting current contents timer/event counter ends FFH. Once overflow occurs, counter reloaded from timer/event counter preload register, generates interrupt request flag (T0F; INTC0, T1F; INTC1). pulse width measurement mode with values bits equal one, after TMR0 (TMR1) received transient from high high will start counting until TMR0 (TMR1) returns original level resets TON. measured result remains timer/event counter even activated transient occurs again. other words, only cycle measurement made until set. cycle measurement will re-function long receives
Timer/Event Counter
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Label (TMR0C) Bits Unused bit, read define TMR0 active edge timer/event counter (0=active high; 1=active high low) enable/disable timer counting (0=disabled; 1=enabled) multiplexer control inputs select timer/event counter clock source (0=RTC outputs; system clock system clock/4) define operating mode (TN1, TN0) 01=Event count mode (External clock) 10=Timer mode (Internal clock) 11=Pulse Width measurement mode (External clock) 00=Unused TMR0C register further transient pulse. this operation mode, timer/event counter begins counting according logic level transient edges. case counter overflows, counter reloaded from timer/event counter preload register issues interrupt request, other modes, i.e., event timer modes. enable counting operation, Timer (TON; TMR0C TMR1C) should pulse width measurement mode, automatically cleared after measurement cycle completed. other modes, only
Function
instructions. overflow Timer/Event Counter wake-up sources also applied (Programmable Frequency Divider) output mask option. Only (PFD0 PFD1) applied mask option matter what operation mode writing ET0I ET1I disables related interrupt service. When function selected, executing instruction enable output executing instruction disable output. case timer/event counter condition, writing data timer/event counter
Timer/Event Counter
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Label (TMR1C) Bits Unused bit, read define TMR1 active edge timer/event counter active high; active high low) enable/disable timer counting disabled; enabled) multiplexer control inputs select timer/event counter clock source mask option clock source; system clock/4) define operating mode Event count mode (External clock) Timer mode (Internal clock) Pulse Width measurement mode (External clock) Unused TMR1C register preload register also reloads that data timer/ event counter. timer/event counter turn data written timer/event counter kept only timer/event counter preload register. timer/event counter still continues operation until overflow occurs. When timer/event counter (reading TMR0/TMR1) read, clock blocked avoid errors. this results counting error, blocking clock should taken into account programmer. strongly recommended load desired value into TMR0/TMR1 register first, then turn related timer/event counter proper operation. Because initial value TMR0/TMR1 unknown. timer/event scheme, programmer should special attention instruction enable then disable timer first time, whenever there need timer/event function, avoid unpredicatable result. After this procedure, timer/event function operated normally. example given below, using 8-bit width (timer ;timer cascade into 16-bit width. START: ET0I&EMI bits intc0, enable timer global interrupt Function
ET1I enable intc1, timer interrupt operating mode tmr1c, timer mode select mask option clock source 0a0h operating mode timer tmr0c, mode select system clock/4 tmr1c.4 Enable then disable timer tmr1c.4 first time tmr0, tmr1, Load desired value into TMR0/TMR1 register Normal operating
tmr0c.4 tmr1c.4
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Input/output ports There 12-bit bidirectional input/output port, 8-bit input port HT49C50-1, labeled which mapped [12H], [14H] [16H] RAM, respectively. PA0~PA3 configured CMOS (output) NMOS (input/output) with without pull-high resistor mask option. PA4~PA7 always pull-high NMOS (input/output). choose NMOS (input), each port (PA0~PA7) configured wake-up input. only used input operation. contents PC4~PC7 unknown. configured CMOS output NMOS input/output with without pull-high resistor mask option. port input operation (PA, PC), these ports non-latched, that inputs should ready rising edge instruction (m=12H 14H). output operation, data latched remain unchanged until output latch rewritten. When structures open drain NMOS type, should noted that, before reading data from pads, should written related bits disable NMOS device. That executing first instruction (i=0~7 disable related NMOS device, then stable data. After chip reset, these input lines remain high level left floating options). Each these output latches cleared [m], (m=12H 16H) instruction. Some instructions first input data then follow output operations. example, read entire port states into CPU, execute defined operations (bit-operation), then write results back latches accumulator. When line used line, related line options should configured NMOS with without pull-high resistor. Once line selected CMOS output, function cannot used. input state line read from related pad. When configured NMOS with without pull-high resistor, should careful when applying read-modify-write instruction Since read-modify-write will read entire port state (pads state) firstly, execute specified instruction then write result port data register. When read operation executed, fault state (caused load effect floating state) read. Errors will then occur. There three function pins that share with port: PA0/BZ, PA1/BZ PA3/PFD.
Input/output ports
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buzzer driving output pair programmable frequency divider output. user wants BZ/BZ function, related port should CMOS output. buzzer output signals controlled data registers defined following table. Data Data PA0/PA1 State Register Register PA0=BZ, PA1=BZ PA0=BZ, PA1=0 PA0=0, PA1=0 output signal function controlled data register timer/event counter state. output signal frequency also dependent timer/event counter overflow period. definitions control signal output frequency listed following table. display memory HT49C50-1 provides area embedded data memory display. This area located from Bank Bank pointer (BP; located RAM) switch between display memory. When data written into 40H~60H will effect display. When cleared data written into 40H~60H means access general purpose data memory. display memory read written only indirect addressing mode using MP1. When data written into display data area, automatically read driver which then generates corresponding driving sigPA3 State Frequency
Note: stands
Input Ports
Timer Timer Preload Value Data Register
Note: stands stands
Display memory
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nals. turn display off, written corresponding display memory, respectively. figure illustrates mapping between display memory pattern HT49C50-1. driver output output number driver options (i.e., duty, duty duty). bias type driver type type. bias type selected, external capacitor required. bias type selected, capacitor mounted between pins needed. bias voltage driver bias bias options. bias selected, capacitor mounted between ground required. bias selected, capacitors needed pins. Refer application diagram.
driver output (1/3 duty, bias, type)
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driver output (1/4 duty, bias, type)
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voltage reset/detector functions There voltage detector (LVD) voltage reset circuit (LVR) implemented microcontrollers. These functions enabled/disabled code options. enabled/disabled code options. Once code options enabled, user RTCC.3 Register RTCC (09H) Note: Label RT0~RT2 LVDC* QOSC LVDO enable/disable (1/0) circuit read detector status (0/1) from RTCC.5; otherwise, function disabled. same effect function with external signal which performs chip reset. During HALT state, disabled. definitions RTCC register listed following table. Function multiplexer control inputs select real clock prescaler output enable/disable (1/0) 32768Hz quick start-up oscillating 0/1: quickly/slowly start detection output (1/0) voltage detected Undefined, read
Read/Write Reset
Once function enabled reference generator should enabled; otherwise reference generator controlled code option. relationship between options LVDC shown. LVDC VREF Generator Comparator Comparator
Mask option following shows mask options HT49C50-1. these options should defined order ensure proper system functioning. Mask Option type selection. This option decide Crystal 32768Hz crystal oscillator chosen system clock. Clock source selection. Time Base. There three types selection: system clock/4 OSC. enable/disable selection. enabled disabled mask option.
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Mask Option times selection. This option defines clear instruction. means that clear WDT. means only both have been executed, cleared. Time Base time-out period selection. Time Base time-out period ranges from clock/212 clock/215. means clock source selected mask option. Buzzer output frequency selection. There eight types frequency signals buzzer output: Clock/22~Clock/29. means clock source selected mask option. Wake-up selection. This option defines wake-up capability. External pins only) have capability wake-up chip from HALT falling edge. Pull-high selection. This option decide whether pull-high resistance visible PA0~PA3 PA4~PA7 always pull-high) PA0~PA3 CMOS NMOS selection. structure PA0~PA3 each bits selected CMOS NMOS individually. When CMOS selected, related pins only used output operations. When NMOS selected, related pins used input output operations. (PA4~PA7 always NMOS) Clock source selection Timer/Event Counter There types selection: system clock system clock/4. Clock source selection Timer/Event Counter There three types selection: TMR0 overflow, system clock Time Base overflow. pins share with other functions selection. PA0/BZ, PA1/BZ: pins buzzer outputs. PA3/PFD: pins output. common selection. There three types selection: common (1/2 duty) common (1/3 duty) common (1/4 duty). common selected, segment output will common output. bias power supply selection. There types selection: bias bias. bias type selection. This option decide what kind bias selected, type type. driver clock selection. There seven types frequency signals driver circuits: fS/22~fS/28. means clock source selection mask option. ON/OFF HALT selection selection enable disable options selection enable disable options selection. output, there types selection; PFD0 output, other PFD1 output. PFD0, PFD1 timer overflow signals Timer/Event Counter Timer/Event Counter respectively.
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Application Circuits
illa
illa
illa
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Instruction Summary
Mnemonic Arithmetic A,[m] ADDM A,[m] A,[m] ADCM A,[m] A,[m] SUBM A,[m] A,[m] SBCM A,[m] Logic Operation A,[m] A,[m] A,[m] ANDM A,[m] A,[m] XORM A,[m] CPLA INCA DECA data memory data memory Exclusive-OR data memory data memory data memory Exclusive-OR data memory immediate data immediate data Exclusive-OR immediate data Complement data memory Complement data memory with result Increment data memory with result Increment data memory Decrement data memory with result Decrement data memory data memory data memory immediate data data memory with carry register with carry Subtract immediate data from Subtract data memory from Subtract data memory from with result data memory Subtract data memory from with carry Subtract data memory from with carry with result data memory Decimal adjust addition with result data memory Z,C,AC,OV Z,C,AC,OV Z,C,AC,OV Z,C,AC,OV Z,C,AC,OV Z,C,AC,OV Z,C,AC,OV Z,C,AC,OV Z,C,AC,OV Z,C,AC,OV Description Flag Affected
Increment Decrement
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Mnemonic Rotate RRCA RLCA Data Move A,[m] [m],A Operation [m].i [m].i Branch addr [m].i [m].i SIZA SDZA CALL addr RETI Table Read TABRDC TABRDL Read code (current page) data memory TBLH Read code (last page) data memory TBLH None None Jump unconditionally Skip data memory zero Skip data memory zero with data movement Skip data memory zero Skip data memory zero Skip increment data memory zero Skip decrement data memory zero Skip increment data memory zero with result Skip decrement data memory zero with result Subroutine call Return from subroutine Return from subroutine load immediate data Return from interrupt None None None None None None None None None None None None None Clear data memory data memory None None Move data memory Move data memory Move immediate data None** None None Rotate data memory right with result Rotate data memory right Rotate data memory right through carry with result Rotate data memory right through carry Rotate data memory left with result Rotate data memory left Rotate data memory left through carry with result Rotate data memory left through carry None None None None Description Flag Affected
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Mnemonic Miscellaneous WDT1 WDT2 SWAP SWAPA HALT operation Clear data memory data memory Clear Watchdog Timer Pre-clear Watchdog Timer Pre-clear Watchdog Timer Swap nibbles data memory Swap nibbles data memory with result Enter power down mode None None None TO,PD TO*,PD* TO*,PD* None None TO,PD Description Flag Affected
Note: 8-bit immediate data 7-bit data memory address accumulator number bits addr: 10-bit program memory address Flag(s) affected Flag(s) affected Flag(s) affected execution status version E.V. chip, zero flag affected executing A,[M] instruction. version E.V. chip, zero flag cannot changed executing A,[M] instruction.
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Instruction Definition
A,[m] Description Operation Affected flag(s) ADCM A,[m] Description Operation Affected flag(s) A,[m] Description Operation Affected flag(s) Description Operation Affected flag(s) data memory carry accumulator contents specified data memory, accumulator carry flag added simultaneously, leaving result accumulator. ACC+[m]+C
accumulator carry data memory contents specified data memory, accumulator carry flag added simultaneously, leaving result specified data memory. ACC+[m]+C
data memory accumulator contents specified data memory accumulator added. result stored accumulator. ACC+[m]
immediate data accumulator contents accumulator specified data added, leaving result accumulator. ACC+x
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ADDM A,[m] Description Operation Affected flag(s) A,[m] Description Operation Affected flag(s) Description Operation Affected flag(s) ANDM A,[m] Description Operation Affected flag(s) accumulator data memory contents specified data memory accumulator added. result stored data memory. ACC+[m]
Logical accumulator with data memory Data accumulator specified data memory perform bitwise logical_AND operation. result stored accumulator.
Logical immediate data accumulator Data accumulator specified data perform bitwise logical_AND operation. result stored accumulator.
Logical data memory with accumulator Data specified data memory accumulator perform bitwise logical_AND operation. result stored data memory.
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CALL addr Description Subroutine call instruction unconditionally calls subroutine located indicated address. program counter increments once obtain address next instruction, pushes this onto stack. indicated address then loaded. Program execution continues with instruction this address. Stack PC+1 addr Description Operation Affected flag(s) [m].i Description Operation Affected flag(s) Description Operation Affected flag(s)
Operation Affected flag(s)
Clear data memory contents specified data memory cleared
Clear data memory specified data memory cleared [m].i
Clear Watchdog Timer Prescaler cleared (re-counting from power down (PD) time-out (TO) cleared.
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WDT1 Description Preclear Watchdog Timer flags cleared (re-counting from other preclear instruction been executed. Only execution this instruction without other preclear instruction sets indicated flag which implies that this instruction been executed flags remain unchanged. 00H* WDT2 Description
Operation Affected flag(s)
Preclear Watchdog Timer flags cleared (re-counting from other preclear instruction been executed. Only execution this instruction without other preclear instruction sets indicated flag which implies that this instruction been executed flags remain unchanged. 00H*
Operation Affected flag(s)
Description Operation Affected flag(s)
Complement data memory Each specified data memory logically complemented complement). Bits which previously contained changed vice-versa.
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CPLA Description Complement data memory place result accumulator Each specified data memory logically complemented complement). Bits which previously contained changed vice-versa. complemented result stored accumulator contents data memory remain unchanged. Description
Operation Affected flag(s)
Decimal-Adjust accumulator addition accumulator value adjusted (Binary Coded Decimal) code. accumulator divided into nibbles. Each nibble adjusted code internal carry (AC1) will done nibble accumulator greater than adjustment done adding original value original value greater than carry set; otherwise original value remains unchanged. result stored data memory only carry flag affected. ACC.3~ACC.0 AC=1 then [m].3~[m].0 (ACC.3~ACC.0)+6, AC1=AC else [m].3~[m].0) (ACC.3~ACC.0), AC1=0 ACC.7~ACC.4+AC1 then [m].7~[m].4 ACC.7~ACC.4+6+AC1,C=1 else [m].7~[m].4 ACC.7~ACC.4+AC1,C=C
Operation
Affected flag(s)
Description Operation Affected flag(s)
Decrement data memory Data specified data memory decremented [m]-1
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DECA Description Operation Affected flag(s) HALT Description Decrement data memory place result accumulator Data specified data memory decremented leaving result accumulator. contents data memory remain unchanged. [m]-1
Enter power down mode This instruction stops program execution turns system clock. contents registers retained. prescaler cleared. power down (PD) time-out (TO) cleared. PC+1
Operation
Affected flag(s)
Description Operation Affected flag(s)
Increment data memory Data specified data memory incremented [m]+1
INCA Description Operation Affected flag(s)
Increment data memory place result accumulator Data specified data memory incremented leaving result accumulator. contents data memory remain unchanged. [m]+1
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addr Description Operation Affected flag(s) A,[m] Description Operation Affected flag(s) Description Operation Affected flag(s) [m],A Description Operation Affected flag(s) Description Operation Affected flag(s) Directly jump contents program counter replaced with directly-specified address unconditionally, control passed this destination. addr
Move data memory accumulator contents specified data memory copied accumulator.
Move immediate data accumulator 8-bit data specified code loaded into accumulator.
Move accumulator data memory contents accumulator copied specified data memory (one data memories).
operation operation performed. Execution continues with next instruction. PC+1
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A,[m] Description Logical accumulator with data memory Data accumulator specified data memory (one data memories) perform bitwise logical_OR operation. result stored accumulator. Description Operation Affected flag(s) A,[m] Description
Operation Affected flag(s)
Logical immediate data accumulator Data accumulator specified data perform bitwise logical_OR operation. result stored accumulator.
Logical data memory with accumulator Data data memory (one data memories) accumulator perform bitwise logical_OR operation. result stored data memory.
Operation Affected flag(s)
Description Operation Affected flag(s)
Return from subroutine program counter restored from stack. This 2-cycle instruction. Stack
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Description Operation Affected flag(s) RETI Description Return place immediate data accumulator program counter restored from stack accumulator loaded with specified 8-bit immediate data. Stack
Return from interrupt program counter restored from stack, interrupts enabled setting bit. enable master (global) interrupt (bit register INTC). Stack
Operation Affected flag(s)
Description Operation Affected flag(s)
Rotate data memory left contents specified data memory rotated left with rotated into [m].(i+1) [m].i; [m].i:bit data memory (i=0~6) [m].0 [m].7
Description
Rotate data memory left place result accumulator Data specified data memory rotated left with rotated into leaving rotated result accumulator. contents data memory remain unchanged. ACC.(i+1) [m].i; [m].i:bit data memory (i=0~6) ACC.0 [m].7
Operation Affected flag(s)
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Description Rotate data memory left through carry contents specified data memory carry flag rotated left. replaces carry bit; original carry flag rotated into position. [m].(i+1) [m].i; [m].i:bit data memory (i=0~6) [m].0 [m].7 RLCA Description
Operation
Affected flag(s)
Rotate left through carry place result accumulator Data specified data memory carry flag rotated left. replaces carry original carry flag rotated into position. rotated result stored accumulator contents data memory remain unchanged. ACC.(i+1) [m].i; [m].i:bit data memory (i=0~6) ACC.0 [m].7
Operation
Affected flag(s)
Description Operation Affected flag(s)
Rotate data memory right contents specified data memory rotated right with rotated [m].i [m].(i+1); [m].i:bit data memory (i=0~6) [m].7 [m].0
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Description Rotate right-place result accumulator Data specified data memory rotated right with rotated into leaving rotated result accumulator. contents data memory remain unchanged. ACC.(i) [m].(i+1); [m].i:bit data memory (i=0~6) ACC.7 [m].0 Description
Operation Affected flag(s)
Rotate data memory right through carry contents specified data memory carry flag together rotated right. replaces carry bit; original carry flag rotated into position. [m].i [m].(i+1); [m].i:bit data memory (i=0~6) [m].7 [m].0
Operation
Affected flag(s)
RRCA Description
Rotate right through carry-place result accumulator Data specified data memory carry flag rotated right. replaces carry original carry flag rotated into position. rotated result stored accumulator. contents data memory remain unchanged. ACC.i [m].(i+1); [m].i:bit data memory (i=0~6) ACC.7 [m].0
Operation
Affected flag(s)
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A,[m] Description Subtract data memory carry from accumulator contents specified data memory complement carry flag subtracted from accumulator, leaving result accumulator. ACC+[m]+C SBCM A,[m] Description
Operation Affected flag(s)
Subtract data memory carry from accumulator contents specified data memory complement carry flag subtracted from accumulator, leaving result data memory. ACC+[m]+C
Operation Affected flag(s)
Description
Skip decrement data memory contents specified data memory decremented result next instruction skipped. result following instruction, fetched during current instruction execution, discarded dummy cycle replaced proper instruction cycles). Otherwise proceed with next instruction cycle). Skip ([m]-1)=0, ([m]-1)
Operation Affected flag(s)
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SDZA Description Decrement data memory place result ACC, skip contents specified data memory decremented result next instruction skipped. result stored accumulator data memory remains unchanged. result following instruction, fetched during current instruction execution, discarded dummy cycle replaced proper instruction cycles). Otherwise proceed with next instruction cycle). Skip ([m]-1)=0, ([m]-1) Description Operation Affected flag(s) [m].i Description Operation Affected flag(s) Description
Operation Affected flag(s)
data memory Each specified data memory
data memory specified data memory [m].i
Skip increment data memory contents specified data memory incremented result following instruction, fetched during current instruction execution, discarded dummy cycle replaced proper instruction cycles). Otherwise proceed with next instruction cycle). Skip ([m]+1)=0, ([m]+1)
Operation Affected flag(s)
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SIZA Description Increment data memory place result ACC, skip contents specified data memory incremented result next instruction skipped result stored accumulator. data memory remains unchanged. result zero, following instruction, fetched during current instruction execution, discarded dummy cycle replaced proper instruction cycles). Otherwise proceed with next instruction cycle). Skip ([m]+1)=0, ([m]+1) [m].i Description
Operation Affected flag(s)
Skip data memory specified data memory next instruction skipped. data memory following instruction, fetched during current instruction execution, discarded dummy cycle replaced proper instruction cycles). Otherwise proceed with next instruction cycle). Skip
Operation Affected flag(s)
A,[m] Description Operation Affected flag(s)
Subtract data memory from accumulator specified data memory subtracted from contents accumulator, leaving result accumulator. ACC+[m]+1
SUBM A,[m] Description Operation Affected flag(s)
Subtract data memory from accumulator specified data memory subtracted from contents accumulator, leaving result data memory. ACC+[m]+1
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Description Operation Affected flag(s) SWAP Description Operation Affected flag(s) SWAPA Description Subtract immediate data from accumulator immediate data specified code subtracted from contents accumulator, leaving result accumulator. ACC+x+1
Swap nibbles within data memory low-order high-order nibbles specified data memory (one data memories) interchanged. [m].3~[m].0 [m].7~[m].4
Swap data memory-place result accumulator low-order high-order nibbles specified data memory interchanged, writing result accumulator. contents data memory remain unchanged. ACC.3~ACC.0 [m].7~[m].4 ACC.7~ACC.4 [m].3~[m].0
Operation Affected flag(s)
Description
Skip data memory contents specified data memory following instruction, fetched during current instruction execution, discarded dummy cycle replaced proper instruction cycles). Otherwise proceed with next instruction cycle). Skip [m]=0
Operation Affected flag(s)
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Description Move data memory ACC, skip contents specified data memory copied accumulator. contents following instruction, fetched during current instruction execution, discarded dummy cycle replaced proper instruction cycles). Otherwise proceed with next instruction cycle). Skip [m]=0, [m].i Description
Operation Affected flag(s)
Skip data memory specified data memory following instruction, fetched during current instruction execution, discarded dummy cycle replaced proper instruction cycles). Otherwise proceed with next instruction cycle). Skip [m].i=0
Operation Affected flag(s)
TABRDC Description
Move code (current page) TBLH data memory byte code (current page) addressed table pointer (TBLP) moved specified data memory high byte transferred TBLH directly. code (low byte) TBLH code (high byte)
Operation Affected flag(s)
TABRDL Description Operation Affected flag(s)
Move code (last page) TBLH data memory byte code (last page) addressed table pointer (TBLP) moved data memory high byte transferred TBLH directly. code (low byte) TBLH code (high byte)
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A,[m] Description Operation Affected flag(s) XORM A,[m] Description Logical accumulator with data memory Data accumulator indicated data memory perform bitwise logical Exclusive_OR operation result stored accumulator.
Logical data memory with accumulator Data indicated data memory accumulator perform bitwise logical Exclusive_OR operation. result stored data memory. flag affected.
Operation Affected flag(s)
Description
Logical immediate data accumulator Data accumulator specified data perform bitwise logical Exclusive_OR operation. result stored accumulator. flag affected.
Operation Affected flag(s)
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Holtek Semiconductor Inc. (Headquarters) No.3 Creation Science-based Industrial Park, Hsinchu, Taiwan, R.O.C. Tel: 886-3-563-1999 Fax: 886-3-563-1189 Holtek Semiconductor Inc. (Taipei Office) 11F, No.576, Sec.7 Chung Hsiao Rd., Taipei, Taiwan, R.O.C. Tel: 886-2-2782-9635 Fax: 886-2-2782-9636 Fax: 886-2-2782-7128 (International sales hotline) Holtek Semiconductor (Hong Kong) Ltd. RM.711, Tower Cheung Plaza, Cheung Rd., Kowloon, Hong Kong Tel: 852-2-745-8288 Fax: 852-2-742-8657 Holtek Semiconductor (Shanghai) Ltd. Floor, Building No.889, Shan Rd., Shanghai, China Tel: 021-6485-5560 Fax: 021-6485-0313 Holmate Technology Corp. 48531 Warm Springs Boulevard, Suite 413, Fremont, 94539 Tel: 510-252-9880 Fax: 510-252-9885 Copyright 2001 HOLTEK SEMICONDUCTOR INC. information appearing this Data Sheet believed accurate time publication. However, Holtek assumes responsibility arising from specifications described. applications mentioned herein used solely purpose illustration Holtek makes warranty representation that such applications will suitable without further modification, recommends products application that present risk human life malfunction otherwise. Holtek reserves right alter products without prior notification. most up-to-date information, please visit site http://www.holtek.com.tw.
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Operating voltage: 2.2V~5.5V input lines bidirectional lines external

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