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XE88LC06A Ultra Low-Power Low-Voltage Radio Machine Applicat


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Data Sheet XE88LC06A
XE88LC06A
Ultra Low-Power Low-Voltage Radio Machine
Applications
companion chip system supervisor Portable, battery operated instruments Metering Remote control HVAC control XE88LC06A ultra low-power low-voltage microcontroller based Radio Machine. includes revolutionary BitJockey, UART type peripheral specialized radio communication. XE88LC06A available with chip MultipleTime-Programmable (MTP) program memory.
product Features
Ultra low-power MCU, MIPS MIPS operation operation time keeping Low-voltage operation (1.2 supply voltage) ROM/MTP, counters PWM, UART, BitJockey Analog matrix switching low-power analog comparators independant crystal oscillators reset, interrupt, event sources
Ordering Information
Product
XE88LC06AMI000 XE88LC06AMI014 XE88LC06AMI015 XE88LC06AMI026 XE88LC06ARI000 XE88LC06ARI014 XE88LC06ARI015 XE88LC06ARI026
Temperature range
-40°C -40°C -40°C -40°C -40°C 125°C -40°C 125°C -40°C 125°C -40°C 125°C
Memory type
Package
SO24 SO28 TQFP32 SO24 SO28 TQFP32
years Flash retention 55°C
Cool Solutions Wireless Connectivity
XEMICS e-mail: info@xemics.com web: www.xemics.com
Datasheet XE88LC06
TABLE CONTENTS Chapter Title General overview XE88LC06A performance Memory mapping power modes Reset generator Clock generation Interrupt handler Event handler power Port Port Port Radio Asynchronous Receiver/Transmitter (BitJockey) Universal Asynchronous Receiver/Transmitter (UART) Universal Synchronous Receiver/Transmitter (USRT) Counters/PWM Voltage Level Detector power comparators Dimensions
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Datasheet XE88LC06A
General overview
CONTENTS
1.2.1 1.2.2 1.2.3 schematic TQFP-32 SO-28 XE88LC06A SO-24 assignment
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Datasheet XE88LC06A
schematic
level block schematic circuit shown Figure 1-1. heart circuit consists Coolrisc816 (central processing unit) core. This core includes multiplier internal registers. controller generates control signals access data registers other than internal registers. reset block generates adequate reset signals rest circuit function setup contained control registers. Possible reset sources power-on-reset (POR), external NRESET, watchdog (WD), error detected controller programmable pattern Port clock generation power management block sets clock signals generates internal supplies different blocks. clock generated from oscillator (this start-up condition), crystal oscillator (XTAL) external clock source (given pin). test controller generates set-up signals different test modes. normal operation, used power RAM. power consumption important application, variables that need accessed frequently should stored these registers rather than RAM. handler routes interrupt signals different peripherals inputs core. allows masking interrupt sources flags which interrupt source active. Events generally used restart processor after HALT period without jumping specified address, i.e. program execution resumes with instruction following HALT instruction. handler routes event signals different peripherals inputs core. allows masking event sources flags which event source active. Port parallel port with analog capabilities. USRT, UART, CMPD blocks also make this port. instruction memory 22-bit wide flash memory depending circuit version. case version, used. maximal number instructions this product 8192. data memory this product byte SRAM. port parallel input port. also generate interrupts, events reset. used input external clocks timer/counter/PWM block. Port general purpose parallel port. USRT (universal synchronous receiver/transmitter) contains some simple hardware functions order simplify software implementation synchronous serial link. UART (universal asynchronous receiver/transmitter) contains full hardware implementation asynchronous serial link. RFIF interface serial interface dedicated communication with circuits. From side, very much looks like ordinary UART also implements level coding/decoding frame synchronisation. input/output pins multiplexed port counters/timers/PWM take clocks from internal external sources Port generate interrupts events. output Port
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Datasheet XE88LC06A (voltage level detector) detects battery life with respect programmable threshold. CMPD contains channel comparator. intended monitor analog digital signals whilst having very power consumption.
INSTRUCTION MEMORY
DATA MEMORY
COOLRISC816
VBAT
MULTIPLIER
address control datain
PORT
PA(7:0)
dataout
PORT
PD(7:0)
REGISTERS
NRESET
RESET BLOCK
reset control
USRT
XOUT VREG
XTAL
CLOCK GENERATION/ MANAGEMENT
clocks
UART
test control
VREG
TEST CONTROLLER
TEST
DATA REGISTERS
HANDLING
PB(1:0) PA(3:0)
COUNTERS TIMERS
HANDLING
PORT
PB(7:0)
CMPD
RFIF BitJockey
PD(3:0)
Figure 1-1. Block schematic XE88LC06A circuit.
PB(7:4)
PB(7:6)
PB(5:4)
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Datasheet XE88LC06A
XE88LC06A delivered different packages. maps different packages given below. 1.2.1 TQFP-32
NRESET
PD(2)
PA(2)
PA(1)
PD(1)
PB(1)
PB(0)
PB(2) PB(3) PD(3) PA(3) PA(4) PD(4) PB(4) PB(5)
PD(0) PA(0) VBAT XOUT PA(7) PD(7)
Figure 1-2. TQFP-32 1.2.2 SO-28
PD(2)/PA(2) PB(0) PB(1) PB(2) PB(3) PD(3) PA(3) PA(4) PD(4) PB(4) PB(5) PB(6) PB(7) PD(5)/PA(5)
VREG
PB(6)
PB(7)
PD(5)
PA(5)
PA(6)
PD(6)
TEST
PA(1)/PD(1) NRESET PD(0) PA(0) VBAT XOUT PA(7) PD(7) VREG TEST
PA(6)/PD(6)
Figure 1-3. SO28 SO-28 package, pins Port Port connected together. user choose between functionality Port Port these pins. Note: pins PD(1), PD(2), PD(5), PD(6) used output, pull corresponding Port should disabled order have power consumption.
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Datasheet XE88LC06A 1.2.3 XE88LC06A SO-24
PD(2)/PA(2) PB(0) PB(1) PB(2) PB(3) PD(3)/PA(3) PD(4)/PA(4) PB(4) PB(5) PB(6) PB(7) PD(5)/PA(5)
PA(1)/PD(1) NRESET PA(0)/PD(0) VBAT XOUT PA(7)/PD(7) VREG TEST
PA(6)/PD(6)
Figure 1-4. SO24 SO-24 package, pins Port Port connected together. user choose between functionality Port Port Note: pins Port used output, pull corresponding Port should disabled order have power consumption.
assignment
table below gives short description different assignments. VBAT VREG NRESET TEST XIN/XOUT PA(7:0) PB(7:0) PD(7:0) Assignment Positive power supply Negative power supply Connection mandatory external capacitor voltage regulator High voltage supply flash memory programming versions) Resets circuit when voltage Sets flash programming mode Quartz crystal connections, also used flash memory programming Parallel input port pins Parallel port pins Parallel port pins
Table 1-1. assignment
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Datasheet XE88LC06A
XE88LC06A performance
CONTENTS
2.4.1 2.4.2 Absolute maximum ratings Operating range Current consumption Operating speed Flash circuit version circuit version
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Datasheet XE88LC06A
Absolute maximum ratings
Table 2-1. Absolute maximal ratings Min. Voltage applied VBAT with respect Voltage applied with respect Voltage applied pins except VBAT Storage temperature (ROM device unprogrammed flash device) Storage temperature (programmed flash device) -0.3 VBAT-0.3 VSS-0.3 Max. VBAT+0.3 Note
Stresses beyond absolute maximal ratings cause permanent damage device. Functional operation absolute maximal ratings implied. Exposure conditions beyond absolute maximal ratings affect reliability device.
Operating range
Table 2-2. Operating range flash device Min. Max. Note Voltage applied VBAT with respect Voltage applied VBAT with respect during flash programming Voltage applied with respect VBAT 11.5 Voltage applied pins except VBAT VBAT Operating temperature range Capacitor VREG During programming device, supply voltage should least equal supply voltage used during normal operation, temperature between 10°C 40°C. Table 2-3. Operating range device Min. Max. Note Voltage applied VBAT VREG by-passed with respect VREG Voltage applied pins except VBAT VBAT Operating temperature range Capacitor VREG capacitor omitted when VREG connected VBAT.
specifications this document valid complete operating range unless otherwise specified. Table 2-4. Operating range Flash memory Min. Max. Note Retention time 85°C years Retention time 55°C years Number programming cycles Valid only programmed using programming tool that qualified Circuits programmed more than times that case, retention time longer guaranteed.
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Datasheet XE88LC06A
Current consumption
tables below give current consumption circuit different configurations. figures indicative only change function actual software implemented circuit. Table gives current consumption flash version circuit. peripherals (USRT, UART, CNT, VLD, CMPD) disabled. parallel ports configured input with pull Their pins connected externally. Table 2-5. Typical current consumption XE88LC06AM version instructions flash memory) Operation mode High speed MIPS Xtal Consumption 11.0 14.5 comments 2.4V<>5.5V, 27°C Note
speed
MIPS
2.4V <>5.5V, 27°C
power
kIPS
2.4V <>5.5V, 27°C
power time keeping Fast wake-up time keeping Immediate wakeup time keeping static current CMPD static current
HALT HALT HALT
Ready
32kHz
2.4V <>5.5V, 27°C 2.4V <>5.5V, 27°C 2.4V <>5.5V, 27°C 2.4V <>5.5V, 27°C 2.4V <>5.5V, 27°C
Software without data access 100% power access 100% access typical software
Table shows typical current consumption version with instructions. possible modes possible: 2.4V-5.5V operating range using internal regulator 1.2V3.3V operating range short circuiting voltage regulator (i.e. connect VREG VBAT). Table 2-6. Current consumption XE88LC06AR version instructions memory) Operation mode High speed Max. Speed speed power voltage power time keeping MIPS MIPS MIPS kIPS kIPS HALT Xtal Consumption comments 2.4V<>5.5V, 27°C 2.4V<>5.5V, 27°C 2.4V <>5.5V, 27°C 2.4V <>5.5V, 27°C 1.2V, 27°C 2.4V <>5.5V, 27°C Note
Software using MOVE instruction using internal registers peripheral registers. Using internal voltage regulator (see Figure 2-3). With internal regulator short circuited (i.e. connecting VREG VBAT, Figure 2-5). this case, current consumption will increase with VBAT.
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Datasheet XE88LC06A Hints power operation: power instead parameters that accessed frequently. average current consumption power about times lower than RAM. Rather than using circuit speed, better circuit higher speed switch blocks when needed. power consumption program memory important part overall power consumption. case intend version power consumption high, please provide with circuit version with smaller size.
2.4.1
Operating speed
Flash circuit version
speed flash devices highly dependent upon supply voltage. However, limiting temperature range, speed increased. minimal guaranteed speed function supply voltage maximal temperature operating temperature given Figure 2-2.
VBAT VREG
Figure 2-1. Supply configuration flash circuit operation.
speed (MIPS)
85°C
45°C
supply voltage VBAT
Figure 2-2. Guaranteed speed function supply voltage maximal temperature.
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Datasheet XE88LC06A
2.4.2
circuit version, regulator
version, possible operating modes exist: with without voltage regulator. Using voltage regulator, power consumption will obtained even with supply voltages above 2.4V. Without voltage regulator (i.e. VREG short-circuited VBAT) higher speed obtained.
VBAT VREG 100nF
Figure 2-3. Supply configuration circuit operation using internal regulator.
85°C speed (MIPS) supply voltage VBAT 45°C 125°C
Figure 2-4. Guaranteed speed function supply voltage different maximal temperatures using voltage regulator.
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Datasheet XE88LC06A
2.4.3
circuit version, regulator by-passed
VBAT VREG
Figure 2-5. Supply configuration circuit operation by-passing internal regulator.
85°C speed (MIPS)
45°C
125°C
supply voltage VBAT
Figure 2-6. Guaranteed speed function supply voltage temperature ranges when VREG=VBAT.
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Datasheet XE88LC06A
CONTENTS
description internal registers instruction short reference
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Datasheet XE88LC06A
description
XE8000 series power RISC core. internal registers efficient implementation compiler. instruction made generic instructions, coded bits, with addressing modes. instructions executed clock cycle, including conditional jumps multiplication. circuit therefore runs MIPS 1MHz clock. hardware software description given document "Coolrisc816 Hardware Software Reference Manual". short summary given following paragraphs. good code efficiency core makes possible compute polynomial like less than clock cycles (software code generated XEMICS C-compiler, numbers signed integers bits).
internal registers
shown Figure 3-1, internal 8-bit registers. Some these registers concatenated 16-bit word some instructions. function these registers defined Table 3-1. status register stat (Table 3-2) used manage different interrupt event levels. interrupt event both used wake after HALT instruction. difference that interrupt jumps special interrupt function whereas event continues software execution with instruction following HALT instruction. program counter (PC) register that indicates address instruction that executed. stack (STn) used memorise return address when executing subroutines interrupt routines.
program counter stack instruction
stat data internal registers
Instruction memory 22bit
Data memory
Figure 3-1. internal registers
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Datasheet XE88LC06A
Register name stat
Register function general purpose general purpose general purpose data memory offset data memory index data memory index data memory index data memory index data memory index data memory index data memory index data memory index program memory index program memory index status register accumulator
Table 3-1. internal register definition name function enables (when interrupt request level enables (when interrupt request level enables (when interrupt request levels interrupt request level interrupts labelled "low" interrupt handler routed this interrupt level. This cleared when interrupt served. interrupt request level interrupts labelled "mid" interrupt handler routed this interrupt level. This cleared when interrupt served. interrupt request level interrupts labelled "hig" interrupt handler routed this interrupt level. This cleared when interrupt served. event request level events labelled "low" event handler routed this event level. This cleared when event served. event request level events labelled "hig" event handler routed this event level. This cleared when event served.
Table 3-2. Status register description also number flags that used conditional jumps. These flags defined Table 3-3. symbol name zero carry function when accumulator content zero This flag used shift arithmetic operations. shift operation, value that shifted (LSB shift right, shift left). arithmetic operation with unsigned numbers: occurrence overflow during addition equivalent). occurrence underflow during subtraction equivalent). This flag used shift arithmetic operations. arithmetic shift operations with signed numbers, overflow underflow occurs.
overflow
Table 3-3. Flag description
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Datasheet XE88LC06A
instruction short reference
Table shows short description different instructions available Coolrisc816. notation conditional jump instruction refers condition description given Table 3-6. notation reg, reg1, reg2, reg3 refers internal registers Table 3-1. notation eaddr DM(eaddr) refer extended address modes defined Table 3-5. notation DM(xxx) refers data memory location with address xxx.
Instruction
Jump addr[15:0] Jump addr[15:0] Call addr[15:0] Call Calls addr[15:0] Calls Rets Reti Push Move reg,#data[7:0] Move reg1, reg2 Move reg, eaddr Move eaddr, Move addr[7:0],#data[7:0] Cmvd reg1, reg2 Cmvd reg, eaddr Cmvs reg1, reg2 Cmvs reg, eaddr reg1, reg2 reg, eaddr Shlc reg1, reg2 Shlc Shlc reg, eaddr reg1, reg2 reg, eaddr Shrc reg1, reg2 Shrc Shrc reg, eaddr Shra reg1, reg2 Shra Shra reg, eaddr Cpl1 reg1, reg2 Cpl1 Cpl1 reg, eaddr Cpl2 reg1, reg2 Cpl2 Cpl2 reg, eaddr Cpl2c reg1, reg2 Cpl2c Cpl2c reg, eaddr reg1, reg2 reg, eaddr Incc reg1, reg2 Incc Incc reg, eaddr
Modification
-,-,-, -,-,-, -,-,-, -,-,-, -,-,-, -,-,-, -,-,-, -,-,-, -,-,-, -,-,-, -,-,-, -,-,-, -,-,-, -,-, -,-, -,-, -,-,-, -,-,-, -,-, -,-, -,-, -,-, -,-, -,-, -,-,
Operation
addr[15:0] true then addr[15:0] true then STn+1 (n>1); PC+1; addr[15:0] STn+1 (n>1); PC+1; PC+1; addr[15:0] PC+1; ST1; STn+1 (n>1) ST1; STn+1 (n>1); PC+1; STn+1 (n>1); PC+1; ST1; STn+1 (n>1) data[7:0]; data[7:0] reg2; reg1 reg2 DM(eaddr); DM(eaddr) DM(eaddr) DM(addr[7:0]) data[7:0] reg2; then reg1 DM(eaddr); then reg2; then reg1 DM(eaddr); then reg2<<1; a[0] reg2[7]; reg1 reg<<1; a[0] reg[7]; DM(eaddr)<<1; a[0] :=0; DM(eaddr)[7]; reg2<<1; a[0] reg2[7]; reg1 reg<<1; a[0] reg[7]; DM(eaddr)<<1; a[0] DM(eaddr)[7]; reg2>>1; a[7] reg2[0]; reg1 reg>>1; a[7] reg[0]; DM(eaddr)>>1; a[7] DM(eaddr)[0]; reg2>>1; a[7] reg2[0]; reg1 reg>>1; a[7] reg[0]; DM(eaddr)>>1; a[7] DM(eaddr)[0]; reg2>>1; a[7] reg2[7]; reg2[0]; reg1 reg>>1; a[7] reg[7]; reg[0]; DM(eaddr)>>1; a[7] DM(eaddr)[7]; DM(eaddr)[0]; NOT(reg2); reg1 NOT(reg); NOT(DM(eaddr)); NOT(reg2)+1; then C:=1 else reg1 NOT(reg)+1; then C:=1 else NOT(DM(eaddr))+1; then C:=1 else NOT(reg2)+C; then C:=1 else reg1 NOT(reg)+C; then C:=1 else NOT(DM(eaddr))+C; then C:=1 else reg2+1; then else reg1 reg+1; then else DM(eaadr)+1; then else reg2+C; then else reg1 reg+C; then else DM(eaadr)+C; then else
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Datasheet XE88LC06A
reg1, reg2 reg, eaddr Decc reg1, reg2 Decc Decc reg, eaddr reg,#data[7:0] reg1, reg2, reg3 reg1, reg2 reg, eaddr reg,#data[7:0] reg1, reg2, reg3 reg1, reg2 reg, eaddr reg,#data[7:0] reg1, reg2, reg3 reg1, reg2 reg, eaddr reg,#data[7:0] reg1, reg2, reg3 reg1, reg2 reg, eaddr Addc reg,#data[7:0] Addc reg1, reg2, reg3 Addc reg1, reg2 Addc reg, eaddr Subd reg,#data[7:0] Subd reg1, reg2, reg3 Subd reg1, reg2 Subd reg, eaddr Subdc reg,#data[7:0] Subdc reg1, reg2, reg3 Subdc reg1, reg2 Subdc reg, eaddr Subs reg,#data[7:0] Subs reg1, reg2, reg3 Subs reg1, reg2 Subs reg, eaddr Subsc reg,#data[7:0] Subsc reg1, reg2, reg3 Subsc reg1, reg2 Subsc reg, eaddr reg,#data[7:0] reg1, reg2, reg3 reg1, reg2 reg, eaddr Mula reg,#data[7:0] Mula reg1, reg2, reg3 Mula reg1, reg2 Mula reg, eaddr Mshl reg,#shift[2:0] Mshr reg,#shift[2:0] Mshra reg,#shift[2:0] reg,#data[7:0] reg1, reg2 reg, eaddr Cmpa reg,#data[7:0] Cmpa reg1, reg2 Cmpa reg, eaddr Tstb reg,#bit[2:0] Setb reg,#bit[2:0] Clrb reg,#bit[2:0] Invb reg,#bit[2:0]
-,-, -,-, -,-, -,-, -,-, -,-, -,-, -,-, -,-, -,-, -,-, -,-,
reg2-1; a=hFF then else reg1 reg-1; a=hFF then else DM(eaddr)-1; a=hFF then else reg2-(1-C); a=hFF then else reg1 reg-(1-C); a=hFF then else DM(eaddr)-(1-C); a=hFF then else data[7:0]; reg2 reg3; reg1 reg1 reg2; reg1 DM(eaddr); data[7:0]; reg2 reg3; reg1 reg1 reg2; reg1 DM(eaddr); data[7:0]; reg2 reg3; reg1 reg1 reg2; reg1 DM(eaddr); reg+data[7:0]; overflow then C:=1 else reg2+reg3; overflow then C:=1 else reg1 reg1+reg2; overflow then C:=1 else reg1 reg+DM(eaddr); overflow then C:=1 else reg+data[7:0]+C; overflow then C:=1 else reg2+reg3+C; overflow then C:=1 else reg1 reg1+reg2+C; overflow then C:=1 else reg1 reg+DM(eaddr)+C; overflow then C:=1 else data[7:0]-reg; underflow then else reg2-reg3; underflow then else reg1 reg2-reg1; underflow then else reg1 DM(eaddr)-reg; underflow then else data[7:0]-reg-(1-C); underflow then else reg2-reg3-(1-C); underflow then else reg1 reg2-reg1-(1-C); underflow then else reg1 DM(eaddr)-reg-(1-C); underflow then else reg-data[7:0]; underflow then else reg3-reg2; underflow then else reg1 reg1-reg2; underflow then else reg1 reg-DM(eaddr); underflow then else reg-data[7:0]-(1-C); underflow then else reg3-reg2-(1-C); underflow then else reg1 reg1-reg2-(1-C); underflow then else reg1 reg-DM(eaddr)-(1-C); underflow then else (data[7:0]*reg)[7:0]; (data[7:0]*reg)[15:8] (reg2*reg3)[7:0]; reg1 (reg2*reg3)[15:8] (reg2*reg1)[7:0]; reg1 (reg2*reg1)[15:8] (DM(eaddr)*reg)[7:0]; (DM(eaddr)*reg)[15:8] (data[7:0]*reg)[7:0]; (data[7:0]*reg)[15:8] (reg2*reg3)[7:0]; reg1 (reg2*reg3)[15:8] (reg2*reg1)[7:0]; reg1 (reg2*reg1)[15:8] (DM(eaddr)*reg)[7:0]; (DM(eaddr)*reg)[15:8] (reg*2 )[7:0]; (reg*2 )[15:8] (8-shift (8-shift (reg*2 )[7:0]; (reg*2 )[15:8] (8-shift (8-shift (reg*2 )[7:0]; (reg*2 )[15:8] data[7:0]-reg; underflow then else C:=1; (not reg2-reg1; underflow then else C:=1; (not DM(eaddr)-reg; underflow then else C:=1; (not data[7:0]-reg; underflow then else C:=1; (not reg2-reg1; underflow then else C:=1; (not DM(eaddr)-reg; underflow then else C:=1; (not a[bit] reg[bit]; other bits reg[bit] other bits unchanged; reg[bit] other bits unchanged; reg[bit] reg[bit]; other bits unchanged;
shift shift
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Datasheet XE88LC06A
Sflag Rflag Rflag eaddr Freq divn Halt
-,-,-, -,-,-, -,-,-, -,-,-,
a[7] a[6] a[5] full; a[4] empty a[0] reg[7] DM(eaddr)<<1; a[0] :=0; DM(eaddr)[7] reduces frequency (divn=nodiv, div2, div4, div8, div16) halts operation
unchanged, undefined, *MSHR reg,# doesn't shift
Table 3-4. Instruction short reference Coolrisc816 different addressing modes. These modes described Table 3-5. this table, notation refers data memory index registers Using eaddr instruction Table will access data memory address DM(eaddr) will simultaneously execute index operation.
extended address eaddr addr[7:0] (ix) (ix, offset[7:0]) (ix,r3) (ix)+ (ix,offset[7:0])+ -(ix) -(ix,offset[7:0]) accessed data memory location DM(eaddr) DM(h00&addr[7:0]) DM(ix) DM(ix+offset) DM(ix+r3) DM(ix) DM(ix+offset) DM(ix-1) DM(ix-offset) index operation ix+1 ix+offset ix-1 -offset direct addressing indexed addressing indexed addressing with immediate offset indexed addressing with register offset indexed addressing with index post-increment indexed addressing with index post-increment offset indexed addressing with index pre-decrement indexed addressing with index pre-decrement offset
Table 3-5. Extended address mode description Eleven different jump conditions implemented shown Table 3-6. contents column this table should replace notation instruction description Table 3-4.
condition
(EV1 EV0)=1
After op1,op2
op1=op2 op1op2 op1>op2 op1op2 op1<op2 op1op2
Table 3-6. Jump condition description
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Datasheet XE88LC06A
Memory mapping
CONTENTS
4.2.1 4.2.2 4.2.3 4.2.4 4.2.5 4.2.6 4.2.7 4.2.8 4.2.9 4.2.10 4.2.11 4.2.12 4.2.13 4.2.14 4.2.15 Memory organisation Quick reference data memory register power data registers (h0000-h0007) System, clock configuration reset configuration (h0010-h001F) Port (h0020-h0027) Port (h0028-h002F) Port (h0030-h0033) Flash programming (h0038-003B) Event handler (h003C-h003F) Interrupt handler (h0040-h0047) USRT (h0048-h004F) UART (h0050-h0057) Counter/Timer/PWM registers (h0058-h005F) interface (h0060-h0067) Comparator registers (h0072-h0073) Voltage Level Detector registers (h007E-h007F) (h0080-h027F)
LC06A fev. 2002
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Datasheet XE88LC06A
Memory organisation
XE88LC06A build Harvard architecture. Harvard architecture uses separate instruction data memories. instruction data also separated. advantage such structure that fetch instruction read/write data simultaneously. circuit configuration shown Figure 4-1. internal registers. instruction memory capacity 8192 22-bit instructions. data memory space power registers, peripheral register space bytes RAM.
0h1FFF
0h027F
instruction
capacity: bytes
stat data internal registers
capacity: 22bit
0h0080 0h007F Peripheral registers 0h0008 power data registers 0h0000
0h0000
Figure 4-1. Memory mapping internal registers described chapter. short reference power registers peripheral registers given 4.2.
Quick reference data memory register
data register given tables below. more detailed description different registers given detailed description different peripherals. tables give following information: register name register address different bits register access mode different bits (see Table code description) reset source reset value different bits reset source coding given Table 4-2. full description reset sources, please refer reset block chapter. D0209-136
Data memory
Instruction memory
Datasheet XE88LC06A code access mode read written always reads always reads cleared writing value cleared writing cleared after reading special function, verify detailed description respective peripherals
Table 4-1. Access mode codes used register definitions code glob cold pconf sleep reset source nresetglobal nresetcold nresetpconf nresetsleep
Table 4-2. Reset source coding used register definitions 4.2.1
Address Reg00 h0000 Reg01 h0001 Reg02 h0002 Reg03 h0003 Reg04 h0004 Reg05 h0005 Reg06 h0006 Reg07 h0007
power data registers (h0000-h0007)
Name Reg00[7:0] rw,00000000,glob Reg01[7:0] rw,00000000,glob Reg02[7:0] rw,00000000,glob Reg03[7:0] rw,00000000,glob Reg04[7:0] rw,00000000,glob Reg05[7:0] rw,00000000,glob Reg06[7:0] rw,00000000,glob Reg07[7:0] rw,0000000,glob
Table 4-3. power data registers 4.2.2 System, clock configuration reset configuration (h0010-h001F)
EnResetPConf
Name Address RegSysCtrl SleepEn h0010 rw,0,cold RegSysReset Sleep h0011 rw,0,glob RegSysClock CpuSel h0012 rw,0,sleep RegSysMisc h0013 RegSysWD h0014 RegSysPre0 h0015 RegSysRCTrim1 h001B RegSysTrim2 h001C
rw,0,cold SleepFlag rc,0,cold
EnBusError rw,0,cold
ResetBusError
cold EnExtClock rw,0,cold
EnResetWD rw,0,cold ResetWD cold BiasRC rw,1,cold RcFreqRange rw,0,cold
ResetfromportA
cold ColdXtal r,1,sleep
EnableXtal EnableRC rw,0,sleep rw,1,sleep Output16k OutputCpuCk rw,0,sleep rw,0,sleep WatchDog[3:0] s,0000,glob
ClearLowPresca
c1r0,0,r0 RcFreqCoarse[3:0] rw,0001,cold RcFreqFine[5:0] rw,00000,cold
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Datasheet XE88LC06A Table 4-4. Reset block clock block registers 4.2.3
Address RegPAIn h0020 RegPADebounce h0021 RegPAEdge h0022 RegPAPullup h0023 RegPARes0 h0024 RegPARes1 h0025 RegPACtrl h0026 RegPASnapToRail h0027
Port (h0020-h0027)
Name PAIn[7:0] PADebounce[7:0] rw,00000000,pconf PAEdge[7:0] rw,00000000,glob PAPullup[7:0] rw,11111111,pconf PARes0[7:0] 00000000, glob PARes1[7:0] rw,00000000,glob PASnapToRail[7:0] rw,00000000,pconf
DebFast rw,0,pconf
Table 4-5. Port registers 4.2.4
Address RegPBOut h0028 RegPBIn h0029 RegPBDir h002A RegPBOpen h002B RegPullup h002C RegPBAna h002D
Port (h0028-h002F)
Name PBOut[7:0] rw,00000000,pconf PBIn[7:0] PBDir[7:0] rw,00000000,pconf PBOpen[7:0] rw,00000000,pconf PBPullup[7:0] rw,11111111,pconf PBAna[7:0] rw,00000000,pconf
Table 4-6. Port registers 4.2.5
Address RegPDOut h0030 RegPDIn h0031 RegPDDir h0032 RegPDPullup h0033 PDSnapToRail[3:0] rw,0000,pconf
Port (h0030-h0033)
Name PDOut[7:0] rw,00000000,pconf PDIn[7:0] PDDir[7:0] rw,00000000,pconf
PDPullup[3:0] rw,1111,pconf
Table 4-7. Port registers 4.2.6 Flash programming (h0038-003B)
These four registers used during flash programming only. Refer flash programming algorithm documentation more details.
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Datasheet XE88LC06A
4.2.7
Address
Event handler (h003C-h003F)
Name RegEvn CntIrqA rc1,0,glob CntIrqC rc1,0,glob 128Hz rc1,0,glob PAEvn[1] CntIrqB rc1,0,glob rc1,0,glob EvnEn[7:0] rw,00000000,glob EvnPriority[7:0] r,11111111,glob CntIrqD rc1,0,glob rc1,0,glob PAEvn[0] rc1,0,glob
h003C RegEvnEn h003D RegEvnPriority h003E RegEvnEvn h003F
EvnHigh r,0,glob
EvnLow r,0,glob
Table 4-8. Event handler registers origin different events summarised table below. Event CntIrqA CntIrqB CntIrqC CntIrqD 128Hz PAEvn[1:0] Event source Counter/Timer (counter block) Counter/Timer (counter block) Counter/Timer (counter block) Counter/Timer (counter block) prescaler (clock block) prescaler (clock block) Port
Table 4-9. Event source description 4.2.8
Address
Interrupt handler (h0040-h0047)
Name 128Hz rc1,0,glob UrstCond1 rc1,0,glob PAIrq[6] rc1,0,glob RfifTx rc1,0,glob PAIrq[5] rc1,0,glob CntIrqB rc1,0,glob CntIrqA CntIrqC rc1,0,glob rc1,0,glob PAIrq[4] rc1,0,glob rc1,0,glob CntIrqD PAIrq[3] rc1,0,glob rc1,0,glob IrqEnHig[7:0] rw,0000000,glob IrqEnMid[7:0] rw,0000000,glob IrqEnLow[7:0] rw,0000000,glob IrqPriority[7:0] r,11111111,glob CmpdIrq rc1,0,glob VldIrq rc1,0,glob PAIrq[2] rc1,0,glob UartIrqTx rc1,0,glob PAIrq[1] rc1,0,glob UartIrqRx rc1,0,glob PAIrq[0] rc1,0,glob
RfifRx h0040 rc1,0,glob RegIrqMid UsrtCond2 h0041 rc1,0,glob RegIrqLow PAIrq[7] h0042 rc1,0,glob RegIrqEnHig h0043 RegIrqEnMid h0044 RegIrqEnLow h0045 RegIrqPriority h0046 RegIrqIrq h0047 RegIrqHig
IrqHig r,0,glob
IrqMid r,0,glob
IrqLow r,0,glob
Table 4-10. Interrupt handler registers origin different interrupts summarised table below.
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Datasheet XE88LC06A
Interrupt CmpdIrq CntIrqA CntIrqB CntIrqC CntIrqD 128Hz PAIrq[7:0] RfifRx RfifTx UartIrqRx UartIrqTx UsrtCond1 UsrtCond2 VldIrq
Interrupt source power comparators Counter/Timer (counter block) Counter/Timer (counter block) Counter/Timer (counter block) Counter/Timer (counter block) prescaler (clock block) prescaler (clock block) Port interface reception interface transmission UART reception UART transmission USRT condition USRT condition Voltage level detector
Table 4-11. Interrupt source description 4.2.9
Address RegUsrtS1 h0048 RegUsrtS0 h0049 RegUsrtCtrl h004A RegUsrtCond1 h004B RegUsrtCond2 h004C RegUsrtBufferS1 h004D RegUsrtEdgeS0 h004E UsrtWaitS0 r,0,glob
UsrtEnWaitCond1
USRT (h0048-h004F)
Name UsrtS1 s,1,glob UsrtS0 s,1,glob UsrtEnWaitS0 UsrtEnable rw,0,glob rw,0,glob UsrtCond1 rc,0,glob UsrtCond2 rc,0,glob UsrtBufferS1 r,0,glob UsrtEdgeS0 r,0,glob
rw,0,glob
Table 4-12. USRT register description 4.2.10 UART (h0050-h0057)
UartEcho rw,0,glob SelXtal rw,0,glob UartEnRx rw,0,glob UartEnTx rw,0,glob UartXRx UartXTx rw,0,glob rw,0,glob UartRcSel[2:0] rw,000,glob UartTx[7:0] rw,0000000,glob UartPM rw,0,glob UartBR[2:0] rw,101,glob UartPE rw,0,glob UartWL rw,1,glob
Name Address RegUartCtrl h0050 RegUartCmd h0051 RegUartTx h0052 RegUartTxSta h0053 RegUartRx h0054 RegUartRxSta h0055
UartTxBusy UartTxFull r,0,glob r,0,glob UartRx[7:0] r,00000000,glob UartRxSErr UartRxPErr UartRxFErr UartRxOerr UartRxBusy UartRxFull r,0,glob r,0,glob r,0,glob rc,0,glob r,0,glob r,0,glob
Table 4-13. UART register description
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Datasheet XE88LC06A
4.2.11
Address
Counter/Timer/PWM registers (h0058-h005F)
Name RegCntA CounterA[7:0] s,00000000,glob CounterB[7:0] s,00000000,glob CounterC[7:0] s,00000000,glob CounterD[7:0] s,00000000,glob CntDCkSel[1:0] CntCCkSel[1:0] CntBCkSel[1:0] CntACkSel[1:0] rw,00,glob rw,00,glob rw,00,glob rw,00,glob CntDDownUp CntCDownUp CntBDownUp CntADownUp CascadeCD CascadeAB CntPWM1 CntPWM0 rw,0,glob rw,0,glob rw,0,glob rw,0,glob rw,0,glob rw,0,glob rw,0,glob rw,0,glob CapSel[1:0] CapFunc[1:0] Pwm1Size[1:0] Pwm0Size[1:0] rw,00,glob rw,00,glob rw,00,glob rw,00,glob CntDExtDiv CntCExtDiv CntBExtDiv CntAExtDiv CntDEnable CntCEnable CntBEnable CntAEnable rw,0,glob rw,0,glob rw,0,glob rw,0,glob rw,0,glob rw,0,glob rw,0,glob rw,0,glob
h0058 RegCntB h0059 RegCntC h005A RegCntD h005B RegCntCtrlCk h005C RegCntConfig1 h005D RegCntConfig2 h005E RegCntOn h005F
Table 4-14. Counter/timer/PWM register description. 4.2.12 interface BitJockey (h0060-h0067)
RfifBRCoarse[1:0] RfifBRFine[3:0] rw,00,glob rw,0000,glob RfifEnStart[1:0] RfifEnCod RfifRxClock RfifTxClock RfifPCM[2:0] rw,00,glob rw,0,glob rw,0,glob rw,0,glob rw,000,glob RfifRxIrqEn[2:0] RfifRxIrqMem[2:0] RfifEnTx RfifEnRx rw,000,glob rc1,000,glob rw,0,conf rw,0,conf RfifTx wr0,00000000,glob RfifTxFifoOverrun RfifTxFifoFull RfifTxFifoEmpty RfifTxStopped rc1,0,glob r,1,glob r,0,glob r,0,glob RfifRx r,00000000,glob RfifRxFifoOverrun RfifRxFifoFull RfifRxStartDet RfifRxBusy RfifRxReady rc1,0,glob r,0,glob r,0,glob rc1,0,glob r,0,glob RfifSPat[7:0] rw,0000000,glob
Name Address RegRfifCmd1 h0060 RegRfifCmd2 h0061 RegRfifCmd3 h0062 RegRfifTx h0063 RegRfifTxSta h0064 RegRfifRx h0065 RegRfifRxSta h0066 RegRfifSPat h0067
Table 4-15. interface (Rfif) register description. 4.2.13 Comparator registers (h0072-h0073)
CmpdStat[3:0] rca,0000,glob IrqOnRising[2:0] rw,000,glob CmpdOut[3:0] r,0000,glob EnIrqCh[3:0] rw,0000,glob Enable rw,0,glob
Name Address RegCmpdStat h0072 RegCmpdCtrl h0073
Table 4-16. power comparator registers
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Datasheet XE88LC06A
4.2.14
Address
Voltage Level Detector registers (h007E-h007F)
Name RegVldCtrl RegVldStat VldRange rw,0,glob VldTune[2:0] rw,000,glob VldResult VldValid r,0,glob r,0,glob VldEn rw,0,glob
h007E h007F
Table 4-17. Voltage level detector register description 4.2.15 (h0080-h027F)
bytes accessed read write operations. reset function. Variables stored should initialised before since they have value circuit start
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Datasheet XE88LC06A
power modes
5.1.1
power modes. Features Overview Operating mode
power modes 1.2- janvier 2001 D0209-136
Datasheet XE88LC06A
5.1.1
Features
Overview
XE8000 chips have three operating modes. These normal, current very current modes (see Figure 5-1). different modes controlled reset clock blocks (see documentation respective blocks).
Operating mode
Start-up bits reset design when padnreset active. enabled, Xtal disabled reset (pmaddr 0000). port used return from sleep mode, bits with nresetcold change (see sleep mode) Start-up bits with nresetglobal nresetpconf(if enabled) reset. Clock configuration doesn't change except cpuck (freqdiv reset, clock block). reset Active mode This mode where peripherals work execute embedded software. Standby mode Executing HALT instruction moves XE8000 into Standby mode. stopped, clocks remain active. Therefore, enabled peripherals remain active e.g. time keeping. reset interrupt/event request enabled) cancels standby mode. Sleep mode This very low-power mode because circuit clocks peripherals stopped. Only some service blocks remain active. time-keeping possible. instructions necessary move into sleep mode. First, SleepEn (sleep enable) RegSysCtrl sleep mode then activated setting Sleep RegSysReset There three possibe ways wake-up from sleep mode: (power-on-reset caused power-down followed power-on). information lost. padnreset Port reset combination Port present product). Port documentation more details. Note: Port used return from sleep mode, bits with nresetcold change (RegSysCtrl, RegSysReset (except sleep), Enextclock Biasrc RegSysClock, RegSysRcTrim1 RegSysRcTrim2). SleepFlag RegSysReset, reads back circuit sleep mode since flag last cleared (see reset block more details). recommended insert instruction after instruction that sets circuit sleep mode because this instruction executed when sleep mode left using resetfromportA.
Note:
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Datasheet XE88LC06A
START-UP
without condition
padnreset
RESET
padnreset without condition portA reset watchdog reset buserror reset
padnreset padnreset portA reset
portA reset watchdog reset
Halt instruction
ACTIVE
Interrupt/event
STAND-BY
SLEEP
sleep
normal mode
current
very current
Figure 5-1. XE8000 operating modes.
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Datasheet XE88LC06A
Reset generator
6.5.1 6.5.2 6.5.3 6.5.4 6.5.5
Features Overview Register Reset handling capabilities Reset source description Power Reset NRESET Programmable Port input combination Watchdog reset BusError reset Sleep mode Control register description operation Watchdog Start-up watchdog specifications
Reset generator novembre 2000
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Datasheet XE88LC06A
Features
Power Reset (POR) External reset from NRESET Programmable Watchdog timer reset Programmable BusError reset Sleep mode management
Product dependant: Programmable Port input combination reset
Overview
reset block reset manager. handles different reset sources distributes them through system. also controls sleep mode circuit.
Register
register name RegSysCtrl RegSysReset RegSysWD Table 6-1. Reset registers Table gives different registers used this block.
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Datasheet XE88LC06A
Pos.
RegSysCtrl SleepEn EnResetPConf
Reset nresetcold nresetcold
EnBusError EnResetWD
nresetcold nresetcold
0000
Function enables Sleep mode sleep mode disabled sleep mode enabled enables nresetpconf signal when nresetglobal active nresetpconf disabled nresetpconf enabled enables reset from BusError BusError reset source disabled BusError reset source enabled enables reset from Watchdog Watchdog reset source disabled Watchdog reset source enabled this unused
Table 6-2. RegSysCtrl register.
Pos.
RegSysReset Sleep SleepFlag ResetBusError ResetWD ResetfromportA
Reset nresetglobal nresetcold nresetcold nresetcold nresetcold
Function Sleep mode control (reads always Sleep mode active before reset source BusError reset source Watchdog reset source Port combination unused
Table 6-3. RegSysReset register
Pos.
RegSysWD WDKey[3] WDCounter[3] WDKey[2] WDCounter[2] WDKey[1] WDCounter[1] WDKey[0] WDCounter[0]
Reset 0000 nresetglobal nresetglobal nresetglobal nresetglobal
Function unused
Watchdog Watchdog counter Watchdog Watchdog counter Watchdog Watchdog counter Watchdog Watchdog counter
Table 6-4. RegSysWD register
Reset handling capabilities
There reset sources: Power Reset (POR) External reset from NRESET Programmable port input combination Programmable watchdog timer reset Programmable BusError reset processor access outside allocated memory
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Datasheet XE88LC06A Another reset source Sleep RegSysReset register. This source fully controlled software only used during sleep mode. Four internal reset signals generated from these sources distributed through system: nresetcold: asserted NRESET nresetglobal: asserted when nresetcold other enabled reset source active nresetsleep: asserted when circuit sleep mode nresetpconf: asserted when nresetglobal active EnResetPConf RegSysCtrl register set. This reset generally used different ports. allows maintain port configuration unchanged while rest circuit reset. Table shows summary dependency internal reset signals various reset sources. tables describing different registers, reset source indicated. Internal reset signals Asserted reset source NRESET PortA input Watchdog BusError Sleep nresetglobal Asserted Asserted Asserted Asserted Asserted nresetpconf when when EnResetPConf EnRestPConf Asserted Asserted Asserted Asserted Asserted Asserted Asserted nresetsleep Asserted Asserted Asserted nresetcold Asserted Asserted
Table 6-5. Internal reset assertion function reset source.
6.5.1
Reset source description
Power Reset
power reset (POR) monitors external supply voltage. activates reset rising edge this supply voltage. reset inactivated only internal voltage regulator started block performs precise voltage level detection. 6.5.2 NRESET
Applying input state NRESET activate reset. 6.5.3 Programmable Port input combination
Port present product) generate reset signal. description Port further information. 6.5.4 Watchdog reset
Watchdog will generate reset EnResetWD RegSysCtrl register been watchdog cleared time processor. chapter describing watchdog further information.
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Datasheet XE88LC06A 6.5.5 BusError reset
address space assigned shown register product. EnBusError RegSysCtrl register software accesses unused address, reset generated.
Sleep mode
Entering sleep mode will reset part circuit. reset used configure circuit correct wake-up after sleep mode. SleepEn RegSysCtrl register been set, sleep mode entered setting Sleep RegSysReset. During sleep mode, nresetsleep signal active. detailed information sleep mode, system documentation.
Control register description operation
registers dedicated reset status control, RegSysReset RegSysCtrl. bits Sleep, SleepFlag SleepEn also located those registers described chapter dedicated different operating modes circuit (system block). RegSysReset register gives information source that generated last reset. read beginning application program detect circuit recovering from error exception condition, circuit starting normally. when ResetBusError forbidden address access generated reset. when ResetWD watchdog generated reset. when ResetfromPortA PortA combination generated reset. Note: reset source either NRESET internal POR. Note: Several bits might not, register cleared between reset occurrences. other bits concern sleep mode control information (see system documentation sleep mode description). When SleepFlag sleep mode active before reset occurred. This will always appear together with ResetfromPortA since other possibilities leave sleep mode (POR NRESET pin) will clear SleepFlag. When Sleep SleepEn sleep mode entered. always reads back RegSysCtrl register enables different available reset sources sleep mode. EnBusError enables reset error condition. EnResetWD enables reset watchdog (can disabled once enabled). EnResetPConf enables reset port configurations when reset Port Error watchdog. SleepEn unlocks Sleep bit. long SleepEn Sleep effect.
Watchdog
watchdog timer, which cleared least every seconds software prevent reset generated timeout condition. watchdog enabled software setting EnResetWD RegSysCtrl register then only disabled power reset setting NRESET state.
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Datasheet XE88LC06A watchdog timer cleared writing consecutively values Hx0A Hx03 RegSysWD register. sequence must strictly respected clear watchdog. assembler code, sequence clear watchdog move AddrRegSysWD, #0x0A move AddrRegSysWD, #0x03 Only writing Hx0A followed Hx03 resets some other write instruction done RegSysWD between writing Hx0A Hx03 values, watchdog timer will cleared. possible read status watchdog RegSysWD register. watchdog counter with count range between system reset generated when counter reaching value
Start-up watchdog specifications
start-up circuit, block generates reset signal during tPOR. circuit starts software execution after this period (see system chapter). intended force circuit into correct state start-up. precise monitoring supply voltage, voltage level detector (VLD) used. Symbol TPOR Vbat_sl WDtime Parameter reset duration Supply ramp Watchdog timeout period Unit V/ms Comments
Table Electrical timing specifications Note: Vbat_sl defines minimum slope required VBAT. Correct start-up circuit guaranteed this slope slow. such case, delay built using NRESET pin. Note: minimal watchdog timeout period guaranteed when internal oscillators used. case external clock source used, watchdog timeout period will correct contents RegSysRCTrim1 RegSysRCTrim2 registers correct (see clock block documentation more details).
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Datasheet XE88LC06A
nresetcold ckmstr ckslv prenresetorsynch buserror resetfromwd bitbuserror bitresetfromwd resetporta
flagnresetcold bitresetfromporta
reset writing regsysreset.
RegSysReset clear software before reset signal, register RegSysReset will false. databitresetfromporta enableregsysreset (bistresetfromporta not(bitresetfromwd bitresetbuserror prenresetorsynch flagnresetcold))
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Datasheet XE88LC06A
Clock generation
7.6.1 7.6.2 7.6.3 7.7.1 7.7.2 7.8.1 7.8.2 7.10 7.11
Clock generation. Features. Overview. Register Interrupts events map. Clock sources oscillator Configuration oscillator frequency tuning. oscillator specifications. Xtal oscillator Xtal configuration. Xtal oscillator specifications. External clock External clock configuration. External clock specification Clock source selection. Prescalers. frequency selector 7-10
Clock generation janvier 2001 D0209-136
Datasheet XE88LC06A
Features
available clock sources oscillator, quartz oscillator external clock). divider chains: high-prescaler bits) low-prescaler bits). clock disabling halt mode.
Overview
XE88LCxx chips work different clock sources oscillator, quartz oscillator external clock). clock generator block charge distributing necessary clock frequencies circuit. Figure represents functionality clock block. internal oscillator external clock source selected drive high prescaler. This prescaler generates frequency divisions down 1/256 input frequency. 32kHz clock generated enabling quartz oscillator present product) selecting appropriate high prescaler. prescaler generates clock signals from 32kHz down 1Hz. clock source selected from oscillator, external clock 32kHz clock.
Register
pos. RegSysClock CpuSel EnExtClock BiasRc ColdXtal EnableXtal EnableRc reset nresetsleep nresetcold nresetcold nresetsleep nresetsleep nresetsleep function Select speed cpuck Unused Enable external clock Enable Rcbias (reduces start-up time RC). Xtal start phase Unused Enable Xtal oscillator Enable oscillator
Table 7-1: RegSysClock register pos. RegSysMisc -Output16k OutputCpuCk reset 000000 nresetsleep nresetsleep function Unused Output signal PB[3] Output clock PB[2]
Table 7-2: RegSysMisc register pos. RegSysPre0 -ClearLowPrescal reset 0000000 function Unused Write reset prescaler, always reads
Table 7-3: RegSysPre0 register
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Datasheet XE88LC06A
pos.
RegSysRcTrim1 -RcFreqRange RcFreqCoarse[3] RcFreqCoarse[2] RcFreqCoarse[1] RcFreqCoarse[0]
reset nresetcold nresetcold nresetcold nresetcold nresetcold
function Unused Low/high freq. range (low=0) coarse trim coarse trim coarse trim coarse trim
Table 7-4: RegSysRCTrim1 register pos. RegSysRcTrim2 -RcFreqFine[5] RcFreqFine[4] RcFreqFine[3] RcFreqFine[2] RcFreqFine[1] RcFreqFine[0] reset nresetcold nresetcold nresetcold nresetcold nresetcold nresetcold function Unused fine trim fine trim fine trim fine trim fine trim fine trim
Table 7-5: RegSysRCTrim2 register pos. RegSysPtckmode -Reserved reset 0000000 nresetglobal function Unused Reserved
Table 7-6: RegSysPtckmode register
Interrupts events
interrupt source ck128Hz ck1Hz Default mapping interrupt manager RegIrqHig(6) RegIrqMid(3) Table 7-7: Interrupts events Default mapping event manager RegEvn(5) RegEvn(1)
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Clock
ckRCExt
high prescaler
ckRCExt ckRCExt/256
RegSysRcTrim1&2 EnableXtal not(En Clock) ck32kHz
div.
prescaler
ck32kHz ck1Hz cpuck
Xtal
EnableRc Clock system clock
Figure 7-1. Clock block structure
Datasheet XE88LC06A
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Datasheet XE88LC06A
7.6.1
Clock sources oscillator
Configuration
oscillator always turned selected system operation power-on reset, NRESET, when exiting sleep mode. turned after Xtal (quartz oscillator) been started, after selection external clock entering sleep mode. oscillator frequency ranges: sub-MHz MHz) above-MHz (0.5 MHz). Inside range, frequency tuned software coarse fine adjustment. registers RegSysRcTrim1 RegSysRcTrim2. EnableRc register RegSysClock controls propagation clock signal operation oscillator. user stop oscillator resetting EnableRc. Entering sleep mode disables oscillator. Note: oscillator bias maintained while oscillator disabled setting BiasRc RegSysClock. This allows faster restart oscillator cost increased power consumption (see section 7.6.3). 7.6.2 oscillator frequency tuning
oscillator frequency using bits RegSysRcTrim1 RegSysRcTrim2 registers. Figure shows nominal frequency oscillator function these bits. absolute value frequency given register content change ±35% from chip chip tolerances integrated capacitors resistors. However, modification frequency function modification register content fairly precise. This means that curves Figure shift down that slope remains unchanged. RcFreqRange modifies oscillator frequency factor upper curve figure corresponds RcFreqRange=1. RcFreqCoarse modifies frequency oscillator factor (RcFreqCoarse+1). figure represents frequency different values bits RcFreqCoarse: each value frequency multiplied Incrementing RcFreqFine code, increases frequency about 1.4%. frequency oscillator therefor given with fRcmin oscillator frequency registers
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Datasheet XE88LC06A
1E+07
RcFreqRange='1' RcFreqRange='0'
Nominal oscillator frequency [Hz]
1E+06
RcFreqFine(5:0)
1E+05
1E+04 0000 0001 0011 0111 1111
Figure 7-2. oscillator nominal frequency tuning. 7.6.3 oscillator specifications description Lowest frequency fine tuning step startup time Supply voltage dependence Temperature dependence unit %/°C Comments Note BiasRc=0 BiasRc=1 Note Note
fRCmin RcFreqFine RC_su PSRR
Table 7-8. oscillator specifications Note this frequency tolerance when trimming codes frequency start-up about twice high. Note frequency shift function VBAT with normal regulator function. Note frequency shift function VBAT while regulator short-circuited VBAT. tolerances minimal frequency drift with supply temperature cancelled using software hardware DFLL (digital frequency locked loop) which uses crystal oscillator reference frequency.
RcFreqFine(5:0)
RcFreqCoarse(3:0)
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Datasheet XE88LC06A
7.7.1
Xtal oscillator
Xtal configuration
Xtal operates with external crystal 32'768 During Xtal oscillator start-up, first 32768 cycles masked. bits EnableXtal ColdXtal register RegSysClock control oscillator. power-on reset, NRESET pulse during sleep mode, EnableXtal reset ColdXtal (Xtal oscillator selected start-up). user start Xtal oscillator setting EnableXtal. When Xtal oscillator starts, ColdXtal reset after 32768 cycles. Before ColdXtal reset system, Xtal frequency precision guaranteed. Xtal oscillator stopped user resetting EnableXtal. When user enters into sleep mode, Xtal stopped. 7.7.2 Xtal oscillator specifications
crystal oscillator been designed crystal with specifications given Table 7-9. oscillator precision only guaranteed this crystal. Symbol Description Resonance frequency nominal frequency Motional resistance Motional capacitance Shunt capacitance Motional resistance overtone (parasitic) Quality factor 32768 400k Unit Comments
Table 7-9. Crystal specifications. safe operation, power consumption meet specified precision, careful board layout required: Keep lines XOUT short insert line between them. Connect crystal package VSS. noisy digital lines near XOUT. Insert guards where needed. Respect board specifications Table 7-10. Symbol Rh_xin Rh_xout Rh_xin_xout Cp_xin Cp_xout Cp_xin_xout Description Resistance XIN-VSS Resistance XOUTVSS Resistance XINXOUT Capacitance XINVSS Capacitance XOUTVSS Capacitance XINXOUT Unit Comments
Table 7-10. Board layout specifications.
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oscillator characteristics given Table 7-11. characteristics valid only crystal board layout meet specifications above. Symbol fXtal St_xtal Fstab Description Nominal frequency Start-up time Frequency deviation 32768 Unit Comments
-100
Note
Table 7-11. Crystal oscillator characteristics. Note This gives relative frequency deviation from nominal crystal with CL=8.2pF within temperature range -40°C 85°C. crystal tolerance, crystal aging crystal temperature drift included this figure.
7.8.1
External clock
External clock configuration
user provide external clock instead internal oscillators. external provided frequency internally divided two. external clock input XIN. system configured external clock EnExtClock register RegSysClock. Using bits registers RegSysRcTrim1 RegSysRcTrim2, ck32kHz clock frequency controlled (see section 7.11). Note: when using external clock, Xtal available. 7.8.2 External clock specification
external clock satisfy specifications table below. Correct behavior circuit guaranteed external clock signal does respect specifications below. Symbol FEXT PW_1 PW_0 FEXT_LV PW_1_LV PW_0_LV Description External clock frequency Pulse width Pulse width External clock frequency Pulse width Pulse width 0.06 0.03 Unit Comments Note Note Note Note Note Note
Table 7-12. External clock specifications. Note VBAT2.4V Note VBAT=VREG=1.2V
Clock source selection
There three possible clock sources available clock. clock always selected after power-up, negative pulse NRESET after Sleep mode. clock selection done with CpuSel RegSysClock fastest clock, from Xtal EnableXtal EnExtClock else from high prescaler output). Switching from clock source another glitch free. D0209-136
Datasheet XE88LC06A next table summarizes different clock configurations circuit: Clock Sources EnExtClock EnableXtal EnableRc Mode name Cpuck High Prescaler Clock input RCNOTE External Prescaler Clock input Xtal High presc. Xtal High presc. Clock targets
CpuSel=0 Xtal RCNOTE RCNOTE External NOTE
CpuSel=1 Xtal High presc. Xtal High presc.
Sleep Xtal Xtal External
Table 7-13: Table clocking modes. Note frequency must higher than when Xtal enabled order ensure proper operation. Note clock divided value freq instruction (see coolrisc instruction information) freq instruction nodiv div2 div4 div8 div16 cpuck external RC/2 external/2 RC/4 external/4 RC/8 external/8 RC/16 external/16
Note Switching from clock source another stopping unused clock source must performed using MOVE instructions RegSysClock. First select clock source then stop unused one.
7.10 Prescalers
clock generator block embeds divider chains: high prescaler one. high prescaler made stage dividing chain prescaler stage dividing chain. Features: High prescaler only driven with clock external clock (bits EnableRc EnExtClock have set, Table 7-13). prescaler driven from high prescaler directly with Xtal clock when EnableXtal EnExtClock ClearLowPrescal RegSysPre0 register allows reset synchronously prescaler, prescaler also automatically cleared when EnableXtal set. Both dividing chains reset asynchronously nresetglobal signal. ColdXtal=1 indicates Xtal start phase. active 32768 Xtal cycles after setting EnableXtal.
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Datasheet XE88LC06A
7.11 frequency selector
decoder used select from high prescaler, frequency that closest operate prescaler when Xtal running. this case, oscillator frequency ±35% will also valid prescaler frequency outputs. next table shows trimming values RegSysRcTrim1 RegSysRcTrim2 registers select frequency. least significant bits RcFreqFine word used. order ensure correct frequency selection prescaler when having external clock, proper value must trim registers. code selected from table below function frequency ratio between half frequency external clock 32kHz. frequency correctly, timings derived from prescaler will shifted accordingly (e.g. watchdog frequencies) some peripherals longer function correctly deviation from 32kHz large (e.g. voltage level detector).
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Default case (0'0001'000) From 0'0000'000 0'0000'100 From 0'0000'101 0'0001'100 From 0'0001'101 0'0001'111 0'0010'000 From 0'0010'001 0'0010'110 0'0010'111 From 0'0011'000 0'0011'100 From 0'0011'101 0'0011'111 From 0'0100'000 0'1000'010 From 0'0100'011 0'0100'111 0'0101'000 From 0'0101'001 0'0101'110 0'0101'111 From 0'0110'000 0'0110'101 From 0'0110'110 0'0110'111 From 0'0111'000 0'0111'100 From 0'0111'101 0'0111'111 From 0'1000'000 0'1000'011 From 0'1000'100 0'1000'111 From 0'1001'000 0'1001'010 From 0'1001'011 0'1001'111 From 0'1010'000 0'1010'001 From 0'1010'010 0'1010'111 0'1011'000 From 0'1011'001 0'1011'110 0'1011'111 From 0'1100'000 0'1100'110 0'1100'111 From 0'1101'000 0'1101'101 From 0'1101'110 0'1101'111 From 0'1110'000 0'1110'100 From 0'1110'101 0'1110'111 From 0'1111'000 0'1111'100 From 0'1111'101 0'1111'111 From 1'0000'000 1'0000'010 From 1'0000'011 1'0001'010 From 1'0001'011 1'0010'100 From 1'0010'101 1'0010'111 From 1'0011'000 1'0011'010 From 1'0011'011 1'0011'111 1'0100'000 From 1'0100'001 1'0100'110 1'0100'111 From 1'0101'000 1'0101'100 From 1'0101'101 1'0101'111 From 10110'000 1'0110'011 From 1'0110'100 1'0110'111 From 1'0111'000 1'0111'010 From 1'0111'011 1'0111'111 From 1'1000'000 1'1000'001 From 1'1000'010 1'1000'111 1'1001'000 From 1'1001'001 1'1111'111
Selected high prescaler
Ckrcext/2 Ckrcext Ckrcext/2 Ckrcext/4 Ckrcext/2 Ckrcext/4 Ckrcext/8 Ckrcext/4 Ckrcext/8 Ckrcext/4 Ckrcext/8 Ckrcext/4 Ckrcext/8 Ckrcext/16 Ckrcext/8 Ckrcext/16 Ckrcext/8 Ckrcext/16 Ckrcext/8 Ckrcext/16 Ckrcext/8 Ckrcext/16 Ckrcext/8 Ckrcext/16 Ckrcext/8 Ckrcext/16 Ckrcext/32 Ckrcext/16 Ckrcext/32 Ckrcext/16 Ckrcext/32 Ckrcext/16 Ckrcext/32 Ckrcext/16 Ckrcext/32 Ckrcext/8 Ckrcext/16 Ckrcext/32 Ckrcext/64 Ckrcext/32 Ckrcext/64 Ckrcext/32 Ckrcext/64 Ckrcext/128 Ckrcext/64 Ckrcext/128 Ckrcext/64 Ckrcext/128 Ckrcext/64 Ckrcext/128 Ckrcext/64 Ckrcext/128 Ckrcext/64 Ckrcext/128
Table 7-14: Table 32kHz high prescaler decoder.
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Interrupt handler
Interrupt handler Features. Overview. Register
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Datasheet XE88LC06A
Features
XE8000 chips support interrupt sources, divided into levels priority.
Overview
interrupt sources sampled highest frequency system. interruption generated memorized when interrupt becomes high. interrupt sources divided into levels priority: High interrupt sources), interrupt sources), interrupt sources). Those levels priority directly mapped those supported CoolRisc (IN0, IN2; CoolRisc documentation more information). RegIrqHig, RegIrqMid, RegIrqLow 8-bit registers containing flags interrupt sources. Those flags when interrupt enabled (i.e. corresponding registers RegIrqEnHig, RegIrqEnMid RegIrqEnLow set) rising edge detected corresponding interrupt source. Once memorized, interrupt flag cleared writing corresponding RegIrqHig, RegIrqMid RegIrqLow. Writing does modify flag. definitively clear interrupt, clear CoolRisc interrupt CoolRisc status register. interrupts automatically cleared after reset. registers provided facilitate writing interrupt service software. RegIrqPriority contains number highest priority (its value 0xFF when interrupt memorized). RegIrqIrq indicates priority level current interrupts.
Register
Register name RegIrqHig RegIrqMid RegIrqLow RegIrqEnHig RegIrqEnMid RegIrqEnLow RegIrqPriority RegIrqIrq Table 8-1: Handler Registers
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pos.
RegIrqHig RegIrqHig[7] RegIrqHig[6] RegIrqHig[5] RegIrqHig[4] RegIrqHig[3] RegIrqHig[2] RegIrqHig[1] RegIrqHig[0]
reset nresetglobal nresetglobal nresetglobal nresetglobal nresetglobal nresetglobal nresetglobal nresetglobal
function interrupt (high priority) clear interrupt when written interrupt (high priority) clear interrupt when written interrupt (high priority) clear interrupt when written interrupt (high priority) clear interrupt when written interrupt (high priority) clear interrupt when written interrupt (high priority) clear interrupt when written interrupt (high priority) clear interrupt when written interrupt (high priority) clear interrupt when written
Table 8-2: RegIrqHig pos. RegIrqMid RegIrqMid[7] RegIrqMid[6] RegIrqMid[5] RegIrqMid[4] RegIrqMid[3] RegIrqMid[2] RegIrqMid[1] RegIrqMid[0] reset nresetglobal nresetglobal nresetglobal nresetglobal nresetglobal nresetglobal nresetglobal nresetglobal function interrupt (mid priority) clear interrupt when written interrupt (mid priority) clear interrupt when written interrupt (mid priority) clear interrupt when written interrupt (mid priority) clear interrupt when written interrupt (mid priority) clear interrupt when written interrupt (mid priority) clear interrupt when written interrupt (mid priority) clear interrupt when written interrupt (mid priority) clear interrupt when written
Table 8-3: RegIrqMid
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pos.
RegIrqLow RegIrqLow[7] RegIrqLow[6] RegIrqLow[5] RegIrqLow[4] RegIrqLow[3] RegIrqLow[2] RegIrqLow[1] RegIrqLow[0]
reset nresetglobal nresetglobal nresetglobal nresetglobal nresetglobal nresetglobal nresetglobal nresetglobal
function interrupt (low priority) clear interrupt when written interrupt (low priority) clear interrupt when written interrupt (low priority) clear interrupt when written interrupt (low priority) clear interrupt when written interrupt (low priority) clear interrupt when written interrupt (low priority) clear interrupt when written interrupt (low priority) clear interrupt when written interrupt (low priority) clear interrupt when written
Table 8-4: RegIrqLow pos. RegIrqEnHig RegIrqEnHig[7] RegIrqEnHig[6] RegIrqEnHig[5] RegIrqEnHig[4] RegIrqEnHig[3] RegIrqEnHig[2] RegIrqEnHig[1] RegIrqEnHig[0] reset function enable interrupt enable interrupt enable interrupt enable interrupt enable interrupt enable interrupt enable interrupt enable interrupt
Table 8-5: RegIrqEnHig pos. RegIrqEnMid RegIrqEnMid[7] RegIrqEnMid[6] RegIrqEnMid[5] RegIrqEnMid[4] RegIrqEnMid[3] RegIrqEnMid[2] RegIrqEnMid[1] RegIrqEnMid[0] reset function enable interrupt enable interrupt enable interrupt enable interrupt enable interrupt enable interrupt enable interrupt enable interrupt
Table 8-6: RegIrqEnMid
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pos.
RegIrqEnLow RegIrqEnLow[7] RegIrqEnLow[6] RegIrqEnLow[5] RegIrqEnLow[4] RegIrqEnLow[3] RegIrqEnLow[2] RegIrqEnLow[1] RegIrqEnLow[0]
reset
function enable interrupt enable interrupt enable interrupt enable interrupt enable interrupt enable interrupt enable interrupt enable interrupt
Table 8-7: RegIrqEnLow pos. RegIrqPriority RegIrqPriority reset 11111111 function code highest priority
Table 8-8: RegIrqPriority pos. RegIrqIrq IrqHig IrqMid IrqLow reset 00000 function unused more high priority interrupt more priority interrupt more priority interrupt
Table 8-9: RegIrqIrq
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Event handler
Event handler Features. Overview. Register
Event handler avril 2000 D0209-136
Datasheet XE88LC06A
Features
XE8000 chips support event sources, divided into levels priority.
Overview
event sources sampled highest frequency system. event generated memorized when event becomes high. event sources divided into levels priority: High event sources) event sources). Those levels priority directly mapped those supported CoolRisc (EV0 EV1; CoolRisc documentation more information). RegEvn 8-bit register containing flags event sources. Those flags when event enabled (i.e. corresponding registers RegEvnEn set) rising edge detected corresponding event source. Once memorized, writing corresponding RegEvn clears event flag. Writing does modify flag. interrupts automatically cleared after reset. registers provided facilitate writing interrupt service software. RegEvnPriority contains number highest event (its value 0xFF when event memorized). RegEvnEvn indicates priority level current interrupts.
Register
addresses given Table default values different some products. Register name RegEvn RegEvnEn RegEvnPriority RegEvnEvn Table 9-1: Handler Registers
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pos.
RegEvn RegEvn[7] RegEvn[6] RegEvn[5] RegEvn[4] RegEvn[3] RegEvn[2] RegEvn[1] RegEvn[0]
reset nresetglobal nresetglobal nresetglobal nresetglobal nresetglobal nresetglobal nresetglobal nresetglobal
function event (high priority) clear event when written event (high priority) clear event when written event (high priority) clear event when written event (high priority) clear event when written event (low priority) clear event when written event (low priority) clear event when written event (low priority) clear event when written event (low priority) clear event when written
Table 9-2: RegEvn pos. RegEvnEn RegEvnEn[7] RegEvnEn[6] RegEvnEn[5] RegEvnEn[4] RegEvnEn[3] RegEvnEn[2] RegEvnEn[1] RegEvnEn[0] reset nresetglobal nresetglobal nresetglobal nresetglobal nresetglobal nresetglobal nresetglobal nresetglobal function enable event enable event enable event enable event enable event enable event enable event enable event
Table 9-3: RegEvnEn pos. RegEvnPriority RegEvnPriority reset 11111111 nresetglobal function code highest event
Table 9-4: RegEvnPriority pos. RegEvnEvn EvnHig EvnLow reset 00000 nresetglobal nresetglobal function unused more high priority event more priority event
Table 9-5: RegEvnEvn
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power
power 10-1
10.1 Features 10-2 10.1.1 Overview 10-2 10.2 Register map. 10-2
10-1
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10.1 Features
10.1.1
Overview
order save power consumption, 8-bit registers provided page These memory locations should reserved often-updated variables. they real registers RAM, power consumption greatly reduced.
10.2 Register
pos. Reg00 Reg00 Reg01 Reg02 Reg03 Reg04 Reg05 Reg06 Reg07 reset function low-power data memory low-power data memory low-power data memory low-power data memory low-power data memory low-power data memory low-power data memory low-power data memory
Table 10-1: Power
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Port
11.1 11.2 11.3 11.4 11.5
Port 11-1 Features 11-2 Overview 11-2 Register map. 11-3 Interrupts events 11-4 Port (PA) Operation 11-4
11-1
Port 2001
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11.1 Features
input port, bits wide each individually debounced direct input each individually pullup snap-to-rail option each input each interrupt request source rising falling edge system reset generated input pattern PA[0] PA[1] generate events CPU, individually maskable PA[0] PA[3] used clock inputs counters/timers/PWM (product dependent)
11.2 Overview
PortA general purpose wide digital input port, with interrupt capability. Figure 11-1 shows structure.
VBat
Port
logic debounce RegPASnapToRail RegPAPullup RegPADebounce DebFast (RegPACtrl(0)) RegPACtrl RegPAIn RegPAEdge interrupts events cntclocks 1kHz 32kHz RegPARes1 RegPARes0
resetfromporta
Figure 11-1: structure Port
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11.3 Register
There eight registers Port (PA), namely RegPAIn, RegPADebounce, RegPAPullup, RegPAEdge, RegPARes0, RegPARes1, RegPACtrl RegPASnapToRail. Table 11-2 Table 11-9 show mapping control bits functionality these registers. register name RegPAIn RegPADebounce RegPAEdge RegPAPullup RegPARes0 RegPARes1 RegPACtrl RegPASnapToRail Table 11-1: registers
pos. RegPAIn PAIn[7:0] reset description PA[7] PA[0] input value
Table 11-2: RegPAIn
pos. RegPADebounce PADebounce[7:0] reset nresetpconf description PA[7] PA[0] debounce enabled debounce disabled
Table 11-3: RegPADebounce
pos. RegPAEdge PAEdge[7:0] reset nresetglobal description PA[7] PA[0] edge configuration positive edge negative edge
Table 11-4: RegPAEdge
pos. RegPAPullup PAPullup[7:0] reset nresetpconf description PA[7] PA[0] pullup enable pullup disabled pullup enabled
Table 11-5: RegPAPullup
pos. RegPARes0 PARes0[7:0] reset nresetglobal description PA[7] PA[0] reset configuration
Table 11-6: RegPARes0
pos. RegPARes1 PARes1[7:0] reset nresetglobal description PA[7] PA[0] reset configuration
Table 11-7: RegPARes
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pos.
RegPACtrl [7:1] DebFast
reset 0000000 nresetpconf
description Unused slow debounce, fastdebounce
Table 11-8: RegPACtrl
pos. RegPASnapToRail PASnapToRail[7:0] reset nresetpconf description snap-to-rail input
Table 11-9: RegPASnapToRail Note: Depending status EnResetPConf RegSysCtrl, RegPAEdge, RegPADebounce RegPACtrl reset possible system resets only with power-on reset NRESET pad.
11.4 Interrupts events
Interrupt source pa_irqbus[5] pa_irqbus[4] pa_irqbus[1] pa_irqbus[0] pa_irqbus[7] pa_irqbus[6] pa_irqbus[3] pa_irqbus[2] Default mapping interrupt manager RegIrqMid[5] RegIrqMid[4] RegIrqMid[1] RegIrqMid[0] RegIrqLow[7] RegIrqLow[6] RegIrqLow[3] RegIrqLow[2] Default mapping event manager
RegEvn[4] RegEvn[0]
11.5 Port (PA) Operation
Port input status (debounced not) read from RegPAin. Debounce mode: Each Port individually debounced setting corresponding RegPADebounce. After reset, debounce function disabled. After enabling debouncer, change input value accepted only height consecutive samples identical. Selection clock done DebFast Register RegPACtrl.
DebFast Clock filter 1kHz 32kHz
Table debounce frequency selection Note: tolerance debounce frequency depends selected clock source. When external clock used, pulse width will correct input prescaler frequency close 32kHz (see clock block documentation). Pullups/Snap-to-rail: Different functions possible depending value registers RegPAPullup RegPASnapToRail. When corresponding RegPAPullup inputs floating (pullup pulldown resistors disconnected). When corresponding RegPAPullup RegPASnapToRail pullup resistor connected input pin. Finally, when
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corresponding RegPAPullup RegPASnapToRail snap-to-rail function active. snap-to-rail function connects pullup pulldown resistor input depending value forced input pin. This function used instance when input port connected tristate bus. When floating, pullup pulldown maintains last impedance state before became floating until another impedance output drives bus. also reduces power consumption with respect classic pullup since selects pullup pulldown resistor that confirms detected input state. state input summarized table below.
PAPullup[x] PASnapToRail[x] (last) externally forced PA[x] value PA[x] pull floating pullup pulldown pullup
Table Snap-to-rail Port starts with pullup resistor connected snap-to-rail function disabled. Port interrupt source: Each Port input interrupt request source rising falling edge with corresponding RegPAEdge. After reset, rising edge selected interrupt generation default. interrupt source debounced setting register RegPADebounce. interrupt signals sampled fastest clock circuit. order guarantee that circuit detects interrupt, minimal pulse length should cycle this clock. Note: care must taken when modifying RegPAEdge because this register performs edge selection. change this register result transition, which interpreted valid interruption. Port event source: interrupt signals pins PA[0] PA[1] also available events event controller. Port clock source (product dependent): Images PA[0] PA[3] input ports (debounced not) available clock sources counter/timer/PWM peripheral. Port reset source: Port used generate system reset placing predetermined word Port externally. reset built using logical PARes[x] signals: resetfromportA PAReset[7] PAReset[6] PAReset[5] PAReset[0] PAReset[x] itself logical function corresponding PA[x]. four logical functions selected each writing into registers RegPARes0 RegPARes1 shown Table 11-12.
PARes1[x] PARes0[x] PAReset[x] PA[x] not(PA[x])
Table 11-12: Selection bits reset signal
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reset from Port inhibited placing both PARes1[x] PARes0[x] least pin. Setting both PARes1[x] PARes0[x] makes reset independent value corresponding pin. Setting both registers hFF, will reset circuit independent from Port input value. This makes possible reset software. Note: depending value PA[0] PA[7], changes RegPARes0 RegPARes1 cause reset. Therefore safe have always (RegPARes0[x], RegPARes1[x]) equal `00' during setting operations.
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Port
12.1 12.2 12.3 12.4 12.5 12.5.1 12.5.2 12.6 12.7 12.7.1 12.7.2 12.8
Port 12-1 Features 12-2 Overview 12-2 Register map. 12-2 Port capabilities 12-3 Port analog capability 12-4 Port analog configuration 12-4 Port analog function specification. 12-5 Port function capability 12-5 Port digital capabilities. 12-6 Port digital configuration 12-6 Port digital function specification 12-7 power comparators. 12-7
12-1 Port 2001
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12.1 Features
Input output analog port, bits wide Each individually input output Each individually open-drain push-pull Each individually pull-up (for input open-drain mode) open-drain mode, pull-up active when corresponding zero pads connected individually four internal analog lines line analog bus) internal freq. cpuck) output PB[2] PB[3] Product dependant: signal output pads PB[0] PB[1] synchronous serial interface (USRT) uses pads PB[5], PB[4] UART interface uses pads PB[6] PB[7]
12.2 Overview
Port multi-purpose Input/output port. addition digital behavior, pins used analog signals. Each port terminal individually selected digital input output analog sharing four possible analog lines.
12.3 Register
Table 12-1 shows Port registers. register name RegPBOut RegPBIn RegPBDir RegPBOpen RegPBPullup RegPBAna Table 12-1: Default Port registers
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pos.
RegPBOut
PBOut[7-0]
reset
nresetpconf
description digital mode
PB[7-0] output value
description analog mode
Analog selection PB[7-0]
Table 12-2: RegPBOut
pos.
RegPBIn
PBIn[7-0]
reset
description digital mode
PB[7-0] input status
description analog mode
Unused
Table 12-3: RegPBIn
pos.
RegPBDir
PBDir [7-0]
reset
nresetpconf
description digital mode
PB[7-0] direction (0=input)
description analog mode
Analog selection PB[7-0]
Table 12-4: RegPBDir
pos.
RegPBOpen
PBOpen[7-0]
reset
nresetpconf
description digital mode
PB[7-0] open drain open drain)
description analog mode
Unused
Table 12-5: RegPBOpen
pos.
RegPBPullup
PBPullup[7]
reset
nresetpconf
description digital mode
Pull-up PB[7-0] (1=active)
description analog mode
Connect PB[7-0] selected
Table 12-6: RegPBPullup
pos.
RegPBAna
PBAna [7-0]
reset
nresetpconf
description digital mode
PB[7-0] analog mode
description analog mode
PB[7-0] analog mode
Table 12-7: RegPBAna
Note: Depending status EnResPConf RegSysCtrl, reset conditions registers different. reset block documentation more details nresetpconf signal.
12.4 Port capabilities
Port name PB[7] PB[6] PB[5] PB[4] PB[3] PB[2] PB[1] PB[0] high (analog) analog analog analog analog analog analog analog analog utilization (priority) medium (functions) uart uart usrt usrt clock PWM1 Counter (C+D) PWM0 Counter (A+B) (digital) (default) (with pull-up) (with pull-up) (with pull-up) (with pull-up) (with pull-up) (with pull-up) (with pull-up) (with pull-up)
Table 12-8: Different Port functions
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Table 12-8 shows different usages that made port with order priority. selected analog, overwrites function digital set-up. selected analog, function enabled, overwrites digital set-up. neither analog function selected pin, used ordinary digital I/O. This default configuration start-up. Note: presence functions product dependent.
12.5 Port analog capability
12.5.1 Port analog configuration
Port terminals attached line analog setting PBAna[x] bits RegPBAna register. other registers then define connection these analog lines different pads Port These used implement simple driver converter. Analog switching available only when circuit powered with sufficient voltage (see specification below). Below specified supply voltage, only voltages that close VBAT switched. When PBAna[x] Port terminals changed from digital mode analog. usage registers RegPBPullup, RegPBOut RegPBDir define analog configuration (see Table 12-9). When PBAna[x] then PBPullup[x] connects analog bus. PBDir[x] PBPOut[x] select which analog lines used. analog selection PBDir[x] PBout[x] PBPullup[x] PB[x] selection analog line analog line analog line analog line High impedance
Table 12-9: Selection analog lines with RegPBDir, RegPBout RegPBPullup when PBAna[x] Example: pads PB[2] PB[5] analog line (the values depend configuration others pads) apply high impedance analog mode (move RegPBPullup,#0bXX0XX0XX) analog mode (move RegPBAna,#0bXX1XX1XX) select analog line3 (move RegPBDir,#0bXX1XX1XX move RegPBOut,#0bXX1XX1XX) apply analog line output (move RegPBPullup,#0bXX1XX1XX)
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12.5.2
Port analog function specification
table below defines on-resistance switches between analog different conditions. series resistance between pins Port connected same analog line twice resistance given table. description switch resistance switch resistance input capacitance (off) input capacitance (on) unit Comments Note Note Note Note
Table 12-10. Analog input specifications. Note This series resistance between analog line cases VBAT 2.4V VMULT peripheral present circuit enabled. VBAT 3.0V VMULT peripheral present circuit. Note This series resistance case VBAT 2.8V peripheral VMULT present circuit. Note This input capacitance seen when connected analog line. This value indicative only since product package dependent. Note This input capacitance seen when connected analog line other connected same analog line. This value indicative only since product package dependent.
12.6 Port function capability
Port used different functions implemented other peripherals. description below applicable only circuit contains these peripherals. When counters used implement function (see documentation counters), PB[0] PB[1] terminals used outputs (PB[0] used CntPWM0 RegCntConfig1 PB[1] used CntPWM1 RegCntConfig1 generated values override values written RegPBout. However, PBDir(0) PBDir(1) automatically overwritten have Output16k RegSysMisc, frequency output PB[3]. This overrides value contained PBOut(3). However, PBDir(3) must frequency duty cycle clock signal given Figure 12-1. fmax frequency fastest clock present circuit.
1/fmax 1/16k
Figure 12-1. output clock timing
Similarly, OutputCkCpu RegSysMisc, frequency output PB[2]. This overrides value contained PBOut(2). However, PBDir(2) must
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1/f1 1/f2
Figure 12-2. output clock timing. timing clock (Figure 12-2) depends selection CpuSel RegSysClock register given Table 12-11. fmax frequency fastest clock present circuit. Note that tolerance depends selected clock source (see clock block documentation). CpuSel fmax/4 fmax fmax
Table 12-11. clock timing parameters.
Pins PB[5] PB[4] used USRT (see USRT documentation) when UsrtEnable RegUsrtCtrl. PB[5] PB[4] then become open-drain. This overrides values contained PBOpen(5:4), PBOut(5:4) PBDir(5:4). there external pull-up resistor these pins, internal pull-ups should selected setting PBPullup(5:4). When output, PB[4] takes value UsrtS0 RegUsrtS0. When output, PB[5] takes value UsrtS1 RegUsrtS1. Pins PB[6] PB[7] used UART (see UART documentation). When UartEnTx RegUartCtrl PB[6] used output signal When UartEnRx RegUartCtrl PB[7] used input signal This overrides values contained PBOut(7:6) PBDir(7:6).
12.7 Port digital capabilities
12.7.1 Port digital configuration
direction each within Port (input only input/output) individually using RegPBDir register. PBDir[x] both input output buffer active corresponding Port PBDir[x] corresponding Port input only output buffer high impedance. After reset (nresetpconf) Port input only mode (PBDir[x] reset input values Port available RegPBIn (read only). Reading always direct there debounce function Port case possible noise input signals, software debouncer with polling external hardware filter have realized. input buffer also active when port defined output effective value read back. Data stored RegPBOut outputted Port PBDir[x] default values after reset (0). When output mode (PBDir[x] output conventional CMOS (PushPull) N-channel Open-drain, driving output only low. default, after reset (nresetpconf) PBOpen[x] RegPBOpen cleared (push-pull). PBOpen[x] RegPBOpen then internal transistor output buffer electrically removed output only driven (PBOut[x]=0). When PBOut[x]=1, high Impedance. internal pull-up external pull-up resistor used drive high. Note: Because transistor actually exists (this real Open-drain output) pull-up range limited 0.2V (avoid forward bias transistor diode).
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Each individually pull-up using register RegPBPullup. Input pulled when corresponding this register Default status after (nresetpconf) which means with pull limit power consumption, pull-up resistors only enabled when associated either digital input N-channel open-drain output with other cases (pushpull output open-drain output driven low), pull resistors disabled independent value RegPBPullup. After power-on reset, Port configured input port with pull-up. During power-on reset (see reset block documentation) however, PB[1] pulled down stead pulled Once power-on reset completed, PB[1] pulled exactly other Port pins. input buffer always active, except analog mode. This means that Port input should valid digital value times unless analog mode. Violating this rule lead high power consumption. 12.7.2 VINH VINL Port digital function specification description Input high voltage Input voltage Output high voltage Output voltage 0.7*VBAT VBAT-0.4 VBAT 0.2*VBAT VBAT VSS+0.4 unit Comments VBAT2.4V VBAT2.4V VBAT=1.2V, =0.3mA VBAT=2.4V, =5.0mA VBAT=4.5V, =8.0mA VBAT=1.2V, =0.3mA VBAT=2.4V, =12.0mA VBAT=4.5V, =15.0mA Note
Pull-up resistance Input capacitance
Note this value indicative only since depends package.
12.8 power comparators
power comparator (CMPD) peripheral present circuit, signals pins PB[7:4] used inputs these power comparators. Although comparators functional independent Port configuration, recommended pins that used CMPD analog mode without selecting analog lines. This avoid high power consumption digital input buffer when analog slowly varying digital signals applied.
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Port
13.1 13.2 13.3 13.4
PORT Features Overview Register Port (PD) Operation
13-1 13-2 13-2 13-2 13-4
13-1
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13.1 Features
input output port, bits wide each individually input output pull-ups available input mode snap-to-rail option input mode
13.2 Overview
Port (PD) general purpose input/output digital port. Figure 13-1 shows structure.
VBat
RegPDPullup[7:4]
logic
RegPDPullup[3:0]
RegPDIn
RegPDOut
RegPDDir
Figure 13-1 structure PortD
13.3 Register
There four registers Port (PD), namely RegPDIn, RegPDOut, RegPDDir RegPDPullup. Table 13-3 Table 13-6 show mapping control bits functionality these registers. register name RegPDIn RegPDOut RegPDDir RegPDPullup Table 13-1 registers
13-2
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Datasheet XE88LC06A
Pos.
RegPDIn PDIn[7:0]
Reset
Description PD[7:0] input value
Table 13-2 RegPDIn
Pos. RegPDOut PDOut[7:0] Reset nresetpconf Description PD[7:0] output value
Table 13-3 RegPDOut
Pos. RegPDDir PDDir[7:0] Reset nresetpconf Description PD[7:0] direction (0=input)
Table 13-4 RegPDDir
Pos. RegPDPullup PDSnapToRail[3] PDSnapToRail[2] PDSnapToRail[1] PDSnapToRail[0] PDPullup[3] PDPullup[2] PDPullup[1] PDPullup[0] Reset nresetpconf nresetpconf nresetpconf nresetpconf nresetpconf nresetpconf nresetpconf nresetpconf Description snap-to-rail PD[7] PD[6] (1=active) snap-to-rail PD[5] PD[4] (1=active) snap-to-rail PD[3] PD[2] (1=active) snap-to-rail PD[1] PD[0] (1=active) pullup PD[7] PD[6] (1=active) pullup PD[5] PD[4] (1=active) pullup PD[3] PD[2] (1=active) pullup PD[1] PD[0] (1=active)
Table 13-5 RegPDPullup
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Datasheet XE88LC06A
13.4 Port (PD) Operation
direction each Port (input input/output) individually using RegPDDir register. PDDir[x] output buffer corresponding Port enabled. After reset, Port input only mode (PDDir[x] reset input buffer always enabled independently from RegPDDir contents. Output data: Data stored RegPDOut prior output Port Input data: status Port available RegPDIn (read only). Reading always direct there digital debounce function associated with Port case possible noise input signals, software debouncer external filter must realised. Pull-up/Snap Rail: When configured input (PDDir[x]=0), pull-ups available every pin. pull-up function pins controlled PDPullup PDSnapToRail bits register RegPDPullup. When PDPullup[x] pull-ups pins PD[2x] PD[2x+1] disabled. When PDPullup[x] PDSnapToRail[x] pull-up resistor connected pins PD[2x] PD[2x+1]. When both PDPullup[x] PDSnapToRail[x] snap-to-rail function active pins PD[2x] PD[2x+1]. snap-to-rail function connects pullup pulldown resistor input depending value forced input pin. This function used instance when input port connected tristate bus. When floating, pullup pulldown maintains last impedance state before became floating until another impedance output driving bus. also reduces power consumption with respect classic pullup since selects pullup pulldown resistor that confirms detected input state. function summarised table below function different register settings.
PDDir[2x(+1)] PDPullup[x] PDSnapToRail[x] (last) externally forced PD[2x(+1)] value PD[2x(+1)] pull resistor connected connected pullup pulldown pullup
Table 13-6: Snap-to-rail pullup function power-on reset, Port configured input port with pull-ups active.
13-4
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Datasheet XE88LC06A
Interface (BitJockey)
CONTENTS
14.1 14.2 14.3 14.4 14.5 14.6 14.7 14.8 14.8.1 14.8.1.1 14.8.1.2 14.8.2 14.8.2.1 14.8.2.2 14.8.2.3 14.8.2.4 14.8.3 14.8.4 14.8.5 14.9 14.9.1 14.9.2 14.9.3 14.9.4 14.10 14.11 14.12 14.12.1 14.12.1.1 14.12.1.2 14.12.1.3 14.12.1.4 14.12.1.5 14.12.2 14.12.2.1 14.12.2.2 14.12.2.3 14.12.2.4 14.12.2.5 14.12.2.6 Introduction Features General overview Register Interrupts External connections Supported codes Reception mode: detailed description Input data filter synchronization code Bi-phase Miller code Start Sequence Detection message synchronization start sequence detection "Protocol" start detection "External" start detection "Pattern" start detection decoding Reception FIFO Reception interrupts Transmission mode Transmission FIFO Transmission interrupts Transmission encoding Transmission synchronization clock Baud rate selection Specifications Application hints Using interface with XE1201A Microcontroller transceiver connections Reception mode using coding XE1201A synchronizer Reception mode using Manchester coding Transmission mode using coding Transmission mode using Miller code Using interface with XE1202 Microcontroller transceiver connections Microcontroller clock source derived from XE1202 crystal oscillator Reception mode using coding XE1202 message synchronizer Reception mode using Manchester coding Transmission mode using coding Transmission mode using Manchester code 14-2 14-2 14-2 14-3 14-5 14-5 14-5 14-6 14-7 14-7 14-7 14-7 14-8 14-8 14-8 14-9 14-10 14-10 14-11 14-11 14-11 14-11 14-12 14-12 14-13 14-14 14-14 14-14 14-14 14-15 14-17 14-18 14-19 14-20 14-20 14-21 14-22 14-23 14-25 14-26
14-1
Rfif_dl 1.10 August 2002
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Datasheet XE88LC06A
14.1 Introduction
This block Stream Encoder Decoder Receiver Transmitter Interface. normal microcontroller, bits level coding protocol done software. This very tedious time consuming task since processor handle they received they have transmitted. This block simplifies handling level data handling wireless data transmission systems very much similar UART interface does wired transmission systems.
14.2 Features
functions Receiver Transmitter (half duplex) Internal baud rate generator standard baud rates Decode encode main codes (NRZ, Bi-Phase Miller), bypassed Buffered input output data (FIFO) interrupt sources Internal external synchronization Internal external start sequence detection
14.3 General overview
Interface block stream receiver transmitter wireless transmission. used with XEMICS' third party transceiver circuits.
Encoder Decoder Reception
RFIF0 Input Stream RFIF1 External clock
Control
Decoder
Enable/Bypass
Filter
Start Detection
Enable/Bypass
Shift Register
Type
FIFO
Ctrl Sig.
Match clock Clock Status.
data
Prescaler
clock RFIF2
Baudrate /PCM Type
Interrupts data
Clock
Transmission
FIFO
Ctrl Sig. Status.
RFIF3 Output Stream
Encoder
Enable/Bypass
Shift Register
Figure 14-1 Encoder Decoder Structure
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Datasheet XE88LC06A
Reception block consists "Filter". input data filtered depending selected baud rate. block extracts synchronization clock. When external synchronization clock used, filter bypassed. "Start Detection" block. This block detects programmable start sequence therefor synchronizes message start. interface ignores incoming messages until start sequence detected. This block bypassed external message synchronization signal used (match Figure 14-1). "PCM Decoder" which decodes main types waveforms i.e. NRZ, Bi-Phase, Miller). This block bypassed. "Shift Register" FIFO, that serial parallel conversion memorize input data. Transmission block consists FIFO "Shift Register" which store data parallel serial conversion. "Encoder" which encodes serial data into chosen type. This block bypassed. Prescaler generates clock signals needed reception transmission depending selected baud rate code type.
14.4 Register
register name RegRfifCmd1 RegRfifCmd2 RegRfifCmd3 RegRfifTx RegRfifTxSta RegRfifRx RegRfifRxSta RegRfifRxSPat Table 14-1: Rfif registers pos. RegRfifCmd1 unused RfifBRCoarse(1:0) RfifBRFine(3:0) reset nresetglobal 0000 nresetglobal description Select baud rate (coarse selection) Select baud rate (fine selection)
Table 14-2: RegRfifCmd1 pos. RegRfifCmd2 RfifEnStart(1:0) RfifEnCod RfifRxClock RfifTxClock RfifPCM(2:0) reset nresetglobal nresetglobal nresetglobal nresetglobal nresetglobal description Start Detection mode mode (see page 14-8) enables decoder (Rx) encoder (Tx) enables external clock input (Rx) enables external clock output (Tx) Select type (see page 14-6)
Table 14-3: RegRfifCmd2
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Datasheet XE88LC06A
pos.
RegRfifCmd3 RfifRxIrqEn RfifRxIrqMem RfifEnRx RfifEnTx
r/wc
reset nresetglobal nresetglobal nresetpconf nresetpconf
description enable sources (see page 14-11) Status (see page 14-11) enable Rfif reception mode enable Rfif transmission mode
Table 14-4: RegRfifCmd3 pos. RegRfifTx RfifTx reset 00000000 nresetglobal Table 14-5: RegRfifTx pos. RegRfifTxSta RfifTxFifoOverrun RfifTxFifoFull RfifTxFifoEmpty RfifTxStopped r/wc reset nresetglobal nresetglobal nresetglobal nresetglobal description Fifo overrun error. Write: clear FIFO Fifo full Fifo empty [IRQ] Fifo shift register empty: stopped description Data sent FIFO, depth
Table 14-6: RegRfifTxSta pos. RegRfifRx RfifRx reset 00000000 nresetglobal Table 14-7: RegRfifRx pos. RegRfifRxSta RfifRxFifoOverrun RfifRxFifoFull RfifRxStartDet RfifRxBusy RfifRxReady RfifRxNotEmpty r/wc r/wc reset nresetglobal nresetglobal nresetglobal nresetglobal nresetglobal description Fifo overrun error. Write: clear FIFO Fifo full [IRQ] Start Stream Detected [IRQ] Rfif busy receiving RegRfifRx contains least byte read. Cleared when reading RegRfifRx.[IRQ] description Received data FIFO, depth
Table 14-8: RegRfifRxSta pos. RegRfifRxSPat RfifRxSPat reset 00000000 nresetglobal Table 14-9: RegRfifRxSPat description Programmable start pattern
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Datasheet XE88LC06A
14.5 Interrupts
interrupt lines exist: transmitter receiver. interrupt source Irq_Rfif_Rx Irq_Rfif_Tx Table 14-10: Interrupts
14.6 External connections
interface uses pins. these pins depends interface. Table 14-11 shows possible these pins. receive mode, RFIF0 receiver data stream input. external synchronization clock mode selected, RFIF1 should connected synchronizer clock receiver. receiver message synchronization signal, connected RFIF2. transmitter mode, transmitter data connected RFIF3. synchronization clock generated RFIF2. RFIF0 Receive mode Transmit mode data RFIF1 clock Table 14-11 management case RFIF pins multiplexed parallel digital port, interface overwrites four digital pins soon receive mode transmitter mode interface enabled (bit RfifEnRx RfifEnTx register RegRfifCmd3 Unused pins configured inputs with weak pull-up pull-down. These pins remain floating driven externally. external pull-ups pull-downs required. RFIF2 match clock RFIF3 data
14.7 Supported codes
Seven different codes supported interface. They illustrated figure below. Code: this format message represented chip (i.e. distance between dotted lines Figure 14-2). coding does include clock information. sampling clock information extracted from message preamble. Bi-Phase Code Manchester code: this format message represented chips. This code contains clock information. Delay Modulation Miller code: this format message represented chips. This code contains clock information. interface receive transmit coded uncoded messages. coding/decoding function enabled/disabled using RfifEnCod enable) register RegRfifCmd2.
14-5
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Datasheet XE88LC06A
Types Codes
mark mark space mark space space mark
Level
Mark sampling baudrate Space
Bi-Phase Level sampling baudrate Bi-Phase Mark
Bi-Phase Space
Delay Modulation Miller
Figure 14-2 Supported Codes
code type selected using RfifPCM[2:0] control word register RegRfifCmd2. selection control bits given Table 14-12. Codes RfifPCM[2:0] Level Mark Space Level Bi-Phase Mark Space Miller
Table 14-12: code selection
14.8 Reception mode: detailed description
interface configured reception mode setting RfifEnRx enable) clearing RfifEnTx disable transmission) register RegRfifCmd3. input data stream coming from receiver connected RFIF0 pin.
14-6
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Datasheet XE88LC06A 14.8.1 14.8.1.1 Input data filter synchronization code
When codes used, synchronization clock should extracted from preamble since coding itself contain clock information. this case, external synchronization clock preferable. This clock delivered RFIF1. stream RFIF0 then sampled detection rising edge clock RFIF1 pin. This function enabled setting RfifRxClock register RegRfifCmd2 Selecting this function bypasses input filter. external synchronization clock available, input data filter used (see description below section 14.8.1.2) extract synchronization clock. RfifRxClock register RegRfifCmd2 cleared input data stream contains long periods without transitions, internally generated synchronization clock could slip with respect rate resulting transmission errors (see also specification chapter 14.11). 14.8.1.2 Bi-phase Miller code
bi-phase Miller code include clock information external synchronization clock needed. input data filter used filter noise input data. filter samples input data times selected baud rate performs following majority function successive samples: (number last samples data (number last samples data else data former data filter some hysteresis since output does change when number between input filter always selected bi-phase Miller coding independent from value RfifRxClock register RegRfifCmd2. 14.8.2 Start Sequence Detection message synchronization
full message mainly composed three parts: preamble start sequence data itself optional stop sequence. start sequence necessary indicate start message. interface supports detection several types start sequences. user chose between these start sequence detection modes using bits RfifEnStart[1:0] RegRfifCmd2 shown Table 14-13. actual implementation detection mode differs depending selected coding described below. start sequence detection will RfifRxStartDet register RegRfifRxSta generate interrupt Irq_Rfif_Rx line. contents reception FIFO reset. data preceding message that were read occurrence start sequence lost. first FIFO first valid decoded after detected start sequence. RfifRxStartDet cleared software writing bit.
14-7
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Datasheet XE88LC06A
start detection mode name "None" "protocol" "external" "pattern 8bits" RfifEnStart[1:0]
Table 14-13. Start detection mode selection
14.8.2.1
start sequence detection
this case, interface will look start sequence. incoming data stream will decoded according selected code will stored reception FIFO soon reception mode enabled. message start detected software. 14.8.2.2 "Protocol" start detection
coding defined start sequence. Selecting "protocol" start sequence same effect start detection. bi-phase Manchester code, protocol violation considered start sequence i.e. 1level 0-level which longer than duration chip. example shown Figure 14-3. delay modulation Miller coding, protocol violation considered start sequence i.e. 1-level 0-level which longer than duration chips.
sequence
other start first valid first valid sequence start sequence
Bi-Phase Level
codes
Figure 14-3 Start sequence type Bi-Phase-Level encoding
14.8.2.3
"External" start detection
external start detection signal used. This signal should connected RFIF2. falling edge RFIF2 (also called "match", Figure 14-1) indicates first valid message.
14-8
D0209-136
Datasheet XE88LC06A This edge occur during first half first shown Figure 14-4. minimal width pulse half bit.
RFIF2 (match)
Level
decoded data
first FIFO
Figure 14-4. Timing external word synchronization signal
14.8.2.4
"Pattern" start detection
start sequence defined pattern RfifRxSPat[7:0] written register RegFifRxSPat. This pattern compared incoming stream before decoding. This shown Figure 14-5 Figure 14-6 where identical input data stream identical pattern give same start sequence detection independent from decoded data.
RfifRxSPat=10011111 start sequence
first FIFO
Level
decoded data
Figure 14-5. Pattern start detection NRZ-Level RfifRxSPat[7:0]=10011111
14-9
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Datasheet XE88LC06A
RfifRxSPat=10011111 start sequence
first FIFO
Mark
decoded data
Figure 14-6. Pattern start detection NRZ-Mark RfifRxSPat[7:0]=10011111 start pattern less than bits since bits "don't care". 14.8.3 decoding
interface receive coded uncoded messages. coding/decoding function enabled/disabled using RfifEnCod enable) register RegRfifCmd2. code type selected using RfifPCM[2:0] control word register RegRfifCmd2. selection control bits given Table 14-12. Codes RfifPCM[2:0] Level Mark Space Level Bi-Phase Mark Space Miller
Table 14-14: code selection decoder detects invalid code sequences selected start detection mode "protocol mode (RfifEnStart[1:0] Table 14-13), decoder output generates equivalent number random data bits. decoder disabled (RfifEnCod meaning RfifPCM[2:0] changes: coding selected, input stream sampled selected rate. Manchester Miller coding selected, input stream sampled twice data rate. This allows decoding stream software. 14.8.4 Reception FIFO
decoder output data serially shifted shift register (see Figure 14-1). RfifRxBusy RegRfifRxSta indicates that data shifted When bits present shift register, byte loaded FIFO. FIFO depth RfifRxReady RegRfifRxSta indicates that least byte present FIFO. software read data FIFO RegRfifRx. When RfifRxFifoFull FIFO full data should read software before next byte received. not, data will lost RfifRxFifoOverrun Writing this will clear FIFO contents. detection start sequence will also clear RfifRxFifoOverrun FIFO contents.
14-10
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Datasheet XE88LC06A
first that received found position RfifRx[0], second position RfifRx[1] 14.8.5 Reception interrupts
Only interrupt line dedicated receiver interface. interrupt generated three different sources however. bits RfifRxIrqEn[2:0] RegRfifCmd3 allow selection interrupt source(s) shown Table 14-15. Possible interrupt sources detection message start, shift first byte FIFO after FIFO cleared finally when FIFO full. bits RfifRxIrqMem[2:0] RegRfifCmd3 flag which interrupt source active since these bits were last cleared. interrupt flags cleared writing More than interrupt source enabled same time. RfifRxIrqEn[2:0] RfifRxIrqMem[2:0] Interrupt source Start sequence detection byte written FIFO FIFO full
Table 14-15. Reception interrupt source selection first interrupt allows easy synchronization message start. second interrupt used wants download message byte time. third interrupt used wants download message bytes time.
14.9 Transmission mode
interface configured reception mode setting RfifEnTx enable) clearing RfifEnRx disable reception) register RegRfifCmd3. When transmission mode switched again, transmission will stop when transmission byte shift register completed. output data stream will generated RFIF3 pin. 14.9.1 Transmission FIFO
Data transmitted written FIFO writing register RegRfifTx. These data then loaded shift register which sends data encoder (Figure 14-1). transmission FIFO full, RfifTxFifoFull RegRfifTxSta software continues write data FIFO while full, flag RfifTxFifoOverrun will data will lost. RfifTxFifoOverrun flag cleared writing This clears contents transmission FIFO same time. When last data byte present FIFO loaded shift register, flag RfifTxFifoEmpty software does write data FIFO shift register finished shifting last encoder, RfifTxStopped RFIF3 remains last encoded state. first sent RfifTx[0], second RfifTx[1] 14.9.2 Transmission interrupts
Only interrupt source exists during transmission: interrupt generated moment last byte FIFO transferred transmission shift register. means that FIFO empty refilled with data. interrupt enabled interrupt manager block.
14-11
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Datasheet XE88LC06A 14.9.3 Transmission encoding
transmission encoder bypassed clearing RfifEnCod register RegRfifCmd2. stream RFIF3 then directly connected output shift register. RfifEnCod register RegRfifCmd2 stream coming from shift register encoded first before sending RFIF3 pin. type protocol selected using RfifPCM[2:0] control word register RegRfifCmd2. selection control bits given Table 14-14. Codes RfifPCM[2:0] Level Mark Space Bi-Phase/Manchester Level Mark Space Miller
Table 14-16: code selection When RfifEnCod modified while transmission active, modification will take effect only when byte loaded from FIFO into shift register. While encoder enabled, possible send protocol violation start pattern. protocol violation used start sequence Manchester Miller protocol, following sequence should used: wait until transmission FIFO empty (which means last byte preceding message being coded sent), clear RfifEnCod, write uncoded start pattern transmission FIFO wait until transmission FIFO empty (which means last byte uncoded start pattern being sent) RfifEnCod write message bytes FIFO back Beware that case protocol violation used start sequence Manchester-level Miller coding, used violation will depend value first message. example: Manchester level coding used first message (encoded 01), start sequence needs series 1's. series would used, receiver would unable distinguish leading message from start sequence. When encoder bypassed (RfifEnCod bits RfifPCM[2:0] still have influence output stream when coding chosen, bits shifted selected rate. Manchester Miller codes selected however, bits shifted twice data rate. This allows bits FIFO encode bits software. 14.9.4 Transmission synchronization clock
required, synchronization clock generated RFIF2 data uncoded coding used (bits RfifEnCod RfifPCM[2:0] RegRfifCmd2). generate this clock, RfifTxClock RegRfifCmd2 set. timing generated clock shown Figure 14-7.
14-12
D0209-136
Datasheet XE88LC06A
Level
output bitstream
output clock
Bi-Phase Level
output bitstream
Figure 14-7 Output clock Transmission mode
14.10 Baud rate selection
order have correct baud rates, interface with stable trimmed clock source. clock source external clock source oscillator. precision baud rate will depend precision selected clock source. choice between oscillator external clock source made with EnExtClock RegSysClock. precision obtained baud rate directly proportional frequency deviation used clock source. bits RfifBRCoarse[1:0] RfifBRFine[3:0] RegRfifCmd1 used select appropriate baud rate. Several division factors available. expression baud rate following:
baudrate
with:
fRCExt fine coarse
RCExt frequency half external clock frequency.
fine coarse: division factors selected RfifBRCoarse RfifBRFine.
Note that baud rate rate which chips transmitted twice rate Manchester Miller coding since these codes chips (see chapter 14.7). RfifBRFine[3:0] 0000 0001 0010 0011 1101 1110 1111 fine
Table 14-17 Effect RfifBRFine[3:0]
14-13
D0209-136
Datasheet XE88LC06A
RfifBRCoarse[1:0]
coarse
Table 14-18 Effect RfifBRCoarse[1:0] Even external synchronizer used, baud rate should correctly.
14.11 Specifications
frequency difference exists between transmitter receiver, receiver unable decode received messages correctly. This especially case protocol protocol used without external synchronization clock since these signals contain clock information. Manchester Miller coding more robust since decoder resynchronize code itself. estimated maximal tolerated frequency difference between transmitter interface following (theoretical values): Mode NRZ, external clock NRZ, with external clock Manchester Miller Maximal tolerated f=fRX-fTX receive identical consecutive bits: -50%/+100% -17%/+11% -9%/+8%
Table 14-19 Frequency difference tolerance without external synchronizer, should noted that tolerated frequency deviation larger number consecutive identical bits lower than
14.12 Application hints
14.12.1 Using interface with XE1201A
This chapter gives some examples interface used with XE1201A circuit. does describe possibilities selects some representative cases. 14.12.1.1 Microcontroller transceiver connections external components required operate XE1201A, please refer XE1201A datasheet. connections between XE8000 microcontroller XE1201A shown Figure 14-8. transmission data pins connected between interface microcontroller transceiver. configuration lines XE1201A driven pins parallel port. 3wire configuration data XE1201A used set-up circuit writing registers interface driven hardware software parallel port. Pins interface RFIF0 RFIF3 that used remain floating.
14-14
D0209-136
Datasheet XE88LC06A XE1201A used transmitter only, connections RFIF0 RFIF1 CLKD required. RXTX XE1201A permanently connected ground. RFIF0 RFIF1 remain floating. XE1201A used receiver only, connection RFIF3 required. TXRX permanently connected VDD. synchronizer XE1201A used, connection RFIF1 CLKD required. XE1201A transmitter permanently enabled, permanently connected VDD. This documentation shows set-up data transmission between microcontroller XE1201A. detailed information XE1201A functionality, external components, serial interface protocol register set-up, please refer XE1201A datasheet.
XE8000
RegRfifCmd1 RegRfifCmd2
RFIF0 RFIF1 RFIF2 RFIF3
data [clock] CLKD
interface
RegRfifCmd3 RegRfifTx RegRfifTxSta RegRfifRx RegRfifRxSta RegRfifRxSPat
XE1201
data
parallel port
hardware software
RXTX
register register register
MOSI MISO
Figure 14-8 Configuration connections between microcontroller XE1201A
14.12.1.2 Reception mode using coding XE1201A synchronizer protocol messages received level. start sequence message 11010111 pattern message length after start sequence bytes. messages sent data rate kbit/s. following paragraphs will show set-up XE1201A, setup interface handle received data. 14.12.1.2.1 XE1201A set-up
XE1201A reception mode, RXTX data rate XE1201A default 16kbit/s synchronizer enabled default. This means that
14-15
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Datasheet XE88LC06A dat

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