FILTERING OFFSET REDUCTION AVDD AGND DVDD DGND
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Data Sheet XE1201A Power Transceiver
FILTERING OFFSET REDUCTION
AVDD
AGND
DVDD
DGND
DEMODULATOR SYMBOL CHRO
CLKD
ONTROL POWER MANAGEMEN
POWER
RXTX
RFOU
VREF
CLOCK
RFGN
RFVDD
LOGN
XTAL
XE1201A 300-500
Low-Power Transceiver
Features
very low-power half-duplex operation data rate kbit/s high sensitivity external components internal synchronizer 3-wire easy microcontroller interface output power programmable
General Description
XE1201A half-duplex transceiver operation band (optimized) 300-500 band. modulation used Continuous Phase, level Frequency Shift Keying (CPFSK). direct conversion (zero receiver architecture enables on-chip channel filtering. XE1201A includes synchronizer that glitch free data with synchronized clock directly read cost complexity micro-controller. transmitted power level also controlled bus. XE1201A meets I-ETS300-220 standard available TQFP32 package.
Applications
telemetry security systems wireless data link door openers remote control wireless sensing
Quick Reference Data
supply voltage sensitivity data rate transmitted power -109 kbits/s
Ordering Information
Part XE1201A Temperature range Pin-package TQFP32
Cool Solutions Wireless Connectivity
XEMICS e-mail: info@xemics.com web: www.xemics.com
Data Sheet XE1201A Power Transceiver
Detailed Description
NAME AVDD AGND LOGND RXTX VREF CLKD DGND XTAL XTAL DVDD RFGND RFOUT RFVDD DESCRIPTION Chip enable data enable Supply voltage analog Power amplifier tank circuit Power amplifier tank circuit Ground analog clock data input Ground local oscillator Oscillator tank circuit Oscillator tank circuit Oscillator tank circuit resonator resonator Receiver transmitter enable Voltage stabilizer decoupling Data input stream Received data clock Received data output Ground digital Reference oscillator Reference oscillator Supply voltage digital Test Test input input Ground Transmitter output noise amplifier tank circuit noise amplifier tank circuit Supply voltage
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Data Sheet XE1201A Power Transceiver
RFOUT
RFGND
RFVDD
DVDD XTAL XTAL DGND CLKD VREF
AVDD AGND
LOGND
fig. TQFP package
Absolute Ratings
supply voltage storage temperature -55°C 150°C operating temperature -40°C 70°C
Electrical Characteristics
Tamb 433.92 MHz; frequency deviation; kbit/s pseudo random sequence unless otherwise specified
SYMBOL PARAMETER IDDR IDDT Operating supply voltage Reception supply current Transmission supply current
CONDITIONS
RXTX
13.5
Units
output power output power output power output power Clock running Clock stopped BER=1%, Rsource kbit/s kbit/s kbit/s Parallel real part Parallel capacitive part Parallel capacitive part Funw =FLO ±125 -106 -104
IDDS
Standby current Frequency range Transmitter output power
-109 -107 -102
sensitivity
ZOUT
input impedance output impedance Co-channel rejection
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Data Sheet XE1201A Power Transceiver
SYMBOL PARAMETER
CONDITIONS RFlevel RFS+3dB
Units
FDEV Tclk
Blocking immunity Maximum receiver input level Baseband filter bandwidth Local oscillator drift Local oscillator shift anti-alias filter bandwidth Frequency deviation Data rate Digital input/output level Digital input/output high level Clock wake-up time Receiver wake-up time Transmitter wake-up time Data set-up time Receive transmit switching time Transmit receive switching time clock rise time clock fall time clock frequency
Funw =FRF ±1MHz RFlevel RFS+3dB channel, BER=1% cutoff frequency Tamb +70°
+/-8
+/-15
ppm/°
programmable 3-wire programmable 3-wire
+/-4
+/-200 kbit/s
from cold start (see fig. from oscillator running (see fig. synchronizer bypassed from oscillator running (see fig. (see fig. (see fig. (see fig. synchronizer bypassed
Handling
pins withstand test accordance with MIL-STD-883F method 3015.6 (all pins towards substrate), human body model (2000V). output (pin only protected against negative voltage protection device towards VDD).
Functional Description
XE1201A controlled 3-wire serial microcontroller that addresses wires Serial Data, Serial Clock, Data enable) according format shown Figure stream bits into internal register pin8) with Most Significant (MSB) first shifted during high transition clock pin7). This serial programming enabled Data Enable pin2) which must zero before data transfer. high transition Data Enable validates register filling. Data retained long supply voltage (Vdd) present.
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Data Sheet XE1201A Power Transceiver
3-wire Data Format
first (table bits (D15 D14) determine register access according truth table below REGISTER NAME REGISTER REGISTER REGISTER USED
table Register Address
These three registers filled data according value D14. Register used XE1201A mode (transmission, reception standby modes) select receiver data rate. Register used central frequency adjustment during transmission. Register used frequency deviation set-up, transmitted power adjustment other auxiliary functions.
REGISTER FORMAT (D15=0, D14=0)
table Register Format
CONTROL MODE When this enables XE1201A transmit/receive mode chip enable control addressed pin15 (RXTX) pin1 (EN). further information this control mode, please refer RXTX description page When transmit/receive mode chip enable controls addressed A11. this mode, levels applied have effect. CLOCK CONTROL This used XE1201A internal clock start-up. When clock always running whatever state chip enable (A11 when A13=1 pin1 when A13=0). When clock activity determined chip enable (A11). CHIP ENABLE When blocks XE1201A deactivated (except clock However, 3-wire programmed disabled mode long present. This replaces Chip Enable (pin1) when A13=1. TRANSMIT/RECEIVE MODE When XE1201A receiving mode transmitting mode when This replaces RXTX (pin15) when A13=1 DEMODULATOR SYNCHRONIZER BYPASSING These bits used applications where synchronizer needed e.g. decrease receiver wake-up time receiver normal mode demodulator bypassed. outputs limiters available pin19 output) output). Bits must according table below.
table Receiver Mode with Demodulator Bypassed
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Data Sheet XE1201A Power Transceiver
receiver normal mode internal synchronizer switched off. data available output (pin19). CLKD (pin18) meaningless. this mode, preamble required clock synchronization synchronizer that minimum receiver wake-up time accessed. Bits must according table
table Receiver Mode with Synchronizer Switched
RECEIVER DATA RATE These bits used synchronizer data rate according following formula:
65574
[Hz]
Where unsigned decimal value bits (A5=MSB). inverse function gives value wanted data rate showed below:
ROUND
rate data transmitted should then accordingly (pin17). Note: when synchronizer bypassed (bits A9,A8,A7,A6), necessary program data rate. data demodulated accordingly incoming data rate.
REGISTER FORMAT (D15=0, D14=1)
table register format
B13, B12, B11, B10, OFFSET FREQUENCY These bits used calibrate oscillator central frequency (e.g. related resonator initial accuracy). frequency offset added subtracted frequency Local Oscillator while transmitting according following formula:
3906.25 [Hz]
where signed value bits (from +63). Bits expressed complement bits representation. offset thus range from -250000 (1000000) 246093.75 (0111111). TEST BITS These bits test purpose only. They must zero.
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Data Sheet XE1201A Power Transceiver
REGISTER FORMAT (D15=1, D14=0)
table register format
C13, TRANSMITTED OUTPUT POWER output power available RFOUT (pin29) adjusted with according table below. OUTPUT POWER
table transmitter output power control bits
DATA INVERSION received data stream inverted when this C10, TEST BITS These bits must always C10=1 C9=0 TRANSMITTED OUTPUT AMPLIFIER ENABLE When this disables transmitter output amplifier whatever transceiver state TRANSMITTED DATA This replaces (pin17) when register thus allows data transmission 3-wire bus. MODULATOR FREQUENCY DEVIATION These bits used adjust frequency deviation modulator according following formula:
FDEV 3906
[Hz]
Where unsigned decimal value bits frequency deviation transmitter theoretically adjusted 496093.75 However, should noticed that proper behavior XE1201A demodulator, frequency deviation must greater than data rate (FDEV>DR) smaller than baseband filter bandwidth (BW). addition, FDEV must smaller than anti-alias filter bandwidth (TBW).
registers default values
After applied, internal 3-wire registers initialized with values shown tables below.
table register default value
table register default value
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Data Sheet XE1201A Power Transceiver
table register default value
After power-up, XE1201A following initial state: RXTX (pin15) (pin1) control mode, clock stopped, kbits/s data rate, output power frequency deviation. Ready transmit receive.
RXTX (pin15) (pin1)
RXTX (receive/transmit) (chip enable) activated when control (A13) zero. this mode, XE1201A switched switched transmit receive mode with (EN) (RXTX) explained table figure
RXTX
MODE CHIP DISABLED TRANSMIT MODE RECEIVE MODE
table RXTX pins truth table
synchronization receiving mode
operation based advanced digital controlled ALU. Care must taken while using particularly when receiver permanent listening mode (please refer XE1201A application information documentation). internal demodulator XE1201A needs frame synchronization bits ensure proper clock synchronization. synchronization frame must sequence sent alternatively.
Wake-up time
wake-up time depends clock state. clock kept running (A12=1), wake-up time max. clock off, clock switched before wake-up rest XE1201A explained figure
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Data Sheet XE1201A Power Transceiver
Timing Figures
A,B,C13
A,B,C12
A,B,C1
A,B,C0
Figure timing diagram 3-wire
ready receive
ready transmit
RXTX
RECEIVE MODE
TRANSMIT MODE
Figure timing diagram RXTX control pins
ready transmit receive Tclk
Figure timing diagram chip wake-up (from cold start)
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Data Sheet XE1201A Power Transceiver
(pin
Measurement conditions: kbit/s RFlevel -102
Figure Received data stream with internal synchronizer bypassed
(pin
CLKD (pin
Measurement conditions: kbit/s RFlevel -102
Figure Received data stream with internal synchronizer synchronized data clock output
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Data Sheet XE1201A Power Transceiver
components side (front)
copper side (back)
Figure reference board layout (not actual scale)
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Data Sheet XE1201A Power Transceiver
Analog Description
illa
pin22
illa
pin29
Figure analog pins description
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Data Sheet XE1201A Power Transceiver
Application Information
12nH ustrip 12nH ustrip
10nF
2.2pF
AVDD
AGND
DVDD
DGND
FROM ANTENNA
18nH ustrip 2.2pF 2.2pF
DEMODULATOR SYMBOL SYNCHRO
CLKD
DATA TPUT
CONTROL
3.3pF 18nH ustrip
POWER MANAGEMENT
CHIP CONTROL
POWER
RFOUT
RXTX
2.2pF
ANTENNA
DATA INPUT
VREF
10nF
CLOCK
RFGND
RFVDD
LOGND
XTAL
2.2pF
27nH
10nF
12nH
12nH
12nH 12nH
RESON ATOR R02101A
HC43
10nF
Figure application information
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Data Sheet XE1201A Power Transceiver
Mechanical Data Package
DIMENSIONS Body Thickness Footprint (Body+)
VALUE 1.00 2.00 1.20 0.05 min/0.15 1.00 9.00 7.00 9.00 7.00 0.60 0.80 0.35 0.10 0.20 0°-7°
Package Information TQFP
TOLERANCE ±0.05 ±0.25 ±0.10 ±0.25 ±0.10 +0.15/-0.10 BASIC ±0.05
XEMICS 2002 rights reserved. Reproduction whole part prohibited without prior written consent copyright owner. information presented this document does form part quotation contract, believed accurate reliable changed without notice. liability will accepted publisher consequence use. Publication thereof does convey imply license under patent other industrial intellectual property rights. XEMICS PRODUCTS DESIGNED, INTENDED, AUTHORIZED WARRANTED SUITABLE LIFE-SUPPORT APPLICATIONS, DEVICES SYSTEMS OTHER CRITICAL APPLICATIONS. INCLUSION XEMICS PRODUCTS SUCH APPLICATIONS UNDERSTOOD UNDERTAKEN SOLELY CUSTOMER'S RISK. Should customer purchase XEMICS products such unauthorized application, customer shall indemnify hold XEMICS officers, employees, subsidiaries, affiliates, distributors harmless against claims, costs damages attorney fees which could arise.
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