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information contained herein subject change without notice. Philips continually working improve quality reliability products. Nevertheless, semiconductor devices general malfunction fail their inherent electrical sensitivity vulnerability physical stress. responsibility buyer, when utilizing Philips products, observe standards safety, avoid situations which malfunction failure Philips product could cause loss human life, bodily injury, damage property. developing your designs, please ensure that Philips products used within specified operating ranges forth most recent product specifications. Also, please keep mind precautions conditions forth Philips Semiconductor Reliability Handbook. information contained herein presented only guide applications products. responsibility assumed Philips infringements patents other rights third parties which result from use. license granted implication otherwise under patent patent rights Philips others. Application Information Applications that described herein these products illustrative purposes only. Philips Semiconductors make representation warranty that such applications will suitable without further testing modification. Life support These products designed life support appliances, devices systems where malfunction these products reasonably expected result personal injury. Philips Semiconductors customers using selling these products such applications their risk agree fully indemnify Philips Semiconductors damages resulting from such application. Right make changes Philips Semiconductors reserves right make changes, without notice, products, including circuits, standard cells, and/or software, described contained herein order improve design and/or performance. Philips Semiconductors assumes responsibility liability these products, conveys license title under patent, copyright, mask work these products, makes representations warranties that these products free from patent, copyright, mask work right infringement, unless otherwise specified. Copyright Philips Electronics North America Corporation 1998 rights reserved. Printed U.S.A. Release date: 10/98 Document order number: 9397 04338
Documentation developed Andrew Napell International Consulting Group 2021 Alameda, Suite Jose, California 95126 http://www.icg-sj.com
author wishes thank following persons: Khan, Bill Kolb, Frank Lee, Mary Ohanessian Sumner, Charlie Rehor, Greg Goodhue, Zhimin Ding, Slivkoff, Jerry Hao, Jane Zheng, Hartmut Habben, Eissa, Ismael Nass-Duce, Carol McCarthy, Mark Powell.
Table Contents
List Figures.xiii List Tables .xvii Preface .xxi Chapter Introduction.1
About Serial Communications Controller. Overview XA-SCC Architecture. 1.2.1 1.2.2 1.2.3 1.2.4 1.2.5 1.2.6 XA-SCC Block Diagram Communications Between Other On-Chip Devices. Receive (Rx) Data Flow Simplified. Transmit (Tx) Data Flow Simplified Options: Autobaud V.54/2047 Option SCC0, SCC1, SCC2: Interface.
1.2.7 Communications Between Off-Chip Devices: Interface6 1.2.8 Input/Output Using Multifunction Pins Function Multiplexing Major Features XA-SCC. Typical Applications. 1.4.1 1.4.2 ISDN Terminal Adapter Four Independent Serial Channels
Chapter XA-SCC
Introduction. Timers. 2.2.1 2.2.2 Timer/Counters Watchdog Timer.
Serial Ports (UARTs) Event Interrupts Internal Data Memory Addressing Scope. 2.5.1 2.5.2 Internal Data Memory. Data Memory Addressing Scope
Table Contents
2.10
Internal Code Memory Memory Mapped Registers (MMRs). ResetOut 2.8.1 Operation ResetOut During After Power-Up. External WAIT timing. Special Function Register (SFR) Modifications 2.10.1 2.10.2 2.10.3 2.10.4 2.10.5 2.10.6 2.10.7 2.10.8 2.10.9 (46Ah). BTRH (469h) BTRL (468h). MRBL (496h). MRBH (497h) MICFG (499h) IPA6 (4A6h). IPA7 (4A7h). PCON (404h)
2.10.10 RSTSRC (463h) 2.10.11 XA-G3 SFRs Which Have Been Removed From XA-SCC
Chapter Memory Interface (MIF) DRAM Controller.23
Introduction. Architecture 3.2.1 3.2.2 3.3.1 3.3.2 3.3.3 3.4.1 3.4.2 3.5.1 3.5.2 3.5.3 3.6.1 Block Diagram. Register Bank Banks Bank Bank Swapping Generic Memory Interface Addressing. Generic Memory Interface Timing. DRAM Burst Reads. DRAM Interface Addressing. DRAM Interface Timing. DRAM Refresh Cycle Timing
Memory Banks
Generic Memory Interface
DRAM Interface
DRAM Refresh
Table Contents
WAIT Size8. 3.7.1 3.7.2 3.7.3 WAIT External WAIT Timing Size8 Channel High Priority Override (DMA CHPO). MRBH MRBL.
3.10 3.11
Arbiter. 3.8.1 3.9.1 XA-SCC Memory Mapped Register Relocation. Configuration Example Special Function Register Descriptions. 3.11.1 3.11.2 3.11.3 3.11.4 3.11.5 BTRH: Timing Register High Byte (SFR 469h). BTRL: Timing Register Byte (SFR 468h) MRBH: Base Address High Byte (SFR 497h) MRBL: Base Address Byte (SFR 496h) MICFG: Memory Interface Configuration (SFR 499h). BiCFG: Bank Configuration BiAM: Bank Base Address/DRAM Address Multiplexer Control BiTMG: Bank Timing MBCL: Memory Bank Configuration Lock RFSH: Refresh Timing
3.12
Memory Mapped Register Descriptions 3.12.1 3.12.2 3.12.3 3.12.4 3.12.5
Chapter Direct Memory Access (DMA) Controller
Introduction. Channel Architecture Data Buffer Management Main Memory. 4.3.1 4.3.2 4.4.1 4.4.2 4.4.3 4.4.4 4.4.5 4.4.6 Circular Buffers Linear Buffers. General Principles DMA. Chaining Non-SDLC/HDLC Chaining. SDLC/HDLC Chaining. Stop (Terminal Count) Periodic Interrupt.
Serial Transmit Transfer Process DMA).
Table Contents
Serial Receive Transfer Process DMA) 4.5.1 4.5.2 4.5.3 4.5.4 4.5.5 4.5.6 4.5.7 4.5.8 General Principles SDLC/HDLC Packet Status Byte. SDLC/HDLC Partial Byte Periodic Interrupt. Asynchronous Character Time Out. Asynchronous Character Match. Typical Response MCIP Interrupt
Interrupts Register Descriptions 4.7.1 4.7.2 4.7.3 4.7.4 4.7.5 4.7.6 4.7.7 4.7.8 4.7.9 4.7.10 Global Interrupt Register Control Register Segment Register Buffer Base Register Buffer Bound Register. Address Pointer Register Byte Count Register FIFO Control Status Register Data FIFO Registers Character Time Register (RxCTOR).
Chapter Serial Communications Controller (SCC)
Introduction. Features SCC. Architecture. Communication Modes. 5.4.1 5.4.2 5.4.3 5.4.4 5.4.5 5.4.6 5.5.1 5.5.2 5.5.3 Asynchronous Mode SDLC/HDLC Mode. Monosync Mode. Bisync Mode. External Sync Mode Transparent Mode. Autobaud Baud Rate Generator Baud Rate Generator Example
Baud Rate Generator
Table Contents
Clocks 5.6.1 Clock Issues When (and when not) Using 5.6.2 5.6.3 5.6.4 SCC0 Clock Discussion SCC0 Clock Inputs. SCC0 Clock Outputs Channel Interrupt Groups Bits Bits Interrupt Priorities Receive Interrupts Transmit Interrupts External/Status Interrupts Write Register Command Register Write Register Transmit/Receive Interrupt Control Write Register SDLC Enhancement. Write Register Receiver Control. Write Register Parameters Modes. Write Register Transmitter Control. Write Register Station Address/Sync Char Low/Async Match Char Write Register HDLC Flag/Sync Char High/Async Match Char Write Register Data Buffer Write Register Channel Reset/Master Interrupt Enable Write Register Miscellaneous Control. Write Register Clock Mode Control. Write Register Baud Rate Generator Lower Byte Write Register Baud Rate Generator Upper Byte Write Register Miscellaneous Control Bits Write Register External/Status Interrupt Control Write Registers Async Match Characters Read Register Interrupt Status Bits. Read Register Special Receive Condition Read Register Interrupt Pending. Read Register SDLC Byte Count Lower Byte. Read Register SDLC Byte Count Upper Byte. Read Register Data Buffer. Read Register Miscellaneous Status Bits
Interrupts. 5.7.1 5.7.2 5.7.3 5.7.4 5.7.5 5.7.6
Write Registers 5.8.1 5.8.2 5.8.3 5.8.4 5.8.5 5.8.6 5.8.7 5.8.8 5.8.9 5.8.10 5.8.11 5.8.12 5.8.13 5.8.14 5.8.15 5.8.16 5.8.17
Read Registers 5.9.1 5.9.2 5.9.3 5.9.4 5.9.5 5.9.6 5.9.7
Table Contents
Chapter Autobaud.167
Introduction. Autobaud Detection Clocks Valid Baud Rates 6.3.1 6.3.2 6.3.3 Autobaud Source Clock Valid Baud Rates Acceptable Baud Rate Error Margins.
Autobaud Echo Autobaud Interrupts Using Autobaud 6.6.1 6.7.1 6.7.2 Write Register Configuration Autobaud. BDAEE: Autobaud Echo Enable BDCS: Autobaud Control Status Autobaud Register Descriptions
Chapter V.54/2047 Units .179
Introduction. Assigning V.54/2047 Units 7.2.1 7.2.2 7.3.1 7.3.2 7.4.1 7.4.2 Assigning V.54/2047 Unit Assigning V.54/2047 Unit V.54 Receive. 2047 Receive V.54 Generate. 2047 Generate
V.54 2047 Receive
V.54 2047 Generate
V.54/2047 Interrupts V.54/2047 Register Descriptions 7.6.1 7.6.2 7.6.3 7.6.4 7.6.5 VxCS: Unit Control Status Register. VxCFG: Unit Configuration Register VxTCL: Unit Receiver Threshold Counter Byte VxTCH: Unit Receiver Threshold Counter High Byte. VxEC: Unit Receiver Error Counter.
V.54 2047 Circuits
viii
Table Contents
Chapter Interface.195
Introduction. Interface Architecture. 8.2.1 8.3.1 8.3.2 8.4.1 Interface Block Diagram XA-SCC Uses Channel Request Grant. Assigning SDS1 SDS2. Maximum Frequency L1Clk Signals
Interface Clocks Assigning Channels SCCs Channel Masking Enable 8.6.1 8.6.2 Channel Masking. Channel Enable
Configuration Example Interface Register Descriptions. 8.8.1 8.8.2 Control Register. DataMask Register.
Chapter Interface .213
Introduction. State Machine Timing 9.3.1 9.3.2 Data Rate Frequency SCPClk Description Cycle.
Interrupts Register Descriptions 9.5.1 9.5.2 9.5.3 SCPCFG: Configuration SCPD: Data Byte SCPCS: Control Status.
Chapter Interrupts.
10.1 10.2 10.3 10.4 Introduction. Overview Native Interrupts 10.2.1 Addressing Primer XA-SCC Event Interrupts. High Priority Software Interrupts.
Table Contents
10.5 10.6 10.7 10.8 10.9
Interrupt. Autobaud V.54/2047 Interrupts. Interrupts. Interrupts External Interrupt (INT2).
10.10 External Interrupts Timers
Chapter XA-SCC Pins .241
11.1 11.2 11.3 Introduction. XA-SCC Signals Functions Groupings Function. 11.3.1 11.3.2 11.4 11.4.1 11.4.2 11.4.3 11.4.4 11.4.5 11.5 11.5.1 11.5.2 11.5.3 11.5.4 11.5.5 11.5.6 11.5.7 11.5.8 11.5.9 Functional Groups Typical ISDN Configuration Functional Groups Independent Serial Channels Review Ports Port Naming Conventions Port Configurations. Multifunction Programming Example Multiplexing Control Register (PMCR), 2D0h. P3.0_CS4_RAS4_RTClk1 P3.1_CS5_RAS5_RTS1 P3.2_Timer0_ResetOut P3.3_BRG1_Timer1_Sync1. P3.4_CTS1 P3.5_RxD1. P3.6_TxD1 P3.7_INT 1_TRClk1. P1.0_RxD2.
Multifunction Pins
Multifunction Schematics.
11.5.10 P1.1_TxD2 11.5.11 P1.2_RTClk2. 11.5.12 P1.3_TRClk2. 11.5.13 P1.4_CD2 11.5.14 P1.5_CTS2 11.5.15 P1.6_RTS2 11.5.16 P1.7_BRG2_Sync2. 11.5.17 CD1_Int2 (Input Only)
Table Contents
11.5.18 P2.0_RxD3. 11.5.19 P2.1_TxD3 11.5.20 P2.2_RTClk3. 11.5.21 P2.3_ComClk_TRClk3. 11.5.22 P2.4_CD3 11.5.23 P2.5_CTS3 11.5.24 P2.6_RTS3 11.5.25 P2.7_Sync3_BRG3. 11.5.26 P0.0_Sync0_BRG0_SDS2 11.5.27 P0.1_RTS0_L1RQ 11.5.28 P0.2_CTS0_L1GR 11.5.29 P0.3_CD0_L1SY1. 11.5.30 P0.4_TRClk0_SDS1 11.5.31 P0.5_RTClk0_L1Clk 11.5.32 TxD0_L1TxD. 11.5.33 RxD0_L1RxD 11.5.34 P0.6_SCPTx 11.5.35 100: P0.7_SCPRx. 11.6 XA-SCC Pinout.
Appendix XA-SCC Programming Examples .289
Introduction. Boot Code Bank Bank Swapping (Assembly) SCC3/DMA3 Async Mode SCC1/DMA1 Clear Channel with (C). SCC3/DMA3 Clear Channel with NMSI SCC0/DMA0 HDLC Chaining with (C). Note About Reset External/Status Interrupts Command
Appendix Timing Examples.309
SRAM other generic memory) Timing Examples DRAM Timing Examples
Appendix Addresses.339
Special Function Register (SFR) Addresses Memory Mapped Register (MMR) Addresses
Table Contents
Appendix V.54 2047 Generator Output .351
V.54 Generator Scrambled Zeros Output (VxGP V.54 Generator Scrambled Ones Output (VxGP 2047 Generator Output.
Glossary .355 Index .360
List Figures
Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure 4-10 Figure Figure Figure Figure Figure Figure Figure Figure Simplified Block Diagram XA-SCC ISDN Terminal Adapter. ISDN Terminal Adapter, showing channels Four Independent Serial Channels Logic Showing Details ResetOut Block Diagram (showing address strobe generation only) DRAM Refresh Cycle. External WAIT States. Typical circuits WAIT_Size8 Interconnections Configuration Example. Register Circular Buffer Non-SDLC/HDLC Chaining packet format memory SDLC/HDLC Chaining Packet format memory SDLC/HDLC Chaining Flow-Chart. SDLC/HDLC packet format main memory. SDLC/HDLC Residue Bits Memory Images "Partial Byte" Character Time Timer. Relevant MMRs Asynchronous Character Match. Interrupt Structure Block Diagram Typical Channel Baud Rate Generator. clock options when (and when not) using IDL. SCC0 Clocks (see Sections 5.6.3 5.6.4). SCC1 Clocks. SCC2 Clocks. SCC3 Clocks. SCC0/SCC1 Interrupt Structure.
xiii
List Figures
Figure Figure 5-10 Figure 5-11 Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure 8-10 Figure Figure Figure 10-1 Figure 11-1 Figure 11-2 Figure 11-3 Figure 11-4 Figure 11-5 Figure 11-6 Figure 11-7 Figure 11-8
Continuation Interrupt Structure, Showing Both Interrupt Groups Least Significant First, Bits Character Most Significant First, Bits Character Autobaud Detection State Diagram Logic Logic Logic Logic V.54 Generator V.54 Receiver 2047 Generator. 2047 Receiver. Interface Block Diagram Clocks SCC0 Clocks SCC1 Clocks SCC2 DataMask Bits Channel Time Slots DataMask P0[4] Affecting SDS1 SDS2. Masking, Showing Clocks SCC1 SCC2. Channel Grant, Showing Clocks SCC0. 8-Bit Frame ("Short Frame") Format 10-Bit Frame Format Block Diagram Cycle Timing with both Polarities SCPClk XA-SCC Event Interrupt Structure Typical ISDN: SCC0 SCC2 using IDL, SCC3 using NMSI interface Four Independent Serial Channels Multifunction Example, using Control Register (PMCR) Showing PMCR[3]
List Figures
Figure 11-9 Figure 11-10 Figure 11-11 Figure 11-12 Figure 11-13 Figure 11-14 Figure 11-15 Figure 11-16 Figure 11-17 Figure 11-18 Figure 11-19 Figure 11-20 Figure 11-21 Figure 11-22 Figure 11-23 Figure 11-24 Figure 11-25 Figure 11-26 Figure 11-27 Figure 11-28 Figure 11-29 Figure 11-30 Figure 11-31 Figure 11-32 Figure 11-33 Figure 11-34 Figure 11-35 Figure 11-36 Figure 11-37 Figure 11-38 Figure 11-39 Figure 11-40 Figure
100. Typical SRAM 16-Bit Read Cycle
List Figures
Figure Figure Figure Figure Figure Figure Figure Figure Figure B-10 Figure B-11 Figure B-12 Figure B-13 Figure B-14 Figure B-15 Figure B-16 Figure B-17 Figure B-18 Figure B-19 Figure B-20 Figure B-21 Figure B-22 Figure B-23 Figure B-24 Figure B-25 Figure B-26 Figure B-27 Figure B-28 Figure B-29
SRAM 16-Bit Read Cycle with Longer Access Time SRAM 16-Bit Read Cycle with BLE/BHE Delay. SRAM 16-Bit Read Cycle with Longer Recovery Time. Typical SRAM 16-Bit Write Cycle SRAM 16-Bit Write Cycle with Longer Access Time SRAM 16-Bit Write Cycle with BLE/BHE Delay. SRAM 16-Bit Write Cycle with Longer Access Time BLE/BHE Delay. SRAM 16-Bit Write Cycle with Delay SRAM 16-Bit Write Cycle with Delay BLE/BHE Conversion WEL/WEH. SRAM 16-Bit Write Cycle with Longer Recovery Time. Typical SRAM Word Read Cycle 8-Bit Bus, 2-Word Burst Code Fetch 16-Bit SRAM 8-Bit Word Read Cycle with Delay Typical SRAM Word Write Cycle 8-Bit Bus. SRAM 8-Bit Word Write Cycle with converted SRAM 8-Bit Word Write Cycle with Delay Typical DRAM 16-Bit Word Write Cycle DRAM Word Write Cycle 16-Bit Bus, with longer delay, Longer Recovery Time. Typical DRAM 8-Bit Word Write Cycle Typical DRAM 16-Bit Data Read Cycle DRAM 16-Bit Data Read Cycle, with Longer Recovery Time. Typical Fast Page Mode DRAM Burst Code Read (x2) 16-Bit Fast Page Mode DRAM Burst Code Read (x2) 16-Bit Bus, with Longer Delay Fast Page Mode DRAM Burst Code Read (x2) 16-Bit Bus, with Longer Access Time Fast Page Mode DRAM Burst Code Read (x2) 16-Bit Bus, with Longer Recovery Time. Typical DRAM Burst Code Read (x2) 16-Bit Bus. DRAM Burst Code Read (x2) 16-Bit Bus, with Longer Delay. DRAM Burst Code Read (x2) 16-Bit Bus, with Longer Access Time DRAM Burst Code Read (x2) 16-Bit Bus, with Longer Recovery Time
List Tables
Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Access Internal External Data Memory Register Bank Size Address Range Select Banks Size Base Address Select (ROM) (DRAM) Control Bits Before After Swapping. (ROM) (Generic) Control Bits Before After Swapping. BiMX1 BiMX0 Configuration DRAM Column Address Multiplexing. Arbiter Priority Rankings Registers. Modes Byte Count LastFrag Options, non-SDLC/HDLC Chaining. Byte Count LastFrag options, SDLC/HDLC Chaining. SDLC/HDLC Residue Bits Data Positions Last Byte packet Last Matched Codes Interrupt Bits. Programming BRGClk PClk 14.7456 (CClk 29.4912 MHz) Maximum Clock Frequencies Addresses Interrupts. External/Status Interrupts Write Register Positions Write Register Positions Baud RateM with CClk 29.4912 Baud RateM Error Windows Number CClk Cycles Recommended Write Register Values with Autobaud. V.54/2047 Unit Assignment Bits V.54/2047 Unit Assignment Bits V.54 2047 Interrupt Conditions
xvii
List Tables
Table 10-1 Table 10-2 Table 10-3 Table 10-4 Table 10-5 Table 10-6 Table 10-7 Table 10-8 Table 10-9 Table 10-10 Table 10-11 Table 10-12 Table 11-1 Table 11-2 Table 11-3 Table 11-4 Table 11-5 Table 11-6 Table 11-7 Table 11-8 Table 11-9 Table 11-10 Table 11-11 Table 11-12 Table 11-13 Table 11-14 Table 11-15 Table 11-16 Table 11-17 Table 11-18 Table 11-19 Table 11-20 Table 11-21
Native Interrupts XA-SCC Event Interrupts Autobaud V.54/2047 Interrupt Flags SCC0 Interrupts SCC1 Interrupts SCC2 Interrupts SCC3 Interrupts Interrupts. Interrupts. Interrupts. Interrupts. GPI/O Configurations External Event Interrupts XA-SCC Signals Functions Port Configuration Modes Programming Programming Programming Programming Programming Programming Programming Programming Programming Programming Programming Programming Programming Programming Programming Programming Programming Programming (Input Only) Programming
xviii
List Tables
Table 11-22 Table 11-23 Table 11-24 Table 11-25 Table 11-26 Table 11-27 Table 11-28 Table 11-29 Table 11-30 Table 11-31 Table 11-32 Table 11-33 Table 11-34 Table 11-35 Table 11-36 Table 11-37 Table 11-38 Table Table Table Table
Programming Programming Programming Programming Programming Programming Programming Programming Programming Programming Programming Programming Programming Programming (Output Only). Programming (Input Only) Programming Programming Initial Configuration, Before Swapping. Final Configuration, After Swapping Special Function Register (SFR) Addresses Memory Mapped Register (MMR) Addresses
List Tables
Preface
This book provides information about Philips Serial Communications Controller (XA-SCC). typographic conventions used book explained below.
Convention Overline Square brackets,
Meaning overlined signal name (for example RAS) inverse that signal. Contain number(s). Example: identifies whereas [4:2] identifies bits
addition, this book makes gray shadow boxes, like this one, provide notes warnings.
Preface
xxii
Preface
Chapter
Introduction
XA-SCC
Timers Interrupts Autobaud DRAM Controller Interface Interface Ports Function External components such Physical I/F, U-Chip, S/T, RS-232, etc.
External components such DRAM, SRAM, Flash, ROM, Ports, etc.
V.54/2047
Contents About Serial Communications Controller. Overview XA-SCC Architecture. Major Features XA-SCC. Typical Applications.
Chapter Introduction
About Serial Communications Controller
About Serial Communications Controller
Serial Communications Controller (XA-SCC) driven, multi-channel, multi-protocol, serial communications controller with embedded high-performance 16-bit 80C51-XA core. Because flexible architecture extensive programmability, XA-SCC able provide bidirectional, full-duplex, serial communications many four channels simultaneously, with each channel using different communications protocol desired. XA-SCC incorporates numerous features reduce system cost. virtue resizable memory banks, each with dedicated Chip Select (CS) output, many external memory devices connected XA-SCC using external glue logic. Additionally, XA-SCC provides on-chip DRAM controller, which supports DRAM sizes MBytes. heart XA-SCC four independent, high-speed, bidirectional Serial Communications Controllers (SCCs). Each interfaces with system through dedicated pair channels; channel Transmit (Tx) Receive (Rx). SCCs based industry standard design, they incorporate extensive architectural modifications functional improvements which greatly enhance their programmability, flexibility, ease-of-use. four SCCs support different protocols, each protocol implemented industry standard (Interchip Digital Link) NMSI (Non-Multiplexed Serial Interface) physical layer interface. clocked external clock sources, internally programmable Baud Rate Generator. Since each SCC's transmitter receiver operate independently, they clocked independently. Each dedicated Autobaud circuit, which provide automatic baud rate detection Baud Rate Generator configuration channel. Three SCCs internally connected on-chip Interface, glueless interface Layer devices. Thus connected, three SCCs efficiently support ISDN channels. addition, four SCCs provide support seven standard NMSI interface signals: RxD, TxD, RClk, TClk, RTS, CTS, Other modem control signals, like DTR, easily supported under software control through General Purpose Input/Output (GPI/O) Ports. addition their multiple clock options, Autobaud capabilities, Interface connectivity, each direct access V.54/2047 line testing protocol generator receiver.
Chapter Introduction
Overview XA-SCC Architecture
XA-SCC's core high performance 16-bit 80C51-XA. CPU, with enhanced instruction architecture, provides extensive bit-oriented operations addition support multi-tasking operating systems high-level languages. 24-bit address space (16M Bytes), 16-bit stack pointers general purpose registers, offers both 16-bit 8-bit access. Since most instructions between four bytes length, core executes code very efficiently. also offers Power-Down Idle power reduction modes, hardware support multi-tasking software. control communications with U-Chip, and/or other physical layer devices, uses on-chip Interface. This interface bidirectional, full duplex, synchronous communication bus, similar Microwire. General Purpose Port (GPI/O) functions used provide enables (CS) slave devices, number supportable slave devices limited only number available port pins.
1.2.1
Overview XA-SCC Architecture
XA-SCC Block Diagram
simplified block diagram XA-SCC appears Figure 1-1. depicted figure, XA-SCC's architecture revolves around nine functional blocks devices) primary importance: CPU, DRAM Controller Memory Interface (MIF), DMA, SCC, Autobaud, V.54/2047, Interface, Interface, Function MUX.
XA-SCC
Timers Interrupts Autobaud DRAM Controller Interface Interface Ports Function External components such Physical I/F, U-Chip, S/T, RS-232, etc.
External components such DRAM, SRAM, Flash, ROM, Ports, etc.
V.54/2047
Figure
Simplified Block Diagram XA-SCC
Chapter Introduction
Overview XA-SCC Architecture
1.2.2
Communications Between Other On-Chip Devices
communicates with other devices chip three fundamental ways: issues commands writing device's control registers. Nearly control registers, devices other than itself, Memory Mapped Registers (MMRs). exception DRAM Controller MIF, which also uses Special Function Registers (SFRs). SFRs discussed Chapter "XA-SCC CPU." MMRs discussed Chapter "XA-SCC CPU," again Chapter "Memory Interface (MIF) DRAM Controller." gathers information about status device reading device's status registers. Nearly status registers MMRs. Some devices interrupt setting more interrupt flags. Some interrupt flags bits some bits. Furthermore, some interrupt flags cleared writing flag's position, some cleared writing `1'. Details found individual register descriptions relevant device.
1.2.3
Receive (Rx) Data Flow Simplified
following typical process whereby XA-SCC receives data from physical layer interface, stores external memory: Receive data shifted bit-by-bit into SCC's Shift Register. data have been time-demultiplexed Interface, depending configuration. When complete character been assembled, transferred SCC's Data Buffer. While next character accumulating Shift Register, dedicated channel fetches character, places Data FIFO Registers, asserts request MIF. When grant given that channel, character written external memory. Data FIFOs four bytes deep, grant delayed long five "Byte-Times" (four bytes Data FIFO plus byte Data Buffer) without risk over-writing data. Even highest serial data-rates, grant normally received long before Data FIFO fills Notice that when above process functioning normally, intervention required.
Chapter Introduction
Overview XA-SCC Architecture
1.2.4
Transmit (Tx) Data Flow Simplified
following typical process whereby XA-SCC fetches data from external memory, transmits physical layer interface: Data transmitted placed SCC's Data Buffer, from where they automatically transferred Shift Register when becomes available. Upon being shifted Shift Register, data time-multiplexed Interface, depending configuration. Each time fetches character from Data Buffer places Shift Register, signals channel that Data Buffer empty. While character being shifted out, channel fetches next byte from Data FIFO places SCC's Data Buffer. Since always fetches bytes from even address external memory, after every second byte transferred SCC, channel asserts request MIF. When grant given that channel, more bytes fetched from external memory placed DMA's Data FIFO. grant delayed long four "byte-times" (two bytes Data FIFO, plus byte Data Buffer byte Shift Register) without risk underrun (running data Shift Register). Even highest serial data-rates, grant normally received long before four byte-times have elapsed. Notice that when above process functioning normally, intervention required. SCCs subject Chapter "Serial Communications Controller (SCC)," subject Chapter "Direct Memory Access (DMA) Controller."
1.2.5
Options: Autobaud V.54/2047
Each access hardware Autobaud detector hardware V.54/2047 transceiver. Autobaud used with that operating Asynchronous mode. When Autobaud enabled SCC, automatically detects baud rate, number data bits character only), parity searching incoming data stream certain character sequences. When Autobaud detection sequence successfully completed, Autobaud circuit will program channel's Baud Rate Generator, configure Data Bits, well Even, Odd, Parity. channel will then automatically enabled Receive.
Chapter Introduction
Overview XA-SCC Architecture
hardware transceivers which support V.54/2047 line testing standards attached each SCC. During V.54/2047 line testing sequences, V.54/2047 units send interrupts CPU, determine quality transmission line reading V.54/2047 units' status registers. Autobaud circuits subject Chapter "Autobaud," V.54/2047 circuits subject Chapter "V.54/2047 Units."
1.2.6
Option SCC0, SCC1, SCC2: Interface
SCC0, SCC1, SCC2 internally connected on-chip Interface, glueless interface Layer devices. Thus connected, three SCCs efficiently support ISDN channels, while Interface time-multiplexes demultiplexes outgoing incoming serial data streams. Other configurations also available; individual assigned both Channels simultaneously. subject Chapter "IDL Interface."
1.2.7
Communications Between Off-Chip Devices: Interface
Interface provides means communicate with U-Chip, and/ other off-chip devices, using bidirectional, full duplex, synchronous communication bus, similar Microwire. Interface subject Chapter "SCP Interface."
1.2.8
Input/Output Using Multifunction Pins Function Multiplexing
XA-SCC multifunction pins which highly programmable. many four separate functions might share single pin, function multiplexing allows software choose particular function given pin. Virtually functional blocks XA-SCC multifunction pins various related purposes. Since would prohibitively complex show these signal paths XA-SCC Simplified Block Diagram (Figure 1-1), multifunction pins function multiplexing have been grouped into "virtual functional block" labeled "Pin Function MUX." Multifunction pins function multiplexing subject Chapter "XA-SCC Pins."
Chapter Introduction
Major Features XA-SCC
Major Features XA-SCC
16-Bit maximum clock frequency Separate MByte Code MByte Data Address Spaces, Unified Code/Data Space Dynamic Sizing, 8-bit wide Data access Bytes Internal (On-Chip) Data Memory Watchdog Timer with output ResetOut Enhanced Counter/Timers Interrupt Controller with Maskable Event Interrupts General Purpose Input/Output (GPI/O) Port pins, with four configurations available Enhanced instruction set, tailored high-level language support, which includes intensive logic operations, fast signed unsigned multiply divide Multi-tasking features, including segmented data memory banked registers, support fast context switching Serial Communications Controllers Four independent, high-speed, driven, full-duplex serial communication channels Data rates bits second sustained eight wires simultaneously Asynchronous, SDLC/HDLC, Monosync, Bisync, External Sync, Transparent operating modes Optional hardware-based automatic generation checking FM0, FM1, NRZ, NRZI data encoding Multiple clock options Programmable Baud Rate Generators Dedicated hardware Autobaud circuit each SCC, service 921.6 Kbps clock prescaler synchronous support Auto-Echo Local-Loopback modes
Chapter Introduction
Major Features XA-SCC
Interface Three SCCs connect on-chip Interface separate assigned each time-multiplexed 2B+D channels Flexible Interface architecture allows many alternate configurations Memory Interface (MIF) Direct, glueless interface both DRAM, well SRAM, Flash, EPROM, ROM, other generic memory types Memory Banks, each with dedicated Chip Select (CS) output Bank (boot bank) supports generic memory, Code Space, Data Space, both. Supports bank swapping with Bank Banks support DRAM generic memory, Code Space, Data Space, both Dynamic sizing: Each bank either 16-bits wide DRAM controller supports DRAMs between KBytes MBytes bank, total MBytes Programmable Refresh Timing, before refresh generator Programmable timing Support external WAIT Intelligent Arbiter assign access priorities between Refresh, access, access Direct Memory Access (DMA) Controller Eight channels, dedicated each four serial channels 4-Byte FIFO Data Buffer each channel (plus bytes each SCC) architecture specifically designed efficiently implement circular buffers external memory Circular buffers large KBytes, greatly reducing interrupt response requirements operating SDLC/HDLC mode with circular buffers allows reception transmission multiple HDLC packets with need service interrupts per-packet basis Urgency based dynamic prioritization access external memory
Chapter Introduction
Major Features XA-SCC
Autobaud dedicated hardware Autobaud circuit each Support (asynchronous) baud rates 921.6 Kbps, data bits, with without parity, when using 29.4912 system clock Optional Autobaud Echo mode V.54 2047 Circuits independent V.54/2047 transceivers implemented hardware SCCs doing V.54/2047 line testing simultaneously Interface Support many slave devices there available GPI/O Port pins Selectable inverted non-inverted clock polarities Selectable rates, from 1/32 system clock rate Selectable data frame length, from bits Memory Mapped Registers control configuration registers most XA-SCC functions read/write Memory Mapped Registers MMRs contiguous block address space, 4096 bytes deep individual addressed offset above base address base address programmable Multifunction Pins Multiplexer 100-Pin LQFP Package, pins have multiple functions Individual functions chosen each these pins software GPI/O Port bits share Multifunction with least other function Some multifunction pins "Pin Multiplexing Control Register" function select
Chapter Introduction
Typical Applications
Typical Applications
flexible architecture XA-SCC allows easily configured wide variety applications, using either IDL, NMSI (non-multiplexed serial interface), both types physical layer interface. more common applications appear below.
1.4.1
ISDN Terminal Adapter
XA-SCC
(for control)
SCC0 DMA, DRAM Controller SCC1 SCC2 Demux
Control U-Chip
SCC3
RS232 Similar
Figure
ISDN Terminal Adapter
XA-SCC well suited ISDN terminal adapter applications. typical configuration, depicted Figure 1-2, SCC3 would operated Asynchronous mode would communicate with host RS-232 similar serial interface. SCC0 SCC2 would operating Synchronous mode, attached on-chip interface, with assigned each ISDN channels. on-chip interface would used communication between physical layer interface, such U-Chip other device.
Chapter Introduction
Typical Applications
shown Figure 1-3, receive transmit data from each would moved optional circular buffers external memory dedicated channel on-chip DMA.
SCC0 SCC1 SCC2 SCC3 U-Chip
External Memory
DRAM Controller
Async
Figure
ISDN Terminal Adapter, showing channels
Chapter Introduction
Typical Applications
1.4.2
Four Independent Serial Channels
Another common application four independent serial channels, operating simultaneously, with each channel using different communication protocol desired. This configuration depicted Figure 1-4. Receive transmit data moved from optional circular buffers external memory eight dedicated channels, greatly minimizing interrupt response requirements CPU. Many applications which normally stand-alone UARTs devices streamlined chip-count, circuit board complexity, overall cost XA-SCC's integrated capabilities multi-channel, multi-protocol, high-speed serial communication options.
SCC0
SCC1 Off-Chip Memory Program Data DRAM Controller SCC2
SCC3
Figure
Four Independent Serial Channels
Chapter Introduction
Chapter
XA-SCC
XA-SCC
Timers Interrupts Autobaud DRAM Controller Interface Interface Ports Function External components such Physical I/F, U-Chip, S/T, RS-232, etc.
External components such DRAM, SRAM, Flash, ROM, Ports, etc.
V.54/2047
Contents Introduction. Timers Serial Ports (UARTs). Event Interrupts Internal Data Memory Addressing Scope. Internal Code Memory Memory Mapped Registers (MMRs) ResetOut External WAIT timing. 2.10 Special Function Register (SFR) Modifications.
Chapter XA-SCC
Introduction
Introduction
XA-SCC's on-board 80C51XA-G3 with certain modifications. Detailed information standard core available User Guide, Section 16-Bit 80C51XA Microcontrollers (eXtended Architecture) Data Handbook IC25. Detailed information XA-G3 derivative available Section same publication. This chapter primarily concerned with differences between standard XA-G3, outlined 16-bit 80C51XA Microcontrollers (eXtended Architecture) Data Handbook IC25, XA-SCC. XA-SCC differs from standard XA-G3 these general areas: Timers Serial Ports/UARTs Event Interrupts Internal Data Memory Addressing Scope Internal Code Memory Memory Mapped Registers ResetOut External WAIT timing Special Function Register
2.2.1
Timers
Timer/Counters
XA-SCC standard 16-bit enhanced Timer/Counters, Timer Timer which function identically their counterparts XA-G3. Timer XA-G3's additional 16-bit Up/Down Timer/Counter, been removed from XA-SCC. complete, detailed instructions operation Timer Timer please XA-G3 CMOS single-chip 16-bit microcontroller, Section 16-Bit 80C51XA Microcontrollers (eXtended Architecture) Data Handbook IC25.
2.2.2
Watchdog Timer
XA-SCC Watchdog Timer subsystem same that XA-G3. When Watchdog Timer underflows, causes XA-SCC internal reset. Watchdog Timer will running after type reset, will continue periodically reset chip unless either "fed" disabled user software. complete details
Chapter XA-SCC
Serial Ports (UARTs)
Watchdog Timer, please XA-G3 CMOS single-chip 16-bit microcontroller, Section 16-Bit 80C51XA Microcontrollers (eXtended Architecture) Data Handbook IC25.
Serial Ports (UARTs)
XA-G3 Serial Ports (UARTs) have been removed from XA-SCC.
Event Interrupts
There Event Interrupts implemented XA-SCC. XA-G3, only nine Event Interrupts implemented. Four XA-SCC Event Interrupts called "High Priority Software Interrupts." High Priority Software Interrupt flag bits software, rather than external hardware events. Normal XA-G3 XA-SCC Software Interrupts have fixed priorities between XA-SCC High Priority Software Interrupts assigned priority from appear Event Interrupts. details XA-SCC interrupts, please Chapter "Interrupts." complete discussion interrupts, both User Guide XA-G3 sections 16-bit 80C51XA Microcontrollers (eXtended Architecture) Data Handbook IC25.
2.5.1
Internal Data Memory Addressing Scope
Internal Data Memory
XA-SCC bytes Internal Data Memory, populating addresses 000000h-0000FFh. possible, depending Memory Interface (MIF) programmed, External Data Memory overlap this address space. that case, consider following: reads writes addresses 00h-FFh will always access External Data Memory. reads writes addresses 00h-FFh (using either Direct Addressing Indirect Addressing) will normally access Internal Data Memory. access overlapping portion External Data Memory only using form MOVX instruction. User Guide, Section 16-Bit 80C51XA Microcontrollers (eXtended Architecture) Data Handbook IC25, details.
Chapter XA-SCC
Internal Code Memory
2.5.2
Data Memory Addressing Scope
rules accessing Internal External Data Memory Segment (addresses 000000h 00FFFFh) summarized Table 2-1.
Table Access Internal External Data Memory
using Direct Addressing, accesses. Applicable External Data Memory Internal Data Memory External Data Memory Internal Data Memory External Data Memory External Data Memory always! using Indirect Addressing, accesses. using MOVX Instruction, accesses.
Data Memory access address range. 000400 00FFFF 000100 0003FF
using DMA, accesses.
000000 0000FF
Note SFRs always accessed, without reference pointer segment register, with 10-bit address encoded instructions accessing SFRs. Section 2.10 details about XA-SCC SFRs. Note Kbyte space with relocatable base address. Data Memory accesses that address space always access MMRs. Additionally, illegal base address 000000h. Section details about XA-SCC MMRs. Note accesses ignored Internal Data Memory, SFRs, MMRs. access Internal Data Memory space space will access External Data Memory.
Internal Code Memory
XA-SCC Internal Code Memory. Therefore, External Code Memory starts address 000000h. User Guide, Section 16-Bit 80C51XA Microcontrollers (eXtended Architecture) Data Handbook IC25, details.
Chapter XA-SCC
Memory Mapped Registers (MMRs)
Memory Mapped Registers (MMRs)
XA-SCC 4096 byte block On-Chip Memory Mapped Registers, whose base address relocatable under software control. Most control status registers various XA-SCC functional blocks Memory Mapped Registers. MMRs addressed their offset from base address. base address stored Special Function Registers (SFRs), MRBH MRBL. base address formed appending zero bits concatenation MRBH[7:0] with MRBL[7:4], follows:
MRBH[7:0] MRBL[7:4]
illegal base address address 000000h. XA-SCC Memory Bank configured overlap same address space MMRs, depending Memory Interface (MIF) been programmed. reads writes that address space always access MMRs, while reads writes always access external memory. avoid confusion, best configure this manner. more information XA-SCC MMRs, well MRBH MRBL, please Chapter "Memory Interface (MIF) DRAM Controller."
Chapter XA-SCC
ResetOut
ResetOut
XA-SCC ResetOut signal, which programmed appear purpose ResetOut provide active-low RESET pulse which responds internal reset. internal reset caused either Watchdog Timer underflow execution RESET instruction. Note that reset pulse arriving ResetIn does cause ResetOut pulse. However, ResetOut pulse generated under software control successively writing then P3[2]. logic shown below, Figure 2-1.
Reset
RSTSRC
RESET Instruction Watchdog Underflow Digital Shot
LOGIC
P3.2_Timer0_ResetOut P3[2] Output Latch ResetOut
Timer0
Timer0_Out Timer0_Out_Disable
P3CFGB[2] P3CFGA[2] P3[2]_DataIn Timer0_In Border XA-SCC Chip
Figure
Logic Showing Details ResetOut
shown figure, order ResetOut function drive following must true:
ResetOut function must enabled writing RSTSRC[7] RSTSRC that been added XA-SCC. Section 2.10.10 details. P3.2 (Port Bit[2]) must configured output. P3[2] Output Latch must contain one. Timer output must disabled (Timer0_Out_Disable
Chapter XA-SCC
External WAIT timing
Conversely, Reset function should disabled writing RstSrc[7] when programming output either GPI/O P3.2 Timer
2.8.1
Operation ResetOut During After Power-Up
power-up, will unknown (possibly low) state first PClk cycles, where PClk internal clock whose frequency equal half that System Clock, CClk. only with GPI/O function that behaves this manner. other GPI/O pins high, driven weak pull-up, response ResetIn. Once initial PClk cycle over (where PClk System Clock CClk ResetOut function enabled appear writing RSTSRC[7] duration subsequent ResetOut pulses will PClk cycles (8.681 µsec CClk 29.4912 MHz.). ResetOut enabled then ResetOut externally connected ResetIn this case, internal resets (Watchdog Timer RESET instruction) will assert ResetIn, will function external resets. With this configuration, reset will result RSTSRC[2:0] 001. details RSTSRC Register, Section 2.10.10.
External WAIT timing
external WAIT timing XA-SCC differs from that XA-G3. complete discussion XA-SCC external WAIT, please Section Chapter "Memory Interface (MIF) DRAM Controller."
2.10
Special Function Register (SFR) Modifications
complete discussion Special Function Registers, please User Guide, Section 16-Bit 80C51XA Microcontrollers (eXtended Architecture) Data Handbook IC25. complete list XA-G3 Special Function Registers their addresses, please XA-G3 CMOS single-chip 16-bit microcontroller, Section 16-Bit 80C51XA Microcontrollers (eXtended Architecture) Data Handbook IC25. complete list XA-SCC Special Function Registers their addresses, please Appendix "SFR Addresses."
Chapter XA-SCC
Special Function Register (SFR) Modifications
XA-SCC address space KBytes, populating addresses 400h-7FFh, constitutes separate address space from Data Memory space. accessed time without reference pointer segment. access independent segment register, SFRs always accessible with 10-bit address encoded instructions accessing SFRs. SFRs accessed Indirect Addressing. time indirection used, Data Memory accessed. address referenced indirect address, External Data Memory that address exists) accessed. Please Table 2-1. Details changes XA-SCC Special Function Register set, from that XA-G3, specified below.
2.10.1
(46Ah)
(Bus Configuration Register) comes reset containing value 00000111. This register does function described 16-bit 80C51XA Microcontrollers (eXtended Architecture) Data Handbook IC25, should never written with other value.
2.10.2
BTRH (469h)
BTRH (Bus Timing Register High Byte) comes reset containing value FFFFh. Upon XA-SCC reset, 01010001b must written this register. This register does function described 16-bit 80C51XA Microcontrollers (eXtended Architecture) Data Handbook IC25, should never written with other value.
2.10.3
BTRL (468h)
BTRL (Bus Timing Register Byte) comes reset containing value EFh. Upon XA-SCC reset, 01000000b must written this register. This register does function described 16-bit 80C51XA Microcontrollers (eXtended Architecture) Data Handbook IC25, should never written with other value. Warning! BTRH BTRL function described 16-bit 80C51XA Microcontrollers (eXtended Architecture) Data Handbook IC25, must written with values respectively. Furthermore, recommended that BTRH initialized first, then BTRL, followed least five NOPS.
2.10.4
MRBL (496h)
MRBL (Memory Mapped Registers Base Address Byte) register, which been added XA-SCC. Please Section Memory Mapped Registers (MMRs) Section 3.11 Special Function Register Descriptions.
Chapter XA-SCC
Special Function Register (SFR) Modifications
2.10.5
MRBH (497h)
MRBH (Memory Mapped Registers Base Address High Byte) register, which been added XA-SCC. Please Section Memory Mapped Registers (MMRs) Section 3.11 Special Function Register Descriptions.
2.10.6 MICFG (499h)
MICFG (Memory Interface General Configuration) register, which been added XA-SCC. Please Section 3.11 Special Function Register Descriptions.
2.10.7
IPA6 (4A6h)
IPA6 (Interrupt Priority register, which been added XA-SCC. contains Interrupt Priority fields Event Interrupts "HSWR1" "HSWR0," High Priority Software Interrupts. Please Section 10.4 High Priority Software Interrupts.
2.10.8
IPA7 (4A7h)
IPA7 (Interrupt Priority register, which been added XA-SCC. contains Interrupt Priority fields Event Interrupts "HSWR3" "HSWR2," High Priority Software Interrupts. Please Section 10.4 High Priority Software Interrupts.
2.10.9
PCON (404h)
PCON (Power Control Register), XA-G3, contains only functional bits PCON[1] PCON[0]. Setting these bits activates Power Down Idle modes, respectively. there DRAM system, activating Power Down mode setting PCON[1] will halt refresh, resulting loss data.
2.10.10
RSTSRC (463h)
RSTSRC (Reset Source) register, which been added XA-SCC. There four functional bits this register, which discussed below.
Chapter XA-SCC
Special Function Register (SFR) Modifications
RSTSRC[7] ROEN (Reset Enable)
ResetOut disabled. ResetOut enabled.
RSTSRC Bit[7] enables disables ResetOut function. details ResetOut, please Section ResetOut. RSTSRC[2:0] [R_WD R_CMD R_EXT]
Reset Watchdog Timer underflow. Reset execution RESET instruction. Reset external, ResetIn.
RSTSRC Bits[2:0] reflect cause last XA-SCC reset. After reset, these three bits will one, other bits will zero.
2.10.11
XA-G3 SFRs Which Have Been Removed From XA-SCC
S0CON, S0STAT, S0BUF, S0ADDR, S0ADEN (Serial Port removed) S1CON, S1STAT, S1BUF, S1ADDR, S1ADEN (Serial Port removed) T2CON, T2MOD, TH2, TL2, T2CAPH, T2CAPL (Timer removed)
Chapter XA-SCC
Chapter
Memory Interface (MIF) DRAM Controller
XA-SCC
Timers Interrupts Autobaud DRAM Controller Interface Interface Ports Function External components such Physical I/F, U-Chip, S/T, RS-232, etc.
External components such DRAM, SRAM, Flash, ROM, Ports, etc.
V.54/2047
Contents Introduction. Architecture Memory Banks Generic Memory Interface. DRAM Interface. DRAM Refresh WAIT Size8 Arbiter. XA-SCC Memory Mapped Register Relocation 3.10 Configuration Example. 3.11 Special Function Register Descriptions 3.12 Memory Mapped Register Descriptions
Chapter Memory Interface (MIF) DRAM Controller
Introduction
Introduction
XA-SCC Memory Interface (MIF) allows external memory devices interface directly XA-SCC using external glue logic. Five banks DRAM, banks configured Code Memory, Data Memory, both. size base address each bank individually programmable. provides automatic DRAM refresh with programmable timing, individually programmable Read/Write cycle timing each bank, support external WAIT states. Also built into Intelligent Arbiter, which arbitrates grants between eight XA-SCC channels, CPU, DRAM refresh generator. XA-SCC DRAM Controller support: Fast Page Mode DRAM, with automatic refresh. DRAMs from 256K bytes words bytes). Generic memory interface. Memory types, such SRAM, Flash, ROM, EPROM, etc. mixed. memory banks with unified code data address spaces. Individual Chip Select pins each bank eliminate need external glue logic. Dynamic sizing 16-bit wide data each bank). Programmable timing, bank-by-bank basis. Timing generator. Intelligent arbiter assigns priorities between refresh, access, access. External WAIT. Bank Bank Swap, booting from Flash, executing from RAM. Relocatable Memory Mapped Register (MMR) space.
3.2.1
Architecture
Block Diagram
following discussion relates Block Diagram, Figure 3-1. individual Chip Select (CS) each Memory Bank physically connected memory device(s) dedicated that bank, usually DRAM packages SRAM packages. Chip Select Decoder compares most significant address bits memory addresses base addresses Memory Banks (including Code space Data space qualifiers), asserts that bank which matches. Never more than most significant bits
Chapter Memory Interface (MIF) DRAM Controller
Architecture
need compared, since memory bank base addresses KByte boundaries, hence their least significant bits zero. Memory addresses from eight channels, multiplexed (selected) onto Address Bus, under control Arbiter. DRAM logical address bits a22-a0 multiplexed onto address pins A17-A6 during column phases Row/Column Address (see Table Table 3-7). Generic memory (SRAM, ROM, etc.) logical addresses, a19-a0, appear address pins A19-A0 directly. correct Read/Write cycle timing each bank, which been programmed into that bank's Timing Register (BiTMG), applied Timing Generator whenever bank selected. Optionally, External WAIT signal used extend cycle timing.
Chip Select Decoder a23-a12 Address Select a23-a0
CS5-CS0
Address bits) Address bits)
A19-A18, A5-A0
Row/Column Address Generator Request Grant Arbiter Request Grant Refresh Request DRAM Refresh Timer Control WAIT Timing Generator
A17-A6* *a22-a0 multiplexed onto pins A17-A6 during various DRAM cycles.
BLE, BHE, WAIT
Figure
Block Diagram (showing address strobe generation only)
Chapter Memory Interface (MIF) DRAM Controller
Architecture
3.2.2
Register
uses five Special Function Registers (BTRH, BTRL, MRBH, MRBL, MICFG) twenty Memory Mapped Registers (MBCL, BiCFG, BiAM, BiTMG, RFSH). index used reference Memory Banks
Warning! BTRH BTRL function described 16-bit 80C51XA Microcontrollers (eXtended Architecture) Data Handbook IC25 must written with values respectively. Also, never write register. preloaded Reset with 07h, only legal value. change this value will cause system malfunctions. Table Register
Description Comes reset configured slowest speed. Before programming other registers, 01010001b must written this SFR. Section 3.11.1 page Comes reset configured slowest speed. Before programming other registers, 01000000b must written this SFR. Section 3.11.2 page
Register BTRH (Bus Timing Register High Byte) BTRL (Bus Timing Register Byte)
Contains address bits a23-a16 base address MRBH (Memory Mapped Register Base Address High) KByte Memory Mapped Register space. Section page MRBL (Memory Mapped Register Base Address Low) MICFG (Memory Interface General Configuration) MBCL (Memory Bank Configuration Lock) BiCFG (Bank Configuration) BiAM (Bank Base Address/DRAM Address Multiplexer Control) BiTMG (Bank Timing) RFSH (Refresh Timing) Contains address bits a15-a12 base address KByte Memory Mapped Register space. Section page Contains CLKOUT Enable bit. Section 3.11.5 page Contains bits locking unlocking BiCFG Registers. Section 3.12.4 page Contains size, type, width, enable bits Memory Bank Section 3.12.1 page Contains base address bits DRAM address multiplex control bits Memory Bank Section 3.12.2 page Contains timing control bits Memory Bank Section 3.12.3 page Contains refresh time constant DRAM Refresh Timer enable bit. Section 3.12.5 page
Chapter Memory Interface (MIF) DRAM Controller
Memory Banks
Memory Banks
XA-SCC supports memory banks, Banks through provides individual Chip Select each bank (CS0 through CS5), allowing glueless interface external memory. Each memory bank independently enabled either Code memory access (Harvard Architecture Code space), Data memory access (Harvard Architecture Data space), both (Von Neuman Architecture). memory bank configured both Code Data Memory access, same address range used both. Bank 0.5) selected (CSi asserted) logical address bits a23-a12 (fewer banks larger than match that bank's base address, type access (Code Data) matches that bank's Code/Data enable qualifier. Bank sizes range from KBytes MBytes, logical address bits a11-a0 compared. memory banks assigned same address range, condition that enabled Code access only, other Data access only (Harvard Architecture). that case, only processor Code fetches (PSEN that address range will activate Code enabled memory bank. reads writes, well processor Data memory accesses (PSEN that address range will activate Data enabled memory bank. Warning! Never configure banks such that they will respond same memory access. only configuration which overlapping address ranges permitted, when bank Code only, other Data only. XA-G3 core bytes internal Data which occupy addresses 000000h 0000FFh. memory bank configured overlap this address range, with Data memory access enabled, Data reads writes using direct indirect addressing will still directed internal RAM. access overlapping portion External Data Memory only using form MOVX instruction. User Guide, Section 16-Bit 80C51XA Microcontrollers (eXtended Architecture) Data Handbook IC25, details. reads writes addresses 000000h-0000FFh will always access External Data Memory populated). Banks either DRAM Interfaces (Fast Page Mode DRAM), Generic Memory Interfaces (SRAM, ROM, EPROM, Flash, etc.). Bank only Generic Memory Interface. Burst reads supported Code Memory reads only. Burst reads supported Data Memory accesses, burst never used during Write cycles. However, both word reads word writes 8-bit will access consecutive bytes.
Chapter Memory Interface (MIF) DRAM Controller
Memory Banks
Code Memory accesses sequential addresses, with address bits a23-a4 common, made with burst reads. Burst reads cannot interrupted DRAM Refresh Request, DMA, request. longest burst bytes. hardware reset configures Bank into known state. processor, which initially executes code from Bank later configure banks needed. routine configuring initializing memory bank typically proceeds follows: Configure bank's base address (BiAM Register). Configure bank's size (BiCFG Register). Configure bank's memory interface type, Generic DRAM (BiCFG Register). Configure bank's timing parameters (BiTMG Register). Memory Banks MBytes size. Physical addressing Generic Memory limited bits (A19-A0), there many Generic Memory Banks, each MByte size. Physical addressing DRAM provides A22-A0, DRAM banks MBytes size.
3.3.1
Bank
Bank boot bank cannot configured DRAM Interface. forced hardware into Generic Memory Interface configuration. Upon hardware reset, code execution begins from Bank boot-up sequence (typically Flash ROM) must physical memory connected CS0. However, Bank supports both code data memory accesses support "Bank Bank Swapping" feature. Section 3.3.3 page Other important features Bank base address Bank hard wired 000000h. Bank minimum bank size bytes. byte smaller) memory used, entire byte address space will occupied. Bank always enabled code memory access enabled data memory access. width Bank determined during hardware reset (described below) cannot changed processor.
Chapter Memory Interface (MIF) DRAM Controller
Memory Banks
State Bank after hardware reset B0CFG interpretation these values described below. Code memory access enabled (B0CFG[7] hard wired). Data memory access disabled (B0CFG[6] write occur until this reconfigured. width determined state WAIT_Size8 (Pin immediately after rising edge ResetIn (B0CFG[5] don't care Bank WAIT_Size8 Bank width will bits. WAIT_Size8 width will bits. Section 3.7.3 details Size8 function. Bank configured Generic Memory (B0CFG[4] hard wired). Bank size MBytes with address range from 000000h 7FFFFFh (B0CFG[3:0] 1111, with B0CFG[3] hard wired). B0TMG interpretation these values described below. Write delay disabled (B0TMG[7] cycle delay from BLE/BHE (B0TMG[6] Access Time (BLE/BHE BLE/BHE high) cycles (B0TMG[5:3] 111). cycle minimum delay (Recovery Time) from high again (B0TMG[2:1] 01). BLE/BHE normal data strobes, converted WEL/WEH (B0TMG[0] After reset, Bank configured KBytes MBytes, shown Table 3-2. size address range determined 4-bit field B0CFG[3:0]. Note, however, that B0CFG[3] hard wired logic one.
Table
B0CFG[3]
Bank Size Address Range Select
B0CFG[2] B0CFG[1] B0CFG[0] Bank Size Bytes 128K Bytes 256K Bytes 512KBytes Bytes Bytes Bytes Bytes Bank Address Range 000000h 00FFFFh 000000h 01FFFFh 000000h 03FFFFh 000000h 07FFFFh 000000h 0FFFFFh 000000h 1FFFFFh 000000h 3FFFFFh 000000h 7FFFFFh
Chapter Memory Interface (MIF) DRAM Controller
Memory Banks
3.3.2
Banks
Banks through configured either Generic memory DRAM interfaces. size each bank MBytes, base address each bank programmable. Bank 1.5), size determined 4-bit field BiCFG[3:0]. size chosen Bank either 16K, Bytes, then Bank resides same segment (A23-A16) Memory Mapped Registers. this case, Bank base address formed follows:
a23-a16 MRBH[7:0] a15-a12 BiAM[7:4] a11-a8 a7-a0
size chosen Bank KBytes greater, then Bank base address formed follows:
a23-a16 BiAM[7:0] a15-a12 a11-a8 a7-a0
both cases, order bits BiAM register that less significant than bank size selected, ignored forming base address. Bank size base address formation summarized Table 3-3.
Table Banks Size Base Address Select
Logical Address BiCFG[3:0]
00xx 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 KBytes KBytes KBytes KBytes KBytes KBytes KBytes KBytes MBytes MBytes MBytes MBytes MRB23 MRB23 MRB23 MRB23 BiAM7 BiAM7 BiAM7 BiAM7 BiAM7 BiAM7 BiAM7 BiAM7 MRB22 MRB22 MRB22 MRB22 BiAM6 BiAM6 BiAM6 BiAM6 BiAM6 BiAM6 BiAM6 MRB21 MRB21 MRB21 MRB21 BiAM5 BiAM5 BiAM5 BiAM5 BiAM5 BiAM5 MRB20 MRB20 MRB20 MRB20 BiAM4 BiAM4 BiAM4 BiAM4 BiAM4 MRB19 MRB19 MRB19 MRB19 BiAM3 BiAM3 BiAM3 BiAM3
Bank Size
Reserved MRB18 MRB18 MRB18 MRB18 BiAM2 BiAM2 BiAM2
a11-a0
MRB17 MRB17 MRB17 MRB17 BiAM1 BiAM1
MRB16 BiAM7 BiAM6 BiAM5 BiAM4 MRB16 BiAM7 BiAM6 BiAM5 MRB16 BiAM7 BiAM6 MRB16 BiAM7 BiAM0
Chapter Memory Interface (MIF) DRAM Controller
Memory Banks
Note that DRAMs smaller than KBytes supported, only Generic Memory Interface banks configured sizes KBytes below. Example: Configure Bank KByte size with base address 380000h. Write 1010b B5CFG[3:0] (B5MS3-B5MS0). Chooses KByte size. Write 001110xx B5AM[7:0] (B5AM7-B5AM0). Sets base address 380000h. Notice that bits B5AM[1:0] ignored this case zeros used forming base address.
3.3.3 Bank Bank Swapping
many applications, Bank will Flash ROM-based boot code, Bank will DRAM SRAM. After boot-up, application code will written into DRAM SRAM) subsequent execution. application code executed from DRAM SRAM), with base address 000000h, DRAM SRAM) remapped Memory Bank using Bank Bank Swapping. After Bank Bank Swapping, accesses Bank address space (including Code space Data space qualifiers) will activate CS1, with Bank timing. Conversely, accesses Bank address space (including Code space Data space qualifiers) will activate CS0, with Bank timing. selection Bank still determined address range chosen Bank (B0CFG[3:0]), Code Data memory enables chosen Bank (B0CFG[7:6]). base address Bank remains 000000h. Similarly, selection Bank still determined address range chosen Bank (B1CFG[3:0]), Code Data memory enables chosen Bank (B1CFG[7:6]). base address chosen Bank remains same. Bank Bank Swapping allows interrupt vectors, which memory between 000000h 00011Bh, write accessed. also allows MByte DRAM bank based 000000h. Bank Bank Swapping only take place next time non-burst, even-byte word access occurs.
Chapter Memory Interface (MIF) DRAM Controller
Memory Banks
Example: Assume physically connected 128K ROM, connected 256K DRAM. following sequence typifies Bank Bank Swapping. reset, Bank will have address range 000000h 7FFFFFh, Bank will disabled. Unlock Configuration Locks Banks MBCL Register. Change Bank size KBytes. Configure Bank size KBytes (256K 16), Bank base address 400000h (which yields address range 400000h 47FFFFh), Bank timing required physical DRAM, enable both code data accesses Bank Configure refresh timer enable refresh. Move code DRAM Bank Change Bank size KBytes (the size ROM). Change Bank size KBytes (256K size DRAM) enable both code data accesses Bank Swap Banks (write MBCL[7]) lock Configuration Locks Banks MBCL Register. Now, address range Bank 000000h 07FFFFh (base address 000000h size KBytes), accesses Bank will redirected DRAM CS1_RAS1. address range Bank 400000h 41FFFFh (base address 400000h size KBytes), accesses Bank will redirected CS0. Code still executes from Bank (low memory), physically from DRAM CS1_RAS1. Width, Memory Type, Timing control bits physical memory attached always Bank Register set. Similarly, Width, Memory Type, Timing control bits physical memory attached always Bank Register set. Those control bits which "swap" (relate their before swap, other after swap) summarized Table case DRAM attached CS1, Table case Generic Memory attached CS1.
Chapter Memory Interface (MIF) DRAM Controller
Memory Banks
There very important items note Table 3-4: least significant bits Bank base address after swap (which will activate CS0), will always regardless values previously stored B1AM[1:0]. B1AM1 B1AM0 were relevant bits forming Bank base address before swap (see "64K Bytes" "128K Bytes" rows Table 3-3), then base address after swap could different from that which programmed. shaded Table shows that Address Multiplexer control bits DRAM connected always B1AM[1:0] B1MX1 B1MX0.
(ROM) (DRAM) Control Bits Before After Swapping
Control bits accessing physical memory connected Parameter (ROM) (DRAM) (ROM) (DRAM)
Table
Before Swapping
Code Memory Enable Data Memory Enable Size B0CFG[7] B0CFG[6] B0CFG[3:0] B0AM[7:0] hard wired 00000000 applicable B1CFG[7] B1CFG[6] B1CFG[3:0]
After Swapping
B1CFG[7] B1CFG[6] B1CFG[3:0] B0CFG[7] B0CFG[6] B0CFG[3:0] B0AM[7:0] hard wired 00000000 B1AM[1:0]
Base Address bits
B1AM[7:0]
B1AM[7:2][00]
DRAM Address Multiplexer control bits
B1AM[1:0]
applicable
Table
(ROM) (Generic) Control Bits Before After Swapping
Control bits accessing physical memory connected
Parameter
(ROM)
(Generic)
(ROM)
(Generic)
Before Swapping
Code Memory Enable Data Memory Enable Size B0CFG[7] B0CFG[6] B0CFG[3:0] B0AM[7:0] hard wired 00000000 B1CFG[7] B1CFG[6] B1CFG[3:0]
After Swapping
B1CFG[7] B1CFG[6] B1CFG[3:0] B0CFG[7] B0CFG[6] B0CFG[3:0] B0AM[7:0] hard wired 00000000
Base Address bits
B1AM[7:0]
B1AM[7:0]
Chapter Memory Interface (MIF) DRAM Controller
Generic Memory Interface
Generic Memory Interface
Each memory banks configured Generic Memory Interface, clearing BiTYP that bank's Bank Configuration Register (BiTYP BiCFG[4]). Generic Memory Interface bank used interface with external ROM, EPROM, EEPROM, Flash Memory, SRAM, most peripheral chips.
3.4.1
Generic Memory Interface Addressing
banks configured Generic Memory Interfaces, BiAM[7:0] hold values relevant forming base address bank. Sections 3.3.1 3.3.2. details. base address hard wired 000000h Bank base address given Table Banks (logical addresses a19-a0 appear address pins A19-A0).
3.4.2
Generic Memory Interface Timing
Timing Configuration Registers (BiTMG) Banks must configured before corresponding banks enabled code data accesses. Bank comes hardware reset containing value 7Ah, which sets access times their maximum, reconfigured later processor. changes timing configuration occur AFTER current access cycle over. Generic Memory Interface banks, functions BiTMG Register differ from those DRAM Interface Banks. functions both types memory banks detailed Section 3.12.3. timing examples which demonstrate bits BiTMG Register affect Generic Memory Interface Bank's read write timing, Appendix "Bus Timing Examples."
DRAM Interface
Memory Banks configured DRAM Interfaces, setting BiTYP that bank's Bank Configuration Register (BiTYP BiCFG[4]). Bank cannot configured DRAM Interface.
3.5.1
DRAM Burst Reads
Burst reads supported Code Memory accesses only. Burst reads supported Data Memory reads, burst never used during write cycles (except word write 8-bit bus).
Chapter Memory Interface (MIF) DRAM Controller
DRAM Interface
Code Memory accesses sequential addresses, with address bits a23-a4 common, made with burst reads. Burst reads cannot interrupted DRAM Refresh Request, request. longest burst bytes. Fast Page Mode (FPM) DRAM burst reads differ only regard ClkOut cycle when Data sampled (See Section 3.5.3 DRAM Interface Timing details).
DRAM DRAM data sampled rising edge ClkOut while BLE/BHE (CAS) active. data sampled next rising edge ClkOut after BLE/BHE (CAS) been negated.
3.5.2
DRAM Interface Addressing
banks configured DRAM Interfaces, bank's Address Multiplexer Control Register bits [7:2] (BiAM[7:2]) hold values relevant forming base address bank. Sections 3.3.1 3.3.2. details. base address hard wired 000000h Bank method assigning base address Banks given Table 3-3. BiAM[1:0] Row/Column Address Multiplexer Control Bits, BiMX1 BiMX0, respectively. These bits must configured specific physical DRAM used. choices BiMX1 BiMX0 based number Bytes DRAM, width used that bank. Configuration BiMX1 BiMX0 summarized Table 3-6.
Table BiMX1 BiMX0 Configuration
Number Bytes KBytes MBytes MBytes MBytes 16-Bit 256K deep (512 KBytes total) deep MBytes total) deep MBytes total) Reserved BiMX1 BiMX0 Address Scheme
Data Width 8-Bit
column address multiplexing scheme implemented during cycles DRAM access dependent states BiMX1 BiMX0, well Data Width. assignment logical addresses a23-a0 pins A17-A6 during column address phases DRAM access shown Table 3-7.
Chapter Memory Interface (MIF) DRAM Controller
DRAM Interface
Note that Address pins A23-A18 A5-A0 used during DRAM access, that denotes unused pins corresponding address phase.
Table
Address Scheme column column column column column column column Note Table determine Address Scheme [BiMX1 BiMX0] values. Note During RAS, logical address address always identical.
DRAM Column Address Multiplexing
Address
3.5.3
DRAM Interface Timing
Timing Configuration Registers (BiTMG) Banks must configured before corresponding banks enabled code data accesses. Bank comes hardware reset containing value 7Ah, which sets access times their maximum, reconfigured later processor. changes timing configuration only occur AFTER current access cycle over. Bank Bank Swapping only take place next time non-burst even-byte word access occurs. DRAM Interface banks, definitions BiTMG Register differ from those Generic Memory Interface Banks. functions both types Memory Banks detailed Section 3.12.3.
Chapter Memory Interface (MIF) DRAM Controller
DRAM Refresh
Note: DRAM Interface Banks, value used Bank's Access Time. That BiAC[5:3] BiAC2 BiAC1 BiAC0 assume only binary values through 111. timing examples which demonstrate bits BiTMG Register affect DRAM Interface Bank's read write timing, please Appendix "Bus Timing Examples."
DRAM Refresh
XA-SCC only supports before refresh. interval separating DRAM refresh cycles timed MIF's Refresh Timer. time-out interval programmed into bits [6:0] Refresh Timing Register (RFSH[6:0]), timer will time once every RFSH[6:0] system clock cycles. each Refresh Timer time out, Refresh Request sent Arbiter. Arbiter always assigns highest priority Refresh Request. However, DRAM burst accesses (Fast Page Mode Page Mode) will interrupted refresh. maximum burst bytes. Refresh Timer enabled setting RFSH[7] one. RFSH[7] cleared hardware reset, disabling Refresh Timer, that code execute from boot memory (Bank without interference from Refresh Requests. Refresh Timer must programmed enabled before first access DRAM Interface memory banks. memory banks configured DRAM Interfaces, Refresh Timer should remain disabled. DRAM refresh cannot disabled during Idle mode, there banks configured DRAM Interfaces. Power-Down mode, with clock present, refresh possible data will lost.
3.6.1
DRAM Refresh Cycle Timing
banks configured DRAM Interfaces refreshed simultaneously. duration refresh cycle determined values stored B5CBL B5AC0 B5TMG Register (B5TMG[6] B5TMG[3] respectively). Recovery Time specified values stored B5EC1 B5EC0 (B5TMG[2:1]). accesses occur until Refresh Recovery Time elapses, when Refresh Request removed.
Refresh Recovery timing always determined these bits B5TMG Register, regardless whether actually being used. there banks configured DRAM Interfaces, Bank must them. there multiple DRAM banks, Bank must slowest DRAM bank.
Chapter Memory Interface (MIF) DRAM Controller
WAIT Size8
timing diagram below (Figure 3-2) demonstrates typical DRAM Refresh cycle, which following occurs: (CASL CASH) asserted with negated. ClkOut cycle later (RASi) asserted memory banks configured DRAM Interfaces. B5CBL B5AC0 ClkOut cycles after falling edge (RASi), (RASi) /BHE (CASL/CASH) negated. two-bit field B5TMG[1:0] [BiEC1 BiEC0] determines Recovery Time Refresh Cycle. case shown ClkOut cycles Recovery Time, B5TMG[1:0] [BiEC1 BiEC0]
ClkOut (RAS) BLE/BHE (CAS)
B5CBL+B5AC0+3 Cycles
[B5EC1:B5EC0]+1 Cycles
Figure
DRAM Refresh Cycle
3.7.1
WAIT Size8
WAIT
External circuitry extend cycle memory bank pulling WAIT_Size8 (pin high. However, external WAIT states will only have effect memory banks which configured Generic Memory Interfaces. accesses memory banks configured DRAM Interfaces will affected state WAIT_Size8. When memory bank accessed, internal wait states might might generated, depending state that bank's BiTMG Register. Additional external wait states inserted holding WAIT_Size8 high, bank's BiEC1 BiEC0 BiTMG[2:1] must enable external WAIT feature. WAIT_Size8 used DTACK with 68000 type device.
Chapter Memory Interface (MIF) DRAM Controller
WAIT Size8
XA-SCC WAIT differs from XA-G3 WAIT. details XA-G3 WAIT, please XA-G3 CMOS single-chip 16-bit microcontroller, Section 16-Bit 80C51XA Microcontrollers (eXtended Architecture) Data Handbook IC25.
3.7.2
External WAIT Timing
WAIT_Size8 sampled rising edge ClkOut. WAIT_Size8 must high before rising edge ClkOut cycle that triggers assertion BLE/BHE. termination external WAIT begins rising edge ClkOut when WAIT_Size8 sampled zero. next rising edge ClkOut triggers negation strobes chip selects, cycle complete. typical Generic Memory Interface cycle with external wait states shown Figure 3-3. cycle proceeds follows: Sample WAIT_Size8 insert WAIT state. Sample WAIT_Size8 insert WAIT state. Sample WAIT_Size8 terminate cycle next rising edge ClkOut. cycle complete.
ClkOut BLE/BHE WAIT
Figure
External WAIT States
3.7.3
Size8
state WAIT_Size8 (Pin immediately after reset (when ResetIn goes high) determines data width Memory Bank boot bank. Logic selects 16-bit data bus, logic selects 8-bit. Bank width selected MUST match width boot Flash, etc.) memory being used. WAIT_Size8 will sampled during first CClk (system clock) cycles after ResetIn goes high, logic state must remain unchanged during that time. Later, external circuitry external WAIT input, described Sections 3.7.1 3.7.2 above.
Chapter Memory Interface (MIF) DRAM Controller
WAIT Size8
given application, external circuitry connected will normally designed four following scenarios: Boot bits wide, external WAIT function used. Boot bits wide, external WAIT function used. Boot bits wide, external WAIT function used. Boot bits wide, external WAIT function used.
typical circuit each these cases appears Figure 3-4.
Case Boot bits wide, WAIT function used.
ResetIn
Case Boot bits wide, WAIT function used.
ResetIn
Reset
Minimum Delay WAIT_Size8 CClks
Case Boot bits wide, WAIT function used.
ResetIn
Case Boot bits wide, WAIT function used.
ResetIn
Minimum Delay CClks
WAIT
WAIT_Size8
Minimum Delay CClks
WAIT
WAIT_Size8
Figure
Typical circuits WAIT_Size8
simplest least expensive implement more CClk delay shown cases with simple circuit. important point that logic state WAIT_Size8 (Pin must remain unchanged least CClks after rising edge ResetIn.
Chapter Memory Interface (MIF) DRAM Controller
Arbiter
Arbiter
Arbiter arbitrates grants between DRAM Refresh (assuming least memory bank configured DRAM interface), access, access. memory banks configured DRAM interfaces, refresh timer should turned writing RFSH Register. Refresh Request, request, request pending same time, Refresh Request always highest priority next access. burst access currently progress will interrupted refresh. Arbiter prioritization scheme shown following table.
Table Arbiter Priority Rankings
Prioritization Next Access Refresh (highest) (lower) (lowest) Refresh (highest) CHPO (lower) (lower still) (lowest) CHPO (highest) (lower) (lowest)
Current Access
Refresh
3.8.1
Channel High Priority Override (DMA CHPO)
When channel greater than normal need access, asserts High Priority signal Arbiter. Arbiter then gives that channel High Priority Override, that channel's priority becomes second only DRAM Refresh. channels assert their High Priority signal when there only valid byte remaining channel's Data FIFO registers. channels assert their High Priority signal when there three valid bytes waiting channel's DATA FIFO Registers.
Chapter Memory Interface (MIF) DRAM Controller
XA-SCC Memory Mapped Register Relocation
3.9.1
XA-SCC Memory Mapped Register Relocation
MRBH MRBL
Memory Mapped Registers XA-SCC located anywhere 24-bit address space, with base address space always KByte address boundary. Memory Mapped Registers addressed their offset from base address. base address XA-SCC MMRs stored Special Function Registers (SFRs), MRBH (address 497h) MRBL (address 496h). base address formed appending zero bits concatenation MRBH[7:0] with MRBL[7:4], follows: Formation Memory Mapped Register (MMR) Base Address
MRBH[7:0] MRBL[7:4]
MRBH[7:0] MRBL[7:4] compared A23-A12 from initiate accesses. cannot access MMRs. least significant MRBL called MRBE. zero MRBE disables access MMRs MRBE enables access.
reset, MRBE cleared access MMRs disabled.
3.10
Configuration Example
This example demonstrates procedure assigning, initializing, enabling, bank swapping XA-SCC following configuration (see Figure 3-5): 128K 200ns Boot attached CS0. 256K DRAM (HM514260DI Series, 70ns access time, cycle refresh) attached CS1, swapping with Bank DRAM (MT4C1M16C3, 60ns access time, 16ms 1024 cycle refresh) general purpose use, attached CS2. SRAM (20ns access time) attached CS3. frequency CClk ClkOut 29.4912 MHz. Memory Mapped Register (MMR) Space will located address range FFF000h FFFFFFh. Boot Code resides (CS0). Application code will loaded into Bank DRAM (CS1), will executed from DRAM with base address 000000h after swapping.
Chapter Memory Interface (MIF) DRAM Controller
Configuration Example
XA-SCC
A16-A0 D7-D0 128K A16-A0 D7-D0
A17-A9 D15-D0
CASL CASH A8-A0 D15-D0 CASL CASH A9-A0 D15-D0
256K DRAM (HM514260DI)
A17-A8 D15-D0
DRAM (MT4C1M16C3)
A21-A19 D15-D0
SRAM
A15-A1 D15-D0
A15-A1 D15-D0
Figure
Interconnections Configuration Example
Banks will first configured follows (initial setup, before swapping):
Bank Memory Type DRAM Size 128K 256K Address Range 000000h 01FFFFh 100000h 17FFFFh Remarks This address range activates CS0. This address range activates DRAM CS1.
Chapter Memory Interface (MIF) DRAM Controller
Configuration Example
final state MIF, after banks have been configured Bank Bank Swapping been executed, will follows:
Bank Memory Type unchanged unchanged DRAM SRAM other Generic) Size 128K 256K Address Range 100000h 11FFFFh 000000h 07FFFFh 200000h 3FFFFFh FFE000h FFEFFFh Remarks This address range activates CS0. This address range activates DRAM CS1. 60ns DRAM CS2. Less than Bytes, must same data segment MMRs. Two-cycle access time, CS3.
(unused)
DRAM
Don't care
Don't care
Refresh timing configuration.
Configuration Sequence: Execute hardware reset with WAIT_Size8 (Pin pulled high ensure logic (even though weak internal pull-up). result, Memory Bank configured 8-bit width during reset. used External WAIT input later. Program SFRs: Base Address High Byte. Write MRBH FFh.
MRBH Bits MRBH[7:0] Value(s) 11111111 Comment(s) Base Address bits a23-a16.
Base Address Byte, Enable. Write MRBL F1h.
MRBL Bits MRBL[7:4] (MRB15-MRB12) MRBL[3:1] MRBL[0] (MRBE) Value(s) 1111 Comment(s) Base address bits a15-a12. Don't care, example. Enable access.
update MICFG SFR. Leave ClkOut enabled. Unlock Configuration, Base Address, Timing Registers Banks Memory Bank Configuration Lock Register. Write MBCL 30h.
MBCL Bit(s) MBCL[7] (SWP01) MBCL[6] MBCL[5:4] MBCL[3:0] Value(s) 0000 Comment(s) swap yet. Reserved. Lock registers banks Unlock registers Banks
Chapter Memory Interface (MIF) DRAM Controller
Configuration Example
Configure Bank Bank Timing Register. Write B0TMG 28h.
B0TMG Bit(s) B0TMG[7] (B0RWT) B0TMG[6] (B0CBL) B0TMG[5:3] (B0AC2-B0AC0) B0TMG[2:1] (B0EC1-B0EC0) B0TMG[0] (B0WEX) Value(s) Comment(s) applicable ROM. BLE/BHE delay. Access Time cycles 204ns 200ns ROM. Recovery Time clock cycles, shortest possible. applicable ROM.
Bank Configuration Register. Write B0CFG 89h.
B0CFG Bit(s) B0CFG[7] (B0CE) B0CFG[6] (B0DE) B0CFG[5] (B0BW) B0CFG[4] (B0TYP) B0CFG[3:0] (B0MS3-B0MS0) Value(s) 1001 Comment(s) Hardwired Bank Code accesses always enabled. Data accesses disabled. applicable Bank Hardwired Bank Must Generic Memory Interface. Size Kbytes, from Table 3-2.
Chapter Memory Interface (MIF) DRAM Controller
Configuration Example
Configure Bank Bank Timing Register. Write B1TMG 08h.
B1TMG Bit(s) B1TMG[7] (B1RWT) B1TMG[6] (B1CBL) B1TMG[5:3] (B1AC2-B1AC0) Value(s) Comment(s) DRAM. cycle (68ns) RAS-to-CAS delay, shortest possible. cycle (68ns) delay from data strobes sampling data latching data into memory, shortest possible. Two-cycle (68ns) Recovery (RAS precharge) Time, shortest possible. BLE/BHE used CASL/CASH (not WEL/WEH).
B1TMG[2:1] (B1EC1-B1EC0) B1TMG[0] (B1WEX)
Bank Configuration Register. Write B1CFG FBh.
B1CFG Bit(s) B1CFG[7] (B1CE) B1CFG[6] (B1DE) B1CFG[5] (B1BW) B1CFG[4] (B1TYP) B1CFG[3:0] (B1MS3-B1MS0) Value(s) 1011 Comment(s) Code accesses enabled. Data accesses enabled. 16-bit width. DRAM Interface. Size Kbytes (256 Kwords), from Table 3-3.
Bank Base Address/DRAM Address Mux. Control Reg. Write B1AM 10h.
B1AM Bit(s) B1AM[7:3] B1AM[2] Value(s) 00010 Comment(s) Base address Bank 100000h. B1AM bits [7:3] a23-a19 base address. Table 3-3. When forming base address Bank with size Kbytes, hardware will a18, ignoring value this position. Table 3-3. Address multiplexing 256K DRAM. Address Scheme Table 3-6.
B1AM[1:0] (B1MX1-B1MX0)
Chapter Memory Interface (MIF) DRAM Controller
Configuration Example
Configure Bank Bank Timing Register. Write B2TMG 08h.
B2TMG Bit(s) B2TMG[7] (B2RWT) B2TMG[6] (B2CBL) B2TMG[5:3] (B2AC2-B2AC0) Value(s) Comment(s) DRAM. cycle (68ns) RAS-to-CAS delay, shortest possible. cycle (68ns) delay from data strobes sampling data latching data into memory, shortest possible. Two-cycle (68ns) Recovery (RAS precharge) Time, shortest possible. BLE/BHE used CASL/CASH (not WEL/WEH).
B2TMG[2:1] (B2EC1-B2EC0) B2TMG[0] (B2WEX)
Bank Configuration Register. Write B2CFG FDh.
B2CFG Bit(s) B2CFG[7] (B2CE) B2CFG[6] (B2DE) B2CFG[5] (B2BW) B2CFG[4] (B2TYP) B2CFG[3:0] (B2MS3-B2MS0) Value(s) 1101 Comment(s) Code accesses enabled. Data accesses enabled. 16-bit width. DRAM Interface. Size Mbytes Mwords), from Table 3-3.
Bank Base Address/DRAM Address Control Reg. Write B2AM 21h.
B2AM Bit(s) B2AM[7:5] B2AM[4:2] Value(s) Comment(s) Base address Bank 200000h. B2AM bits [7:5] a23-a21 base address. Table 3-3. When forming base address Bank with size Mbytes, hardware will zeros a20-a18, ignoring values these positions. Table 3-3. Address multiplexing DRAM. Address Scheme Table 3-6.
B2AM[1:0] (B2MX1-B2MX0)
Chapter Memory Interface (MIF) DRAM Controller
Configuration Example
Configure Bank Bank Timing Register. Write B3TMG 48h.
B3TMG Bit(s) B3TMG[7] (B3RWT) B3TMG[6] (B3CBL) B3TMG[5:3] (B3AC2-B3AC0) B3TMG[2:1] (B3EC1-B3EC0) B3TMG[0] (B3WEX) Value(s) Comment asserted same cycle BLE/BHE asserted cycle after BLE/BHE negated cycles after assertion BLE/BHE. Minimum cycle (68ns) high time. BLE/BHE used WEL/WEH.
Bank Configuration Register. Write B3CFG 64h.
B3CFG Bit(s) B3CFG[7] (B3CE) B3CFG[6] (B3DE) B3CFG[5] (B3BW) B3CFG[4] (B3TYP) B3CFG[3:0] (B3MS3-B3MS0) Value(s) 0100 Comment(s) Code accesses disabled. Data accesses enabled. 16-bit width. Generic Memory Interface. Size Kbytes Kwords), from Table 3-3.
Bank Base Address/DRAM Address Control Reg. Write B3AM E0h.
B3AM Bit(s) B3AM[7:4] Value(s) 1110 Comment Because Bank smaller than Kbytes, base address formed concatenating MRBH[7:0]B3AM[7:4][0h][00h] FFE000h. Section 3.3.2 page used.
B3AM[3:0]
0000
Banks will enabled. However, refresh timing configuration needs programmed Bank (B5TMG). Bank timing must configured same slowest DRAM Bank, which Bank configure B5TMG same B1TMG. Bank Timing Register. Write B5TMG 08h.
B5TMG Bit(s) B5TMG[7] (B5RWT) B5TMG[6] (B5CBL) B5TMG[5:3] (B5AC2-B5AC0) Value(s) Comment(s) DRAM. cycle (68ns) RAS-to-CAS delay, shortest possible. cycles (68ns) delay from data strobes sampling data latching data into memory, shortest possible. Two-cycle (68ns) Recovery (RAS precharge) Time, shortest possible. BLE/BHE used CASL/CASH (not WEL/WEH).
B5TMG[2:1] (B5EC1-B5EC0) B5TMG[0] (B5WEX)
Chapter Memory Interface (MIF) DRAM Controller
Configuration Example
Configure Refresh Timing Register. DRAMs have same refresh cycle timing requirement (8ms/512 16ms/1024 15.625 µs). they were different, would have choose shortest cycle. that case, DRAM Banks would refreshed rate required bank which needs refresh most often. this case, 15.625 460.8 ClkOut cycles 29.4912 MHz. Therefore, refresh timer should time rate equal faster than 460.8 ClkOut cycles, must choose multiple Since largest multiple less than 460.8, RFSH[6:0] (decimal). Refresh Timing Register. Write RFSH B9h.
RFSH Bit(s) RFSH[7] (RFEN) RFSH[6:0] (RFTM6-RFTM0) Value(s) 0111001 Comment(s) Refresh enabled. 0111001 (decimal).
Download application program, other data, DRAM Bank ready execute Bank Bank Swapping. Change size Bank Kbytes (the physical size ROM), change size Bank Kbytes (the physical size DRAM). Enable Data Memory Access Bank (which will DRAM CS1). Bank Configuration Register. Write B1CFG F9h.
B1CFG Bit(s) B1CFG[7] (B1CE) B1CFG[6] (B1DE) B1CFG[5] (B1BW) B1CFG[4] (B1TYP) B1CFG[3:0] (B1MS3-B1MS0) Value(s) 1001 Comment(s) Code accesses enabled, same before. Data accesses enabled, same before. 16-bit width. DRAM Interface. Size 128K Bytes, from Table 3-3. Address range 100000h 11FFFFh redirected CS0.
Bank Configuration Register. Write B0CFG CBh.
B0CFG Bit(s) B0CFG[7] (B0CE) B0CFG[6] (B0DE) B0CFG[5] (B0BW) B0CFG[4] (B0TYP) B0CFG[3:0] (B0MS3-B0MS0) Value 1011 Comment Hardwired Bank Code accesses always enabled. Data accesses enabled. applicable Bank Hardwired Bank Must Generic Memory Interface. Size 512K Bytes, from Table 3-2. Address range 000000h 07FFFFh redirected DRAM CS1.
Chapter Memory Interface (MIF) DRAM Controller
Special Function Register Descriptions
Execute Bank Bank Swap, while simultaneously locking Memory Bank Configuration, Base Address, Timing Registers. Memory Bank Configuration Lock Register. Write MBCL BFh.
MBCL Bit(s) MBCL[7] (SWP01) MBCL[6] MBCL[5:4] MBCL[3:0] Value(s) 1111 Comment(s) Swap Banks Reserved. Lock registers banks Lock registers Banks
Banks will swap immediately (the next time non-burst even-byte word access occurs) after SWP01 set. Memory accesses Bank address space (including Code Data enable qualifiers Bank will redirected DRAM CS1, using DRAM's timing configured Bank Timing Register. Memory accesses Bank address space (including Code Data enable qualifiers Bank will redirected CS0, using ROM's timing configured Bank Timing Register.
3.11
3.11.1
Special Function Register Descriptions
BTRH: Timing Register High Byte (SFR 469h)
BTRH (Bus Timing Register High Byte) comes reset containing value FFFFh. Before programming other registers, 01010001b must written this register. This register does function described 16-bit 80C51XA Microcontrollers (eXtended Architecture) Data Handbook IC25, should never written with other value.
3.11.2
BTRL: Timing Register Byte (SFR 468h)
BTRL (Bus Timing Register Byte) comes reset containing value EFh. Before programming other registers, 01000000b must written this register. This register does function described 16-bit 80C51XA Microcontrollers (eXtended Architecture) Data Handbook IC25, should never written with other value.
Warning! BTRH BTRL function described 16-bit 80C51XA Microcontrollers (eXtended Architecture) Data Handbook IC25, must written with values respectively. Furthermore, recommended that BTRH initialized first, then BTRL,
followed least five NOPS.
Chapter Memory Interface (MIF) DRAM Controller
Special Function Register Descriptions
3.11.3
MRBH: Base Address High Byte (SFR 497h)
MRB23 MRB22 MRB21 MRB20 MRB18 MRB18 MRB17 MRB16
MRBH contains high order byte base address: Address bits A23-A16. register resets 0Fh.
3.11.4
MRBL: Base Address Byte (SFR 496h)
MRB15 MRB14 MRB13 MRB12 MRBE
MRBL contains lowest bits base address: Address bits A15-A12. Bit[0] MRBL called MRBE. zero MRBE disables access MMRs MRBE enables access. reset, MRBE cleared access MMRs disabled. MRBL register resets F0h. base address formed follows:
MRBH[7:0] MRBL[7:4]
MRBH[7:0] MRBL[7:4] compared a23-a12 from initiate accesses. cannot access MMRs.
3.11.5
MICFG: Memory Interface Configuration (SFR 499h)
CLKOE
MICFG[0] CLKOE (ClkOut Enable)
ClkOut disabled. ClkOut enabled.
MICFG Register contains only functional bit, which called CLKOE (ClkOut Enable). In-Circuit Emulator being used, ClkOut must remain enabled, emulators this clock. reset value CLKOE ClkOut enabled.
Chapter Memory Interface (MIF) DRAM Controller
Memory Mapped Register Descriptions
3.12
3.12.1
Memory Mapped Register Descriptions
BiCFG: Bank Configuration
BiCE BiDE BiBW BiTYP BiMS3 BiMS2 BiMS1 BiMS0
BiCFG[7] BiCE (Bank Code Memory Enable)
Code Memory access disabled. Code Memory access enabled.
This determines whether corresponding Memory Bank enabled Code Memory access (code space, read enabled). This hard wired Bank resets zero Banks BiCFG[6] BiDE (Bank Data Memory Enable)
Data memory access disabled. Data memory access enabled.
This determines whether corresponding Memory Bank enabled Data Memory access (data space, write enabled). This resets zero Banks BiCFG[5] BiBW (Bank Width)
8-bit data bus. 16-bit data bus.
This determines data width corresponding Memory Bank. This effect Bank whose data width determined state immediately after rising edge ResetIn. This resets zero Banks
Chapter Memory Interface (MIF) DRAM Controller
Memory Mapped Register Descriptions
BiCFG[4] BiTYP (Bank Type)
Generic Memory Interface. DRAM Interface.
This determines whether corresponding Memory Bank configured Generic Memory Interface, DRAM Interface. This hard wired zero Bank resets zero Banks
Chapter Memory Interface (MIF) DRAM Controller
Memory Mapped Register Descriptions
BiCFG[3:0] BiMS3 BiMS2 BiMS1 BiMS0 (Bank Memory Size) This four-bit field determines size Memory Bank Banks shown tables below. Note that B0CFG[3] hard wired `1', Bank must Kbytes greater.
B0CFG[3:0] 1000 1001 1010 1011 1100 1101 1110 1111 Bank Size Bytes 128K Bytes 256K Bytes 512KBytes Bytes Bytes Bytes Bytes
BiCFG[3:0] 00xx 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111
Banks Size Reserved Bytes Bytes Bytes Bytes Bytes 128K Bytes 256K Bytes 512KBytes Bytes Bytes Bytes Bytes
Chapter Memory Interface (MIF) DRAM Controller
Memory Mapped Register Descriptions
3.12.2
BiAM: Bank Base Address/DRAM Address Multiplexer Control
BiAM7 BiAM6 BiAM5 BiAM4 BiAM3 BiAM2 BiAM1 BiAM0
BiAM[7:0] These bits have different functions depending memory interface type memory size. Generic Memory Interface size Bytes larger BiAM7 BiAM0 form most significant byte (a23-a16) base address memory bank. this case, Bank base address formed follows:
a23-a16 MRBH[7:0] a15-a12 BiAM[7:4] a11-a8 a7-a0
Generic Memory Interface size Bytes smaller BiAM7 BiAM4 used address bits a15-a12 base address memory bank. this case, Bank resides same segment (A23-A16) Memory Mapped Registers, Bank base address formed follows:
a23-a16 BiAM[7:0] a15-a12 a11-a8 a7-a0
DRAM Interface BiAM7 BiAM2 used address bits a23-a18 base address memory bank. BiAM1 BiAM0 row/column address multiplexer control bits BiMX1 BiMX0 (see Section 3.5.2. details).
3.12.3
BiTMG: Bank Timing
BiAC2
BiAC1
BiAC0
BiWEX
BiRWT BiCBL
2-cycle (not minimum Recovery Time 2-cycle minimum Recovery Time 3-cycle minimum Recovery Time 4-cycle minimum Recovery Time
Please refer timing examples Appendix "Bus Timing Examples," reference following descriptions.
Chapter Memory Interface (MIF) DRAM Controller
Memory Mapped Register Descriptions
BiTMG[7] BiRWT (Bank Read/Write Timing) DRAM Interface Banks Fast Page Mode DRAM
Selects (Fast Page Mode) DRAM Selects DRAM
DRAM Interface Banks, BiRWT then DRAM selected, Data sampled (for Read) clock cycle before BLE/BHE (CASL/CASH) high (see Figure B-22). BiRWT then DRAM selected, Read data sampled clock cycle after BLE/BHE (CASL/CASH) high, except last Read Burst (see Figure B-26). Generic Memory Interface Banks delay.
delay clock cycle delay
Generic memory interface banks, BiRWT then signal (and BLE/ they have been converted WEL/WEH setting BiWEX asserted same clock cycle (see Figure B-5). BiRWT then signal (and BLE/BHE they have been converted WEL/WEH) asserted clock cycle after (see Figure B-9). BiTMG[6] BiCBL (Bank BLE/BHE delay) DRAM Interface Banks delay
clock cycle delay clock cycle delay
DRAM Interface Banks, BiCBL then BLE/BHE (CASL/CASH) asserted clock cycles after (RASi). BiCBL then BLE/BHE (CASL/CASH) asserted clock cycles after (CSi) RASi. Generic Memory Interface Banks delay
delay clock cycle delay
Generic memory interface banks, BiCBL then BLE/BHE asserted same clock cycle CSi. BiCBL then BLE/BHE asserted clock cycle after CSi.
Chapter Memory Interface (MIF) DRAM Controller
Memory Mapped Register Descriptions
BiTMG[5:3] BiAC2 BiAC1 BiAC0 (Bank BLE/BHE Access Time)
clock cycle (Don't use) clock cycles clock cycles clock cycles clock cycles clock cycles clock cycles clock cycles
code written this three-bit field specifies duration interval from assertion data strobes (BLE/BHE) latching data into memory (Write), sampling Data (Read). duration interval will number clock cycles specified binary number these three bits, plus one. Figure Figure effects Access Time Generic Memory, Figure B-24 Figure B-28 effects DRAM. Code reserved DRAM Interface banks therefore should never used. BiTMG[2:1] BiEC1 BiEC0 (Bank Recovery Time)
(sic) clock cycles (enables WAIT input generic accesses) clock cycles clock cycles clock cycles
DRAM interface banks. code written this field specifies shortest allowable interval that elapse between rising edge RASi (CSi) read write cycle, next falling edge RASi (CSi) beginning next read write cycle. Generic memory interface banks. code written this field specifies shortest allowable interval that elapse between rising edge read write cycle) next falling edge beginning next read write cycle).
Chapter Memory Interface (MIF) DRAM Controller
Memory Mapped Register Descriptions
BiTMG[0] BiWEX (Bank BLE/BHE Conversion WEL/WEH) DRAM Interface Banks DRAM Interface banks, BiTMG[0] reserved must remain Generic Memory Interface Banks Generic memory interface banks, BiWEX then normal data strobes. BiWEX then (externally) converted WEL, (externally) converted WEH. this case, will only active during writes, this bank (see Figure B-15).
3.12.4
MBCL: Memory Bank Configuration Lock
SWP01 Rsvd MBCL5 MBCL4 MBCL3 MBCL2 MBCL1 MBCL0
MBCL[7] SWP01 (Swap Banks
Disable Bank Bank Swapping Enable Bank Bank Swapping
This resets MBCL[6] Reserved MBCL[5] MBCL5 (Memory Bank Configuration Lock)
Memory Bank Configuration, Base Address, Timing Registers (B5CFG, B5AM, B5TMG) unlocked, changed writing these registers. Memory Bank Configuration, Base Address, Timing Registers (B5CFG, B5AM, B5TMG) locked. Writing these registers will have effect when locked.
This resets MBCL[4] MBCL4 (Memory Bank Configuration Lock) Same MBCL[5], Memory Bank MBCL[3] MBCL3 (Memory Bank Configuration Lock) Same MBCL[5], Memory Bank
Chapter Memory Interface (MIF) DRAM Controller
Memory Mapped Register Descriptions
MBCL[2] MBCL2 (Memory Bank Configuration Lock) Same MBCL[5], Memory Bank MBCL[1] MBCL1 (Memory Bank Configuration Lock) Same MBCL[5], Memory Bank MBCL[0] MBCL0 (Memory Bank Configuration Lock) Same MBCL[5], Memory Bank
3.12.5
RFSH: Refresh Timing
RFEN RFTM6 RFTM5 RFTM4 RFTM3 RFTM2 RFTM1 RFTM0
RFSH[7] RFEN (Refresh Enable)
Disable Refresh Timer Enable Refresh Timer
This resets zero. RFSH[6:0] RFTM6 through RFTM0 seven-bit time constant Refresh Timer stored this field. timer will time once every RFSH[6:0] system clock cycles. each Refresh Timer time out, Refresh Request sent Arbiter. These bits reset zero.
Chapter Memory Interface (MIF) DRAM Controller
Memory Mapped Register Descriptions
Chapter Memory Interface (MIF) DRAM Controller
Chapter
Direct Memory Access (DMA) Controller
XA-SCC
Timers Interrupts Autobaud DRAM Controller Interface Interface Ports Function External components such Physical I/F, U-Chip, S/T, RS-232, etc.
External components such DRAM, SRAM, Flash, ROM, Ports, etc.
V.54/2047
Contents Introduction. Channel Architecture. Data Buffer Management Main Memory. Serial Transmit Transfer Process DMA) Serial Receive Transfer Process DMA) Interrupts Register Descriptions
Chapter Direct Memory Access (DMA) Controller
Introduction
Introduction
XA-SCC Controller been designed efficiently implement circular buffering main memory. There eight channels; channel dedicated each Receive (Rx) channel, channel dedicated each Transmit (Tx) channel. detailed operation Transmit Receive will covered separate sections.
Channel Architecture
addition 16-bit Global Interrupt Register (which shared eight channels), each channel seven control registers four-byte Data FIFO. four channels have additional register, Char Time Register. registers accessed Memory Mapped Register (MMR) space. These registers, shown Figure 4-1, summarized below.
Table
Register Global Interrupt Register (not shown Figure 4-1) Control Register Segment Register Buffer Base Register Buffer Bound Register Address Pointer Register
Registers
Description interrupt flags this register. Contains master mode select interrupt enable bits channel. Holds A23-A16 (the current segment) 24-bit data buffer address. Holds A15-A8 address lowest byte circular buffer. Points first out-of-bounds address above circular buffer. Points single byte word data buffer memory. 24-bit address formed concatenating contents Segment Register [A23-A16] with contents Address Pointer Register [A15-A0]. Holds initial number bytes transferred. Holds queuing order full/empty status Data FIFO Registers. four-byte data FIFO buffer internal channel. Holds initial value 8-bit character timeout countdown timer which generate interrupt.
Byte Count Register FIFO Control Status Register Data FIFO Registers Char Time Register (RxCTOR, only)
Chapter Direct Memory Access (DMA) Controller
Data Buffer Management Main Memory
Data FIFO Data FIFO
Data FIFO Data FIFO
From Channel
Control Segment Buffer Base Buffer Bound Address Pointer Byte Count FIFO Control Status
RxCTOR
Channel
From
Data FIFO Data FIFO
Data FIFO Data FIFO
Channel
Control Segment Buffer Base
Figure
Register
Data Buffer Management Main Memory
Each eight channels programmed portion main memory circular buffer. Although circular buffers mandatory, relaxation processor interrupt service requirements that results from their makes them preferable most applications. Once initialized, operation channel circular buffer requires further allocation/de-allocation memory processor. segment memory Byte address space which begins Byte boundary. There segments XA-SCC Byte address space. These segments pointed 8-bit Segment Registers, which provide A23-A16 24-bit memory address.
Chapter Direct Memory Access (DMA) Controller
Data Buffer Management Main Memory
4.3.1
Circular Buffers
Circular Buffers enabled setting Wrap (DMA Control Register [2]) one.
channel circular buffer occupy little byte memory, occupy 65,536 (64K) contiguous bytes. circular buffer must reside entirely within single segment memory; thus cannot cross segment boundary. circular buffers start 256-byte boundaries, with order byte base address forced hardware.
each channel, circular buffer bounded bottom contents Buffer Base Register, which points lowest byte address circular buffer. Buffer Bound Register determines upper bound circular buffer. contains highest byte address
FFFFFF
1AC000
24-bit even byte address, points first out-of-bounds location
Segment Register Circular Buffer 24-bit even byte address, points first data location buffer
Buffer Bound Register
1A8000
Segment Register 000000
Buffer Base Register
Figure
Circular Buffer
Circular Buffer Operation Data transferred from main memory address determined concatenation [Segment Register][Address Pointer Register]. After transfer, Address Pointer Register incremented byte transfer only) word transfer Tx).
Chapter Direct Memory Access (DMA) Controller
Serial Transmit Transfer Process DMA)
value Address Pointer Register equal value Buffer Bound Register, highest byte circular buffer just been used. this case, Address Pointer Register reloaded with concatenation [Buffer Base Register][00h] points bottom circular buffer. Memory access proceeds address given concatenation [Segment Register][Address Pointer Register]. Example: maintain 16,384 byte (16K) circular buffer data segment hex, based hex, Wrap Bit, load Segment, Buffer Base, Buffer Bound Registers shown:
Register Control (Wrap Bit) Segment Register Buffer Bound Register Buffer Base Register Contents C000h
circular buffer occupies Kbytes from (inclusive). Note that Buffer Bound Register points highest byte address (i.e., BFFF C000), that when Address Pointer Register increments from BFFFh C000h will reloaded hardware) with 8000h.
4.3.2
Linear Buffers
channels also configured access main memory typical, linear manner. this case, maintenance linear buffer must overseen processor. Linear Buffers enabled clearing Wrap (DMA Control Register [2]) zero.
some reason channel portion main memory linear buffer, care must taken that channel never tries access memory across segment boundary. When Address Pointer Register rolls over from FFFFh 0000h Segment Register does automatically incremented. Therefore, next memory access that channel will occur 0000h same segment. details main memory data structures various modes will covered Sections 4.5.
Serial Transmit Transfer Process DMA)
This section describes operation typical Transmit channel synchronous operation. various transmit modes their required data structures main memory, well interrupts, will described following sub-sections.
Chapter Direct Memory Access (DMA) Controller
Serial Transmit Transfer Process DMA)
4.4.1
General Principles
block data byte more) memory transmitted referred fragment. fragments begin even address. fragment have even number bytes. byte count stored memory with fragment Chaining mode), written into Byte Count Register (Stop Periodic Interrupt modes). SDLC/HDLC Packet being sent, consist more fragments. channels always fetch bytes time from even address main memory. byte count specified, last byte fragment byte, which will discarded controller, passed along SCC. processor must initialize control registers channel corresponding channel before channel turned channel's Segment Register Address Pointer Register must loaded with address beginning fragment. When channel stops later restarted, contents these registers remains unchanged. When channel proceeds follows: channel fetches bytes from memory, transfers them Data FIFO registers, increments Address Pointer Register Chaining mode, first bytes used Byte Count). When channel's shift register becomes empty, reloaded with current byte channel's Data Buffer (WR8), channel signals channel that buffer empty. channel then transfers next byte FIFO queue, internal 8-bit wide bus, channel's WR8. After transfer, channel's Byte Counter decremented. When Byte Counter reaches zero, action taken channel depends which three distinct transmit modes channel operating Chaining -Non-SDLC/HDLC Chaining -SDLC/HDLC Chaining Stop (Terminal Count) Periodic Interrupt
following table summarizes byte count source, interrupt generated each modes. Details operation each these modes presented following sub-sections:
Chapter Direct Memory Access (DMA) Controller
Serial Transmit Transfer Process DMA)
Table
Modes
Mode Byte Count Source Header memory Header memory Processor loads Byte Count Register (for each fragment) Processor loads Byte Count Register (only once) packet (not fragment) Byte count completed stops) Each time byte count completed continues) Interrupt Generated
Non-SDLC/HDLC Chaining SDLC/HDLC Chaining Stop Periodic Interrupt
4.4.2 Chaining
Chaining provides high throughput allowing multiple fragments (and packets using SDLC/HDLC mode) sent without direct processor intervention. Chaining operates slightly differently non-SDLC/HDLC operation than does SDLC/ HDLC operation, they will presented separately.
4.4.3
Non-SDLC/HDLC Chaining
non-SDLC/HDLC Chaining Mode Fragment Format Memory shown Figure 4-3. Chaining mode non-SDLC/HDLC operation proceeds follows: channel programmed non-SDLC/HDLC operation; either Asynchronous mode, non-SDLC/HDLC synchronous modes. 24-bit (even) address first byte first packet written processor into channel's Segment Register [A23-A16] Address Pointer Register [A15-A0]. channel into Chaining Mode writing into bits [1:0] Control Register. first bytes (the byte count) pointed memory Address Pointer Register fetched loaded into Byte Count Register Byte Counter, Address Pointer Register incremented actual byte count 15-bit number, represented bits [14:0]. [15] called LastFrag bit. Bytes transferred SCC, Byte Counter decremented, normal manner. When Byte Counter decrements zero, channel continues pass data SCC, needed, until DMA's Data FIFO empty. When FIFO empty, channel's Interrupt, enabled, sent processor.
Chapter Direct Memory Access (DMA) Controller
Serial Transmit Transfer Process DMA)
channel fetches next bytes, pointed Address Pointer Register, from memory. These constitute byte count next fragment. Based value byte count LastFrag Bit, channel take following three courses action: byte count greater than zero, loaded into Byte Count Register Byte Counter, transmission fragment begins. byte count equals zero LastFrag equals zero, channel stops (bits [1:0] Control Register cleared hardware). byte count equals zero LastFrag equals one, byte count fetched from memory repeatedly. This process continues until either non-zero byte count fetched, software disables channel. non-zero byte count fetched, loaded into Byte Count Register Byte Counter, transmission fragment begins.
non-SDLC/HDLC Chaining, channel generates interrupt each fragment.
Byte Address
Even Byte Address
etc. Data Byte Data Byte (Pad Byte) Ascending Address Data Byte
Data Byte Data Byte
etc. Byte Count, Fragment Data, Fragment
Data Byte Data Byte Data, Fragment Data Byte Byte Count, Fragment Byte Count, Fragment
Figure
Non-SDLC/HDLC Chaining packet format memory
Chapter Direct Memory Access (DMA) Controller
Serial Transmit Transfer Process DMA)
possible actions taken channel when Byte Counter reaches zero, based value byte count LastFrag Bit, summarized Table 4-3.
Table Byte Count LastFrag Options, non-SDLC/HDLC Chaining
LastFrag equals. .and byte count greater than zero.
When FIFO empty, generate Interrupt start sending next Fragment using byte count.
When FIFO empty, generate Interrupt start sending next Fragment using byte count. When FIFO empty, generate Interrupt repeatedly fetch byte count until either non-zero byte count disabled.
.and byte When FIFO empty, generate count equals zero. Interrupt stops.
4.4.4
SDLC/HDLC Chaining
Packet format memory SDLC/HDLC Chaining operation shown Figure 4-4. SDLC/HDLC Chaining sequence shown graphically flow-chart Figure 4-5, proceeds follows: channel programmed SDLC/HDLC operation (see Chapter "Serial Communications Controller (SCC)," details). 24-bit (even) address first byte first packet written processor into channel's Segment Register [A23-A16] Address Pointer Register [A15-A0]. channel into Chaining Mode writing into bits [1:0] Control Register. first bytes (the byte count) pointed memory Address Pointer Register fetched loaded into Byte Count Register Byte Counter, Address Pointer Register incremented actual SDLC/HDLC byte count 15-bit number, represented bits [14:0]. [15] byte count Last Fragment indicator (LastFrag). [15] signifies Last Fragment current Packet. Conversely, [15] signifies Last Fragment. Bytes transferred SCC, Byte Counter decremented, normal manner. When Byte Counter decrements zero, channel continues pass data SCC, needed, until DMA's Data FIFO empty.
Chapter Direct Memory Access (DMA) Controller
Serial Transmit Transfer Process DMA)
channel fetches next bytes, pointed Address Pointer Register, from memory. These constitute byte count next fragment. Based value LastFrag byte count, channel take following four courses action: LastFrag byte count greater than zero, then loaded into Byte Count Register Byte Counter, Address Pointer Register incremented transmission fragment begins normal manner. LastFrag byte count equals zero, then Underrun beginning occur. That channel's Data Buffer empty, needs another Fragment, next Fragment available main memory. There time period equal serial Byte times (one Byte SCC's Shift Register, SCC's Data Buffer) before Underrun occurs. channel repeatedly fetches next byte count (note long delay before byte count fetched again), waiting become non-zero. non-zero byte count occurs before Underrun (before channel shift register empty), loaded into Byte Count Register Byte Counter, transmission fragment begins normal manner. LastFrag Underrun occurs before non-zero byte count, channel sends Abort
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