Application Note: Internet Reconfigurable Logic Architecting Syst

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Application Note: Internet Reconfigurable Logic Architecting Syst

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Application Note: Internet Reconfigurable Logic
Architecting Systems Upgradability with (Internet Reconfigurable Logic)
XAPP412 (v1.0) June 2001
Summary
Internet Reconfigurable Logic (IRLTM) system design methodology enable remote upgrade hardware, while insuring reliability upgrade. FPGAs, which "Field Programmable" inherently capable changing their functionality with bitstream. takes advantage this capability delivering bitstreams software drivers remote hardware. This application note will describe basic concepts IRL-enabled system, detail design considerations building system give high level description PAVE Framework, Xilinx development framework that enables embedded systems upgraded.
Introduction
advent Xilinx FPGAs, Flash Memory devices ubiquitous networks provide means store bitstreams then upgrade them once hardware been shipped final customer. Architecting your system will allow upgrade software, drivers, firmware, hardware remotely. Reasons enabling your system field upgradability include: Interoperability Products frequently have interoperate with other vendor's products, there reasonable test possible interactions prior shipping product. system IRL-enabled, interoperability issues resolved minimal cost. Time Market hardware shipped sooner with subset full functionality. Features that would have taken long prior initial release added after shipment. Design Corrections event flaw product appears after ships final customer, corrected without need returns, recalls, field service, accompanying customer dissatisfaction Performance Upgrades performance system upgraded engineering team time tune algorithms data paths.
Concepts
What IRL?
Internet Reconfigurable Logic system design methodology that enables modification upgrading hardware software target system across network without need service technician user directly perform change. This methodology, when applied design process, creates products that IRL-enabled. enable upgrades multiple systems simultaneously, ability back previous configuration necessary. typical IRL-enabled system might include 32-bit processor based design with TCP/IP networking connectivity. industry standard example this Single Board Computer (SBC), typically seen CompactPCI implementations. Real Time Operating System (RTOS) such WindRiver® Systems' VxWorks® Xilinx PAVE (PLD VxWorks Embedded) Framework
2001 Xilinx, Inc. rights reserved. Xilinx trademarks, registered trademarks, patents, disclaimers listed other trademarks registered trademarks property their respective owners. specifications subject change without notice.
XAPP412 (v1.0) June 2001
www.xilinx.com 1-800-255-7778
Architecting Systems Upgradability with (Internet Reconfigurable Logic) When upgrade available, would sent target, where PAVE would perform upgrade. example, system, when IRL-enabled, might able autonomously upgrade itself recover from power failure during this upgrade.
Elements system
Creating IRL-enabled system requires certain hardware infrastructure components that will allow remote modifications occur. shown Figure below, there several elements System.
TCP/IP Network
Payload
Host
Upgrade Portal
Target
XAPP412_01_041701
Figure Block Diagram Internet Reconfigurable Logic System
Host where hardware/software design environment resides where FPGA bitstreams application software created. This would include Xilinx design tools, RTOS build environment (such WindRiver Systems' Tornado®) where your software applications developed, PAVE System Integration Framework (SIF), which ties these efforts together. Once upgrade created, assembled into Payload that sent system upgraded. PAVE Framework includes utilities that allow generation payload build environment Host. Upgrade Portal computer your Target communicates with obtain payload. This could reside your domain, your customers could operate Network shown Figure TCP/IP based network: Intranet, local network, Virtual Private Network (VPN) even public Internet. type network used will depend security requirements connectivity available location final product. PAVE perform basic TCP/IP socket connection; additional protocols security other purposes would need added developer. Target system system that needs hardware and/or software upgrade. This product shipped your customers which resides remotely. This IRL-enabled target system will, minimum, have processor running user's application, PAVE (part PAVE Framework), RTOS runtime client (such WindRiver Systems' VxWorks), FPGA. processor handles communication with network connectivity FPGA. PAVE called perform upgrade user embedded application. typical payload structure shown Figure Since changes hardware usually imply software drivers, these included payload structure, drivers upgraded concurrently with hardware. applications that target upgraded well.
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XAPP412 (v1.0) June 2001
Architecting Systems Upgradability with (Internet Reconfigurable Logic)
Header
Bitstream Target Device Device Driver Target Device Bitstream Target Device Device Driver Target Device Bitstream Target Device Device Driver Target Device
X412_02_041701
Figure Payload Diagram
Expanding block diagram Figure system field could look similar Figure Here have target processor, system peripheral bus, FPGA(s). processor running user's application, PAVE API, WindRiver RTOS. Upgrade portal running PAVE client that communicates with PAVE Server running target. payload passes from host target, upgrade portal Internet. Once arrives target, PAVE Server perform required functions upgrade system.
Host
Payload Host
Target Computer
Target FPGA(s)
Processor
Virtex
TCP/IP Network
PAVE
System/Peripheral Upgrade Portal Payload developed Hardware/Software Design Environment
Processor receives validates payload prior FPGA reconfiguration.
Reconfigurable logic resides here.
Target System
XAPP412_03_041701
Figure Fielded System
XAPP412 (v1.0) June 2001
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Architecting Systems Upgradability with (Internet Reconfigurable Logic)
Host, Upgrade Portal, Network Concepts
beginning upgrade process creation FPGA designs accompanying software drivers, followed testing appropriate environment. Once upgrade ready sent field, developer uses utilities supplied with PAVE create payload. After payload been assembled, developer would publish Upgrade portal, similar files published internet delivery. Once payload been published upgrade portal, there main means deliver payload target system. Push (see Figure similar broadcasting; payloads sent upgrade portal each target system. This allows Upgrade portal control upgrade process ensure systems have been upgraded. Pull (see Figure similar FTP; target system contacts upgrade portal upgrades available. payload pulled portal target.
Network
Upgrade Portal
Target
XAPP412_04_041701
Figure Pushing payload target
Network
Response
Upgrade Portal
Request
Target
XAPP412_05_041701
Figure Pulling payload from upgrade portal
Careful consideration using push pull should done ensure that upgrades interfere with user's operation system. operator high-availability system, such telecommunication services, might upgrade portal; this case push would offer complete control over process. user low-cost consumer product would have control upgrade portal. This user might prefer have option upgrading not; this case pull would best choice. upgrades free, upgrade portal need authenticate user ensure upgrade purchased.
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XAPP412 (v1.0) June 2001
Architecting Systems Upgradability with (Internet Reconfigurable Logic)
Target Software Concepts
Figure model software stack that runs target. highest level user applications. Running concurrently with application PAVE server that caches payload, then performs upgrade. second level, PAVE provides system calls customer applications perform reconfiguration process. customer applications both interface directly with RTOS. third level WindRiver RTOS. VxWorks run-time component Tornado embedded development platform acts operating system "kernel" your target system. PAVE works directly with VxWorks RTOS. Board Support Package (BSP) level four stack required interface desired processor RTOS. Each different running RTOS will need Board Support Package abstract processor from RTOS. used must match RTOS embedded processor combination used your system. PAVE assumes existence BSP.
Application
PAVE Device
VxWorks RTOS
VxWorks RTOS (Hardware Abstraction Layer) Processor
X412_06_041701
Figure Target software stack
Target Hardware concepts
Processor Coupling embedded market, processors have known Processor Local (PLB) that directly from processor Embedded System (ESB), such PCI, that usually requires bridge host chip interface from system this secondary bus. varies depending processor standardized like PCI. Embedded System confused with term "system bus", widely used architectures refer PLB. Connecting processor through considered Loosely coupled connecting through considered Tightly coupled. Figure example these different processor couplings. Until recently, advanced processors (32-bit) could only accessed through bridge chips supplied processor vendor. This would lead multi-chip connection, which added performance bottlenecks, consumed board space power, added cost design. Now, with programmable logic, it's possible directly access processor local bus, eliminating this series chips, which enhancing importance tight coupling newer designs.
XAPP412 (v1.0) June 2001 www.xilinx.com 1-800-255-7778
Architecting Systems Upgradability with (Internet Reconfigurable Logic)
Embedded System
Processor Local
Loosely Coupled (e.g., PCI)
Tightly Coupled (e.g., Processor Local Bus)
X412_07_050901
Figure Processor coupling
Double Buffering FPGA bitstreams frequently stored flash devices (including Xilinx XC1800 series devices), which experience problems power fails while being written. involves designing your hardware that impervious power failures during upgrade process. goal never have piece hardware that fails operate. hardware meet this requirement, should have Double Buffer design. example method could consisting Default configuration that always available second configuration that store upgrade.This Default configuration never upgraded changed except factory. Addition second storage location allows upgrades occur, since Default changed. Double buffering ensures hardware reliably upgraded. Rollback ability revert previous upgrade (possibly Default). system that space more than configurations, (e.g. using commodity flash chip), could rollback known good upgrade that previously installed.
Examples
Having examined concepts that make design methodology, let's examine practical examples implement IRL-enabled target system using PAVE.
Basic IRL-enabled System
Figure shows IRL-enabled system with processor, FPGA, multiple FPGA configuration storage areas. Processor communicates with FPGA and, after configuration, perform update upgrade PROM. register bridge address space receives bitstream writes PROM JTAG controller.
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XAPP412 (v1.0) June 2001
Architecting Systems Upgradability with (Internet Reconfigurable Logic)
Processor Coupling (ESB PLB)
Embedded Processor
Bridge
FPGA
Slave Serial/ Parallel/ SelectMAP Config
JTAG Config
JTAG Controller
CNTL
Factory Jumper
XC18Vxx Default
XC18Vxx Upgrade
JTAG Connector
Factory Jumper
Select Logic/NVS
X412_08_041701
Figure Example PROM system
PROM marked "Default" known good configuration from factory. default should never upgraded field provides baseline configuration that hardware revert case failure upgrade process. This protects hardware against power failures, customer technician mistakes, other failure mode that would render hardware inoperable (and non-upgradable). preventing user from updating this PROM, will always have fallback position event upgrade fails. factory jumpers Default PROM's JTAG lines physically prevent changing this PROM, except during manufacturing process. upgrade PROM changed through JTAG controller FPGA. With only storage locations, upgrade always overwrites upgrade. Select Logic Non-volatile storage (NVS) determine which PROM should used default configuration error occurs during loading upgrade. it's simplest form, would attempt load upgrade PROM, monitor DONE line FPGA, failed, automatically revert default PROM. Adding small device, such Dallas Semiconductor DS2430A (scratchpad EEPROM) would allow specifying which PROM boot from initially. This could allow more sophisticated approach choosing among multiple upgrades. select logic could CPLD even something simpler, but, like default, should modifiable outside factory (unless there double buffer CPLD configuration). event configuration fault, select logic should able detect this attempt configure FPGA with Default bitstream. bitstream upgrade buffer
XAPP412 (v1.0) June 2001 www.xilinx.com 1-800-255-7778
DATA
Architecting Systems Upgradability with (Internet Reconfigurable Logic) corrupted non-existent, FPGA DONE signal will high. this case select logic should attempt load default bitstream.
Bridge System
Figure shows system with bridge PROM model discussed last example. bridge FPGA initializes PROMs; subsequently target FPGA configured from processor through bridge. previous example FPGA both bridge target. interface this case could with either PLB. register Bridge interface would accept configuration data sent from processor pass target either SelectMAP JTAG controllers. bridge your system requirement; this example apply your design. This figure example could perform double buffering, only way.
Embedded Processor
Processor Coupling
Bridge Interface
Bridge FPGA
SelectMAP Controller
Target FPGA
Slave Serial/ Parallel/ SelectMAP Config
CNTL
JTAG Config
JTAG Controller
DATA
JTAG Connector
Factory Jumper
Factory Jumper
XC18Vxx Default XC18Vxx Upgrade
CNTL DATA
Config. CPLD
SelectMAP Connector
X412_09_050901
Figure System with Bridge Target FPGAs
programmable bridge system processor cannot directly send configuration data prior initial configuration bridge FPGA. aforementioned details insuring known good configuration still applies this bridge. target FPGA this diagram, processor able send configurations directly from processor's data storage. this case, means configuration supported under PAVE shown, SelectMAP JTAG. select logic used bridge CPLD that acting PROMs. General System Considerations Bridges Communication between Processor target FPGA occurs through bridge. bridge facilitates interface processor through specified interface (e.g. ESB, PLB). Most processors require separate chip Bridge) support ESB. When using bridge chip, processor directly mastering FPGA. processors have direct support chip. These considered have bridge built-in; this bridge would non-upgradable.
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XAPP412 (v1.0) June 2001
Architecting Systems Upgradability with (Internet Reconfigurable Logic)
Most SBCs provide direct access plug-in form factor. case CompactPCI system, form factor known Mezzanine Card (PMC) typically used. card loosely coupled processor could board, carrier same chassis. tight coupling would processor local (PLB), such PowerPC 405GP peripheral that directly from processor. upgrade FPGA passes through this coupling into FPGA; this data then updated into appropriate storage area.
Memory usage storing bitstreams
Building models last examples, this next example adds additional memory space bitstream storage. Figure shows loosely coupled system with configuration flash addition PROMs. This flash chip standard commodity flash, which available varying sizes. Depending design, flash chip could store additional Bridge bitstreams, while depending Processor supply configuration target FPGA, target FPGA configurations could stored there well. Flash chips able store much larger amounts configuration data, this could translate multiple upgrades support largest FPGAs.
SelectLink
Connectors
SelectLink
Signals
Core
Virtex-II
SelectMAP Controller
Virtex-II
Slave Serial/ Parallel/ Config
JTAG Config
JTAG Controller
CNTL
DATA
ADDRESS
JTAG Connector
Factory Jumper
XC18Vxx
CNTL DATA
Config. CPLD XC9500
CNTL
XC18Vxx
DATA
Config. Flash
SelectMAP Connector
X412_10_050901
Figure example with Bridge, PROMs, Flash
this case, CPLD considered thin device, basically data with majority logic FPGA. address lines feeding from both FPGA CPLD flash chip would allow controlled from either chip. this example default could reside Configuration flash PROM; thus jumpers shown PROMs. this case, it's responsibility system designer ensure fail-safe operation.
XAPP412 (v1.0) June 2001
www.xilinx.com 1-800-255-7778
Architecting Systems Upgradability with (Internet Reconfigurable Logic)
PAVE Systems
PAVE Framework embedded applications software development framework that employed facilitate development reconfigurable embedded applications. Object Oriented Hardware PAVE Framework components collection classes object models that abstract implementation Xilinx FPGA, called IRL-enabled Device implementation. PAVE treats programmable hardware object within system, similar software objects used C++. result, applications that written using PAVE tend highly object oriented, modular, extremely upgradable. change single module without replacing whole framework. SelectMAP JTAG support PAVE 1.0, programming interfaces supported SelectMAP JTAG, configuration register contained your design, typically bridge. When compiling design under PAVE, define location this other user registers device memory map. PAVE will encapsulate this programming interface generate source header files associated project files based your design definition.
Available Development Platforms
Several development platforms that used available today: Motorola Motorola MCP750 following features: MPC750 Power processor slot Ethernet connection Compact Flash
Motorola Computer Group contacted http://www.mcg.mot.com Alpha Data Alpha Data ADM-XRC card that allows reconfiguration FPGA across bridge. Details found WInd River Systems Wind River Systems makes Tornado-II RTOS development platform. http://www.windriver.com Xilinx Xilinx offers training PAVE Framework.
Summary
With minor hardware software changes, enable your systems much value both your customers. addition your product will extend it's life simplify support distribution models. With IRL, could manufacture single physical version your hardware ship multiple different hardware versions. your customers will appreciate speedy, hassle-free upgradability your products.
www.xilinx.com 1-800-255-7778
XAPP412 (v1.0) June 2001
Architecting Systems Upgradability with (Internet Reconfigurable Logic)
Xilinx PAVE Framework provides powerful software framework that allows designers easily integrate into their designs. object oriented nature PAVE eliminates need handle level issues with JTAG SelectMAP programming, allowing designer focus end-user's application. Future revisions PAVE Framework will bring additional functionality your IRL-enabled design. modular nature PAVE will allow features without disturbing your current application framework.
Revision History
following table shows revision history this document. Date 6/29/01 Version Initial Xilinx release. Revision
XAPP412 (v1.0) June 2001
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Application Note: Internet Reconfigurable Logic Architecting Syst

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