High-Speed Buffered Crossbar Switch Design Using Virtex-EM Devices

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High-Speed Buffered Crossbar Switch Design Using Virtex-EM Devices

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Application Note: Virtex-EM Family
High-Speed Buffered Crossbar Switch Design Using Virtex-EM Devices
Author: Vinita Singhal Robert
XAPP240 (v1.0) March 2000
Summary
High-speed switches increasingly required high-bandwidth applications. face constantly changing networking standards, FPGAs offer switch designers flexibility adaptability. FPGAs with expanded memory capacity, such VirtexTM-E Extended Memory (Virtex-EM) devices, ideally suited scalable, fast switches. This document discusses high-speed buffered crossbar switch that effectively addresses each these concerns.
Introduction
This document highlights features Virtex-EM architecture context high-speed gigabit bandwidth network switch designs. particular, Virtex-EM devices with favorable ratio memory programmable logic naturally suited buffered crossbar switch implementations. address need higher bandwidth created explosive growth Internet corporate intranets, Gigabit Ethernet become preferred standard marketplace. Another emerging standard Common Switch Interface Specification (CSIX), which defines common interface between different switches from different vendors. More information about this standard available CSIX site (http://www.csix.org). Generally, FPGAs ideal choice applications that based changing standards, Virtex-E architecture with extended memory offers ideal solution. 16-port buffered crossbar switch design supporting OC-192 line rate Gb/s port described illustrate Virtex-EM architecture features.
Switch Architectures
three basic switch architectures (shared bus, shared memory, crossbar), shared shared memory architectures have physical functional limitations their scalability. Buffered crossbar switches highly scalable obvious choice highperformance switching.
Basic Crossbar Switches
crossbar switch organized matrix connect input ports output ports. Crossbar switches transfer packets from multiple input ports multiple outputs simultaneously. Each pair input output ports dedicated path through switch, additional ports incorporated adding switching elements. scheduler keeps maximum number output ports busy. Although architecture inherently non-blocking, susceptible head-of-line (HOL) blocking output contention. This occurs when scheduler uses single FIFO buffer input port incoming packets. scheduler considers packet head single FIFO transfer only when reaches head FIFO queue. Packets behind headof-line packet destined other output ports blocked. blocking reduced crossbar architecture maintaining separate FIFO buffers each input-output port pair.
2000 Xilinx, Inc. rights reserved. Xilinx trademarks, registered trademarks, patents, disclaimers listed other trademarks registered trademarks property their respective owners.
XAPP240 (v1.0) March 2000
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High-Speed Buffered Crossbar Switch Design Using Virtex-EM Devices
Buffered Crossbar Switch Architecture
addition buffers crosspoints reduce blocking hence increase throughput referred buffered crossbar switch architecture. This scheme placing buffers crosspoints instead pure input buffering reduces blocking problem caused output contention. With buffer memory placed each crosspoint, scheduler maximize total throughput keep many output ports busy possible storing input packets buffer memory.
Scheduler
Line Card Line Card
Line Card Line Card
Crossbar Switch
x240_01_031300
Figure Buffered Crossbar Switch Architecture
Design Example Using XCV812E Device
Design Overview:
buffered crossbar switch architecture represented Figure memory intensive. Buffer memory requirements switch with support number priority Quality-ofService (QoS) classes buffers. example, switch connecting sixteen 8-bit input ports sixteen 8-bit output ports with single class requires buffers. XCV812E device over 1.12 block RAM, enabling each crosspoint have buffer space. With more than block XCV812E, fully populated buffered cross switch implemented with high-speed True Dual-PortRAM buffers each crosspoint. optimum crosspoint buffer size memory latency important design considerations dictated system bandwidth. Higher aggregate bandwidths obtained breaking data packet into slices switching them parallel. Sixteen XCV812E devices, each implementing byte-wide
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XAPP240 (v1.0) March 2000
High-Speed Buffered Crossbar Switch Design Using Virtex-EM Devices buffered crossbar switch OC-192 rates Gb/s yield aggregate bandwidth Gb/s. (See Figure
buffer size needed crossbar switch data chip crosspoint class should least equal port speed slice round-trip delay control feedback signal. port speed Gb/s data slices crossbar switch chips) propagation delay through line card switch approximately smallest buffer size needed crosspoint class calculated follows: Buffer Size (Gb/s) (ns) 1000 bits
OC-192 10Gbps Data
Data Packet Slice Input Ports 0-15
Device Buffered Crossbar Switch XCV812E Device Buffered Crossbar Switch XCV812E Input Port Output Port Output Port Output Port XCV812E Input Port Input Port
OC-192 10Gbps Data
Data Packet Slice Input Ports 0-15
OC-192 10Gbps Data
Data Packet Slice Input Ports 0-15
Device Buffered Crossbar Switch XCV812E
x240_02_031300
Figure OC-192 Buffered Crossbar Switch
Physical Link
each crossbar implementation, block True Dual-Port link from input output bus. byte-wide partition scheme, 8-bit transfers data clock frequency MHz. bandwidth each port Mb/s (100 bits). total theoretical bandwidth 16-port byte-wide partition 12.8 Gb/s (800 Mb/s 16). Figure illustrates crossbar link detail. Internally crossbar switch buffer synchronous FIFO running MHz. Synchronous designs eliminate problems associated with different timing delays through different parts logic. They also more reliable over variations temperature, voltage process.
XAPP240 (v1.0) March 2000
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High-Speed Buffered Crossbar Switch Design Using Virtex-EM Devices
P0_IN_<7:0> P0_IN_CLK P0_IN_AF Input Link Output Link
P0_OUT_<7:0> P0_OUT_CLK P0_OUT_AF
Switch Matrix P15_IN_<7:0> P15_IN_CLK P15_IN_AF Input Link Output Link P15_OUT_<7:0> P15_OUT_CLK P15_OUT_AF
Control Signals Switching Element
(0,0)
(0,1)
(0,15)
muxes
x240_03_031300
Figure Buffered Crossbar Switch Internal Detail There multiple levels flow control support. lowest level, link-level control used ensure that buffers overflow packets dropped. flow control signal Px_AF each port becomes true when FIFO nearly full. line card control logic sends data only when this signal false. Since latencies board trace lengths flow control signal detecting logic might large, FIFO should capable accepting reasonable amount data even after sending flow control signal indicate near full condition. With more than block RAM, XCV812E device more than adequate.
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XAPP240 (v1.0) March 2000
High-Speed Buffered Crossbar Switch Design Using Virtex-EM Devices
Crossbar links limited particular electrical interfaces. Virtex SelectI/O+technology provides support standards, including three differential signaling standards (LVDS, LVPECL, BLVDS). chip-to-chip interfaces, high-speed single-ended standard, such SSTL3 Class good choice. better noise immunity lower EMI, LVDS differential standard with narrower data width recommended. more details Virtex SelectI/O+ technology, Xilinx application note XAPP133 Further information I/Os based differential signalling obtained from following application notes:
XAPP230 XAPP233
Data Path Buffering Crossbar Switches
Figure illustrates data path each node crosspoint. switching element multiplexer based. Wide muxes used implement data path crossbar switch. cascade/carry feature Virtex-EM device enables very efficient fast implementation high-speed muxes. Synchronous FIFOs used each crosspoint crossbar switch provide buffering. Virtex-E True Dual-Port FIFOs allow incoming data written port transmitted data read from other end. This feature significantly increases memory bandwidth system performance (see XCV812E devices provide blocks block chip with independent control signals each port. data widths ports configured independently, providing built-in bus-width conversion. block also includes dedicated routing efficient interface with both Configurable Logic Blocks (CLBs) other blocks (see Virtex-EM devices, block organized columns, starting left column right outside edge inserted every fourth column. Each memory block four CLBs high, each memory column extends full height chip, immediately adjacent column locations indicated Table Table CLB/Block Column Locations
Virtex-E Device XCV405E XCV812E
True Dual-Port feature coupled with efficient memory block placement ideally suited implementation data path buffering each crosspoint buffered crossbar switch. Figure illustrates floorplan crossbar switch. inputs located upper lower edges chip, with outputs left right edges chip. block buffer memory each crosspoint used build high-performance synchronous synchronous FIFOs. provide distinct Empty/Full conditions, address dropped from FIFO, FIFO depth instead 512. Binary counters used read/write addresses that address block RAM. FIFO performance excess explained detail application note XAPP131 (http://www.xilinx.com/xapp/ xapp131.pdf).
XAPP240 (v1.0) March 2000
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High-Speed Buffered Crossbar Switch Design Using Virtex-EM Devices
Block (BRAM)
P0_IN P2_IN
CLBs (Control Logic Data Path)
P14_IN
P0_OUT
P1_OUT
CLBs (Control Logic Data Path)
CLBs (Control Logic Data Path)
CLBs (Control Logic Data Path)
P14_OUT
P15_OUT
P1_IN P3_IN
P15_IN
x240_4_031300
Figure Floorplan Layout Reference Design
Achieving Maximum Switch Performance
Optical interface standards such Synchronous Optical NETwork (SONET) have made highspeed data rates possible. XCV812E buffered crossbar switch example described above needs keep with OC-192 line rate Gb/s. Having determined that bits data (partitioned sliced into sixteen 8-bit busses) processed parallel port, input FIFOs need operate clock rate Gb/s 128). FIFO clock rate required maintain incoming data rate after considering packet overhead. XCV812E device implement FIFOs that easily meet these requirements. OC-192 buffered crossbar switch design implemented with sixteen XCV812E devices deliver Gb/s ports Gb/s port) aggregate bandwidth. Switch performance further enhanced operating switch buffer memory rate faster than required line rate, known "speed-up." speed-up factor implies that packets transferred from each input port packets destined each output port during each scheduler cycle packet time. Determining optimum speed-up factor fully utilize buffer queues critical switch design. Stanford Professor Nick McKeown cites recent research that suggests crossbar switch with speed-up factor behaves almost identically crossbar switch with speed-up factor independent size Hence, speed-up factor seems optimum implementation.
Conclusion
This application note illustrates Virtex-EM device with abundant True Dual-Port memory makes ideal solution high-speed crossbar switches. Using sixteen XCV812E devices, system designers easily achieve aggregate bandwidth Gb/s buffered crossbar switch application.
www.xilinx.com 1-800-255-7778
XAPP240 (v1.0) March 2000
High-Speed Buffered Crossbar Switch Design Using Virtex-EM Devices
References
"Distributed Processing top," Charlie Jenkins Times, 2000. "Gigabit Ethernet arrived force, with least vendors shipping products various stripes. just time." David Axner, Network World, July 1998. Fast Switched Backplane Gigabit Switched Router," White paper Nick McKeown, Business Communications Review, December 1997 Vol. Survey ASwitching Techniques," Sonia Fahmy, Department Computer Information Science, Ohio State University.
Revision History
following table shows revision history this document. Date 3/14/00 Version Initial Xilinx release. Revision
XAPP240 (v1.0) March 2000
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High-Speed Buffered Crossbar Switch Design Using Virtex-EM Devices

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