Application Note PETER ALFKE BERNIE XAPP 022.000 Summary

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Application Note PETER ALFKE BERNIE XAPP 022.000 Summary

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Adders, Subtracters Accumulators XC3000
Application Note PETER ALFKE BERNIE
XAPP 022.000
Summary
This Application Note surveys different adder techniques that available XC3000 designs. Examples shown, speed/size comparison made.
Xilinx Family
XC3000A XC3100A
Demonstrates
Adder Techniques accumulator register. Since flip-flop set-up time through function generator usually matches combinatorial propagation delay CLB, set-up time accumulator operands similar propagation delay adder.
Introduction
There many ways implement binary adders, subtracters accumulators devices. Various approaches offer different trade-offs between size speed. Most compact, slowest, bit-serial technique that operates bits clock cycle, generating carry. output shift register; carry stored used subsequent time. most compact combinatorial (parallel) adder, subtracter, accumulator consists cascaded CLBs. Each implements full adder, accepting each operand incoming carry. generates outgoing carry. 16-bit function completed delays, requires CLBs. With 5-input function generator, XC3000 implement additions bits time. Three CLBs each handle input bits each operand input carry generate outputs outgoing carry. 16-bit function requires CLBs operation completed eight delays. faster operation, look-ahead carry technique used. Made popular 74181 descendents, look-ahead carry uses Carry Propagate Carry Generate signals reduce ripple-carry delay. Using look-ahead carry techniques XC3000, 16-bit addition completed five delays, using CLBs. even faster conditional-sum algorithm originally described Sklansky. Using this algorithm, 16-bit adder requires CLBs, settles only three delays. With careful layout, propagation delay through such adder less than XC3100-3. Note that Xilinx adder structures used accumulators with size penalty. Unlike conventional gate arrays similar structures, devices provide dedicated flip-flops each that used
Bit-Serial Adders
architecture ideally suited bit-serial arithmetic. shown Figure operands serialized shift registers, presented, first, serial arithmetic unit. created serial stream, again first, that converted parallel data third shift register. Alternatively, input shift registers serve output register, with shifted replace operand. arithmetic unit, Figure comprises 1-bit full adder/ subtracter carry/borrow flip-flop, implemented single CLB. Before commencing operation (addition subtraction) carry/borrow flip-flop must cleared. Subsequently, differences passed output shift register, while carries borrows stored inclusion next serial operation.
Operand An-1 Shift Register Serial Arithmetic Unit Bn-1 Shift Register Bn-1 Operand ADD/SUB RESET
X3119
Shift Register
Figure Serial Adder/Subtracter
Supporting design files available XACT CD-ROM Xilinx Technical Bulletin Board under names XAPP022V (VIEWlogic) XAPP022O (OrCAD)
8-98 This document created with FrameMaker
ADD/SUB
RESET
X3120
Figure Serial Arithmetic Unit
While number clocks required complete operation equals number bits, clock period very small because shallow logic. maximum clock speed, first output shift register should implemented same arithmetic unit. Faster bit-serial operation obtained simultaneously operating bits, Figure even bits each operand loaded into separate shift registers. arithmetic unit takes bits each operand, produces bits clock. These bits loaded into even output shift registers.
Figure shows 2-bit arithmetic unit. Both bits derived parallel, single carry generated stored next cycle. This arithmetic unit permits adders subtracters constructed, adders/ subtracters. adders/subtracter operation, arithmetic unit should implement adder; generate A-B, A-operand should inverted while loading opeand shift register, bits should inverted into output register. carry flip-flop cleared before each operation, regardless whether addition subtraction. While clock rate similar 1-bit scheme, only half many clocks required complete operation.
Operand An-2 Shift Register An-1 Shift Register
2-Bit Arithmetic Unit AEVEN
Ripple-carry Adders
1-bit serial adder, described above, easily converted into ripple-carry parallel adder. simply matter replicating arithmetic unit once each bit, removing carry/borrow flip-flops connecting carry/borrow outputs from next, Figure carry/borrow input zero carry addition, borrow subtraction. bit, this design uses fewer CLBs than other parallel adder. However, this compactness achieved expense speed; settling time delay bit. placing CLBs adder adjacent each other, interconnect delay ripple path minimized, even eliminated.
AODD
SUMEVEN Sn-2
Shift Register Shift Register Sn-1
Shift Register Bn-2 Shift Register Bn-1 Operand
BEVEN
SUMODD
BODD
X3121
Figure 2-Bit Serial Adder
XAPP 022.000
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Adders, Subtracters Accumulators XC3000
AEVEN BEVEN
SEVEN
AODD BODD
SODD
RESET
X3125
Figure 2-Bit Serial Arithmetic Unit
ADD/SUB
faster settling time achieved changing replicated cell from 1-bit adder 2-bit adder, Figure carry output more significant each bitpair functions five inputs. Consequently, each requires entire CLB, increasing requirement bit. However, settling time reduced delay bits, half that previous design. 5-input function generators permit this design used adders subtracters, adder/subtracters. implement adder/subtracter, operands adder must modified before being input into adder.
1-Bit Adder 1-Bit Adder
X3388
Figure One-Bit-At-A-Time Ripple-Carry Adder
operation A-B, there choices, both which require additional gates invert operands while subtracting. technique used bit-serial adder one-bit-at-a-time adder invert A-operand into carry logic only; A-operand input logic unmodified. this case, carry/ borrow input active-high both subtract, tied input carry borrow required.
XAPP 022.000
8-100
X3127
Figure Two-Bits-At-A-Time Ripple-Carry Adder
XAPP 022.000
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Adders, Subtracters Accumulators XC3000
more conventional approach invert B-operand into both carry logic. However, input borrow carry required, input must during addition, High during subtraction.
Look-ahead-carry Adders
faster operation large adders, look-ahead carry lookahead-carry technique uses signals, Carry Generate Carry Propagate that typically outputs arithmetic block, often four bits. Since both these signals depend incoming carry signal, they generated immediately from input data.
name implies, Carry Generate asserted block creates overflow (carry), regardless incoming carry. example, 4-bit adder, Carry Generate asserted operand bits, excluding incoming carry, exceeds block does generate carry itself, would generate carry result incoming carry, Carry Propagate must asserted; assertion optional block generates carry without requiring incoming carry. 4-bit example, Carry Propagate must asserted when sum, excluding incoming carry, exactly optionally asserted when greater.
Look-Ahead Adder Above)
X3128
Figure Four-Bits-at-a-time Adder Block with Internal Look-Ahead Carry
XAPP 022.000
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XC3000 devices, look-ahead carry most effective when used combine 2-bit blocks into 4-bit block that cascades using ripple carry, Figure 4-bit block one-CLB delay from carry carry out, two-CLB delay from carry output more significant bit-pair. delay from operand inputs carry output also CLBs. 16-bit adder implemented ways. most straightforward cascade four 4-bit blocks, shown Figure 8(a). With this design, carry-in-tocarry-out delay only four CLBs, while operand-tosum delay CLBs; operand-to-carry-out carry-in-to-sum delays both five CLBs carry output available delay before sum, carry input need present until delay after operands. design requires CLBs. While shorter carry delay sometimes desirable, design Figure 8(b) faster overall, balancing four delays five CLBs. 2-bit ripple-carry block,
described ripple-carry section, used implement most least significant bit-pairs, only CLBs required. Either design adapted multiple four bits simply adding subtracting 4-bit blocks center adder. advantage over 2-bit ripple-carry technique increases with number bits adder. even numbers bits that multiples four, designs Figure used. 14-bit adder, Figure 9(a) design balances four delays five CLBs, requires CLBs. Figure 9(b) 9(c) designs each additional CLBs, delay faster carry path. Figure 9(b) design carry appears delay before sum, Figure 9(c) design, carry need present until delay after operand. Again, different length adders, simply subtract 4-bit blocks center adder.
COUT COUT A14-15 B14-15 4-Bit Adder B12-15 A10-13 4-Bit Adder A8-11 4-Bit Adder B8-11 A6-9 4-Bit Adder A4-7 4-Bit Adder B4-7 A2-5 4-Bit Adder A0-3 4-Bit Adder B0-3 A0-1 B0-1
X3130
2-Bit Adder
S14-15
A12-15 S12-15
S10-13
B10-13 S8-11
S6-9
B6-9 S4-7
S2-5
B2-5 S0-3 2-Bit Adder
S0-1
Figure 16-Bit Adder Configurations
XAPP 022.000
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Adders, Subtracters Accumulators XC3000
COUT COUT A12-13 B12-13 2-Bit Adder S12-13 A10-13 4-Bit Adder B10-13 A8-11 4-Bit Adder B8-11 S8-11 A6-9 4-Bit Adder B6-9 A4-7 4-Bit Adder B4-7 S4-7 A2-5 4-Bit Adder B2-5 A2-3 B2-3 2-Bit Adder S2-3 A0-3 A0-1 B0-1 A0-1 B0-1 2-Bit Adder S0-1 2-Bit Adder S0-3 S0-1 B0-3 S2-5 B4-7 A4-7 S4-7 S6-9 B8-11 A8-11 S8-11 S10-13 A12-13 B12-13 S12-13 COUT
X3131
Figure 14-Bit Adder Configuration
Conditional-sum Adder
CLBs Delays
Conditional-sum adders, originally described Sklansky June 1960 issue Transaction Electronic Computers, reduce settling time expense much higher logic complexity. version described below created Matt Klein Hewlett Packard, modified algorithm XC3000 architecture. With careful placement routing, total delay kept below XC3100-3. Forty-one CLBs required, which generate function five variables, while remaining CLBs each generate functions four variables. Figure shows these CLBs connected. more information, please refer original paper Xilinx Technical Bulletin Board.
1141
Figure 4-Bit Adder
XAPP 022.000
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Application Note PETER ALFKE BERNIE XAPP 022.000 Summary

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