FEATURES ADF4110: ADF4111: ADF4112: ADF4113: Power Supply Separate Cha

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FEATURES ADF4110: ADF4111: ADF4112: ADF4113: Power Supply Separate Cha

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Frequency Synthesizers ADF4110/ADF4111/ADF4112/ADF4113
FEATURES ADF4110: ADF4111: ADF4112: ADF4113: Power Supply Separate Charge Pump Supply (VP) Allows Extended Tuning Voltage Systems Programmable Dual Modulus Prescaler 8/9, 16/17, 32/33, 64/65 Programmable Charge Pump Currents Programmable Antibacklash Pulsewidth 3-Wire Serial Interface Analog Digital Lock Detect Hardware Software Power-Down Mode
ADF4110 family frequency synthesizers used implement local oscillators upconversion downconversion sections wireless receivers transmitters. They consist low-noise digital (Phase Frequency Detector), precision charge pump, programmable reference divider, programmable counters dual-modulus prescaler (P/P+1). (6-bit) (13-bit) counters, conjunction with dual modulus prescaler (P/P+1), implement divider addition, 14-bit reference counter Counter), allows selectable REFIN frequencies input. complete (Phase-Locked Loop) implemented synthesizer used with external loop filter (Voltage Controlled Oscillator). Control on-chip registers simple 3-wire interface. devices operate with power supply ranging from powered down when use.
APPLICATIONS Base Stations Wireless Radio (GSM, PCS, DCS, CDMA, WCDMA) Wireless Handsets (GSM, PCS, DCS, CDMA, WCDMA) Wireless LANS Communications Test Equipment CATV Equipment FUNCTIONAL BLOCK DIAGRAM
AVDD DVDD CPGND
RSET
REFERENCE
REFIN
14-BIT COUNTER COUNTER LATCH
PHASE FREQUENCY DETECTOR
CHARGE PUMP
DATA COUNTER LATCH 24-BIT INPUT REGISTER FUNCTION LATCH LOCK DETECT CURRENT SETTING CURRENT SETTING
SDOUT
CPI3 CPI2 CPI1 CPI6 CPI5 CPI4
FROM FUNCTION LATCH
HIGH AVDD 13-BIT COUNTER LOAD LOAD 6-BIT COUNTER MUXOUT
RFINA RFINB
SDOUT
PRESCALER
ADF4110/ADF4111 ADF4112/ADF4113
AGND
DGND
REV.
Information furnished Analog Devices believed accurate reliable. However, responsibility assumed Analog Devices use, infringements patents other rights third parties which result from use. license granted implication otherwise under patent patent rights Analog Devices. Technology Way, P.O. 9106, Norwood, 02062-9106, U.S.A. Tel: 781/329-4700 World Wide Site: http://www.analog.com Fax: 781/326-8703 Analog Devices, Inc., 2000
noted) 10%, 10%; AGND DGND CPGND unless
Parameter CHARACTERISTICS Input Frequency ADF4110 ADF4110 ADF4111 ADF4112 ADF4112 ADF4113 Input Sensitivity Maximum Allowable Prescaler Output Frequency3 CHARACTERISTICS Input Frequency ADF4110 ADF4111 ADF4112 ADF4113 ADF4113 Input Sensitivity Maximum Allowable Prescaler Output Frequency3 REFIN CHARACTERISTICS REFIN Input Frequency Reference Input Sensitivity4 REFIN Input Capacitance REFIN Input Current PHASE DETECTOR Phase Detector Frequency5 CHARGE PUMP Sink/Source High Value Value Absolute Accuracy RSET Range 3-State Leakage Current Sink Source Current Matching Temperature LOGIC INPUTS VINH, Input High Voltage VINL, Input Voltage IINH/IINL, Input Current CIN, Input Capacitance LOGIC OUTPUTS VOH, Output High Voltage VOL, Output Voltage POWER SUPPLIES AVDD DVDD IDD6 (AIDD DIDD ADF4110 ADF4111 ADF4112 ADF4113 Power Sleep Mode
Version
Chips
Unit
Test Conditions/Comments Figure Input Circuit. square wave lower frequencies.
45/550 25/550 0.045/1.2 0.2/3.0 0.1/3.0 0.2/3.7 -15/0
45/550 25/550 0.045/1.2 0.2/3.0 0.1/3.0 0.2/3.7 -15/0
min/max min/max min/max min/max min/max min/max min/max
Input Level
Input Level Input Level
square wave lower frequencies. 25/550 0.025/1.4 0.1/3.0 0.2/3.7 0.2/4.0 -10/0 0/100 -5/0 25/550 0.025/1.4 0.1/3.0 0.2/3.7 0.2/4.0 -10/0 0/100 -5/0 min/max min/max min/max min/max min/max min/max min/max min/max Programmable: Table With RSET With RSET Table VP/2
Input Level
AC-Coupled. When DC-Coupled: (CMOS-Compatible)
2.7/10 DVDD DVDD DVDD 2.7/5.5 AVDD AVDD/6.0
2.7/10 DVDD DVDD DVDD 2.7/5.5 AVDD AVDD/6.0
min/V min/V
AVDD Figures Typical Typical Typical Typical 25°C REV.
ADF4110/ADF4111/ADF4112/ADF4113
Parameter NOISE CHARACTERISTICS ADF4113 Phase Noise Floor Phase Noise Performance8 ADF4110: Output9 ADF4111: Output10 ADF4112: Output10 ADF4113: Output10 ADF4111: Output11 ADF4112: 1750 Output ADF4112: 1750 Output ADF4112: 1960 Output ADF4113: 1960 Output ADF4113: 3100 Output Spurious Signals ADF4110: Output9 ADF4111: Output10 ADF4112: Output10 ADF4113: Output10 ADF4111: Output11 ADF4112: 1750 Output ADF4112: 1750 Output ADF4112: 1960 Output ADF4113: 1960 Output ADF4113: 3100 Output15
NOTES
Operating temperature range follows: Version: -40°C +85°C. Chip specifications given typical values. This maximum operating frequency CMOS counters. prescaler value should chosen ensure that input divided down frequency which less than this value. AVDD DVDD AVDD DVDD CMOS-compatible levels. Guaranteed design. 25°C; AVDD DVDD SYNC RFIN ADF4110 MHz; RFIN ADF4111, ADF4112, ADF4113 MHz. synthesizer phase noise floor estimated measuring in-band phase noise output subtracting logN (where divider value). phase noise measured with EVAL-ADF411XEB1 Evaluation Board HP8562E Spectrum Analyzer. spectrum analyzer provides REFIN synthesizer (fREFOUT dBm). SYNC (See Table III). fREFIN MHz; fPFD kHz; Offset frequency kHz; MHz; 2700; Loop kHz. fREFIN MHz; fPFD kHz; Offset frequency kHz; MHz; 4500; Loop kHz. fREFIN MHz; fPFD kHz; Offset frequency MHz; 27867; Loop kHz. fREFIN MHz; fPFD kHz; Offset frequency kHz; 1750 MHz; 8750; Loop kHz. fREFIN MHz; fPFD kHz; Offset frequency 1750 MHz; 175000; Loop kHz. fREFIN MHz; fPFD kHz; Offset frequency kHz; 1960 MHz; 9800; Loop kHz. fREFIN MHz; fPFD MHz; Offset frequency kHz; 3100 MHz; 3100; Loop kHz.
Version -171 -164 -97/-106 -98/-110 -91/-100 -100/-110 -81/-84 -88/-90 -65/-73 -80/-84 -80/-84 -80/-82
Chips2 -171 -164 -97/-106 -98/-110 -91/-100 -100/-110 -81/-84 -88/-90 -65/-73 -80/-84 -80/-84 -82/-82
Unit dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz
Test Conditions/Comments Frequency Frequency Output Offset Frequency Offset Frequency Offset Frequency Offset Frequency Offset Frequency Offset Frequency Offset Frequency Offset Frequency Offset Frequency Offset Frequency kHz/400 Frequency kHz/400 Frequency kHz/400 Frequency kHz/400 Frequency kHz/60 Frequency kHz/400 Frequency kHz/20 Frequency kHz/400 Frequency kHz/400 Frequency MHz/2 Frequency
Specifications subject change without notice.
TIMING CHARACTERISTICS1
Parameter
(AVDD DVDD 10%, 10%; AVDD AGND DGND CPGND TMIN TMAX unless otherwise noted)
Unit Test Conditions/Comments DATA CLOCK Setup Time DATA CLOCK Hold Time CLOCK High Duration CLOCK Duration CLOCK Setup Time Pulsewidth
Limit TMIN TMAX Version)
NOTES Guaranteed design production tested. Specifications subject change without notice.
REV.
ADF4110/ADF4111/ADF4112/ADF4113
CLOCK
DATA DB20 (MSB) DB19
(CONTROL (LSB) (CONTROL
Figure Timing Diagram
ABSOLUTE MAXIMUM RATINGS
25°C unless otherwise noted)
AVDD GND3 -0.3 AVDD DVDD -0.3 +0.3 -0.3 AVDD -0.3 +5.5 Digital Voltage -0.3 Analog Voltage -0.3 REFIN, RFINA, RFINB -0.3 Operating Temperature Range Industrial Version) -40°C +85°C Storage Temperature Range -65°C +150°C Maximum Junction Temperature 150°C TSSOP Thermal Impedance 150.4°C/W Thermal Impedance (Paddle Soldered) 122°C/W
Thermal Impedance (Paddle Soldered) 216°C/W Lead Temperature, Soldering Vapor Phase sec) 215°C Infrared sec) 220°C
NOTES Stresses above those listed under Absolute Maximum Ratings cause permanent damage device. This stress rating only; functional operation device these other conditions above those listed operational sections this specification implied. Exposure absolute maximum rating conditions extended periods affect device reliability. This device high-performance integrated circuit with rating sensitive. Proper precautions should taken handling assembly. AGND DGND
TRANSISTOR COUNT
6425 (CMOS) (Bipolar).
CAUTION (electrostatic discharge) sensitive device. Electrostatic charges high 4000 readily accumulate human body test equipment discharge without detection. Although ADF4110/ADF4111/ADF4112/ADF4113 features proprietary protection circuitry, permanent damage occur devices subjected high-energy electrostatic discharges. Therefore, proper precautions recommended avoid performance degradation loss functionality.
WARNING!
SENSITIVE DEVICE
ORDERING GUIDE
Model ADF4110BRU ADF4110BCP ADF4111BRU ADF4111BCP ADF4112BRU ADF4112BCP ADF4113BRU ADF4113BCP ADF4113BCHIPS
Temperature Range -40°C +85°C -40°C +85°C -40°C +85°C -40°C +85°C -40°C +85°C -40°C +85°C -40°C +85°C -40°C +85°C -40°C +85°C
Package Description Thin Shrink Small Outline Package (TSSOP) Chip Scale Package (CSP) Thin Shrink Small Outline Package (TSSOP) Chip Scale Package (CSP) Thin Shrink Small Outline Package (TSSOP) Chip Scale Package (CSP) Thin Shrink Small Outline Package (TSSOP) Chip Scale Package (CSP) DICE
Package Option* RU-16 CP-20 RU-16 CP-20 RU-16 CP-20 RU-16 CP-20 DICE
*Contact factory chip availability.
REV.
ADF4110/ADF4111/ADF4112/ADF4113
FUNCTION DESCRIPTIONS
Mnemonic RSET
Function Connecting resistor between this CPGND sets maximum charge pump output current. nominal voltage potential RSET 0.56 relationship between RSET
23.5 RSET
CPGND AGND RFINB RFINA AVDD REFIN
DGND DATA MUXOUT DVDD
with RSET ICPmax Charge Pump Output. When enabled this provides ±ICP external loop filter, which turn drives external VCO. Charge Pump Ground. This ground return path charge pump. Analog Ground. This ground return path prescaler. Complementary Input Prescaler. This point should decoupled ground plane with small bypass capacitor, typically Figure Input Prescaler. This small signal input normally ac-coupled from VCO. Analog Power Supply. This range from Decoupling capacitors analog ground plane should placed close possible this pin. AVDD must same value DVDD. Reference Input. This CMOS input with nominal threshold VDD/2 equivalent input resistance Figure This input driven from CMOS crystal oscillator ac-coupled. Digital Ground. Chip Enable. logic this powers down device puts charge pump output into threestate mode. Taking high will power device depending status power-down Serial Clock Input. This serial clock used clock serial data registers. data latched into 24-bit shift register rising edge. This input high impedance CMOS input. Serial Data Input. serial data loaded first with LSBs being control bits. This input high impedance CMOS input. Load Enable, CMOS Input. When goes high, data stored shift registers loaded into four latches, latch being selected using control bits. This multiplexer output allows either Lock Detect, scaled scaled Reference Frequency accessed externally. Digital Power Supply. This range from Decoupling capacitors digital ground plane should placed close possible this pin. DVDD must same value AVDD. Charge Pump Power Supply. This should greater than equal VDD. systems where used drive with tuning range
CONFIGURATIONS TSSOP
RSET CPGND AGND RFINB
CHIP SCALE PACKAGE
DVDD DGND RSET DVDD
MUXOUT DATA
ADF4110 ADF4111 ADF4112 ADF4113
DVDD MUXOUT
CPGND AGND AGND RFINB RFINA
VIEW DATA (Not Scale) RFINA AVDD REFIN
ADF4110 ADF4111 ADF4112 ADF4113
VIEW (Not Scale)
REV.
DGND
AVDD
AVDD
REFIN
DGND
Performance Characteristics
FREQ-UNIT PARAM-TYPE DATA-FORMAT KEYWORD FREQ 0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40 0.45 0.50 0.55 0.60 0.65 0.70 0.75 0.80 0.85 0.90 0.95 1.00 MAGS11 0.89207 0.8886 0.89022 0.96323 0.90566 0.90307 0.89318 0.89806 0.89565 0.88538 0.89699 0.89927 0.87797 0.90765 0.88526 0.81267 0.90357 0.92954 0.92087 0.93788 ANGS11 -2.0571 -4.4427 -6.3212 -2.1393 -12.13 -13.52 -15.746 -18.056 -19.693 -22.246 -24.336 -25.948 -28.457 -29.735 -31.879 -32.681 -31.522 -34.222 -36.961 -39.343 FREQ 1.05 1.10 1.15 1.20 1.25 1.30 1.35 1.40 1.45 1.50 1.55 1.60 1.65 1.70 1.75 1.80 IMPEDANCE OHMS ANGS11 -40.134 -43.747 -44.393 -46.937 -49.6 -51.884 -51.21 -53.55 -56.786 -58.781 -60.545 -61.43 -61.241 -64.051 -66.19 -63.775
OUTPUT POWER -100 -2kHz
REFERENCE LEVEL -4.2dBm
FREQUENCY 200kHz LOOP BANDWIDTH 20kHz RES. BANDWIDTH 10Hz VIDEO BANDWIDTH 10Hz SWEEP SECONDS AVERAGES
MAGS11 0.9512 0.93458 0.94782 0.96875 0.92216 0.93755 0.96178 0.94354 0.95189 0.97647 0.98619 0.95459 0.97945 0.98864 0.97399 0.97216
-92.5dBc/Hz
-1kHz
900MHz
+1kHz
+2kHz
Figure S-Parameter Data ADF4113 Input GHz)
Figure ADF4113 Phase Noise (900 MHz, kHz, kHz) with SYNC Enabled
INPUT POWER
10dB/DIVISION
-40dBc/Hz
NOISE 0.52
PHASE NOISE dBc/Hz
INPUT FREQUENCY
0.52 -100 -110 -120 -130 -140 100Hz
FREQUENCY OFFSET FROM 900MHz CARRIER
1MHz
Figure Input Sensitivity (ADF4113)
Figure ADF4113 Integrated Phase Noise (900 MHz, kHz, kHz, Typical Lock Time:
OUTPUT POWER -100 -2kHz -1kHz 900MHz +1kHz +2kHz -91.0dBc/Hz REFERENCE LEVEL -4.2dBm FREQUENCY 200kHz LOOP BANDWIDTH 20kHz RES. BANDWIDTH 10Hz VIDEO BANDWIDTH 10Hz SWEEP SECONDS AVERAGES
10dB/DIVISION
-40dBc/Hz
NOISE 0.62
PHASE NOISE dBc/Hz
0.62 -100 -110 -120 -130 -140 100Hz
FREQUENCY OFFSET FROM 900MHz CARRIER
1MHz
Figure ADF4113 Phase Noise (900 MHz, kHz, kHz)
Figure ADF4113 Integrated Phase Noise (900 MHz, kHz, kHz, Typical Lock Time:
REV.
ADF4110/ADF4111/ADF4112/ADF4113
REFERENCE LEVEL -4.2dBm FREQUENCY 200kHz LOOP BANDWIDTH 20kHz RES. BANDWIDTH 10Hz -100 -400kHz -200kHz 900MHz +200kHz +400kHz -90.2dBc VIDEO BANDWIDTH 10Hz SWEEP SECONDS AVERAGES
10dB/DIVISION -40dBc/Hz NOISE
PHASE NOISE dBc/Hz
OUTPUT POWER
-100 -110 -120 -130 -140 100Hz
FREQUENCY OFFSET FROM 1750MHz CARRIER
1MHz
Figure ADF4113 Reference Spurs (900 MHz, kHz, kHz)
Figure ADF4113 Integrated Phase Noise (1750 MHz, kHz, kHz)
REFERENCE LEVEL -4.2dBm
FREQUENCY 200kHz POWER OUTPUT LOOP BANDWIDTH 35kHz RES. BANDWIDTH 1kHz VIDEO BANDWIDTH 1kHz SWEEP SECONDS AVERAGES
-100
REFERENCE LEVEL -5.7dBm
FREQUENCY 30kHz LOOP BANDWIDTH 3kHz RES. BANDWIDTH VIDEO BANDWIDTH SWEEP SECONDS POSITIVE PEAK DETECT MODE -79.6dBc
OUTPUT POWER
-89.3dBc
-100
-400kHz
-200kHz
900MHz
+200kHz
+400kHz
-80kHz
-40kHz
1750MHz
+40kHz
+80kHz
Figure ADF4113 Reference Spurs (900 MHz, kHz, kHz)
Figure ADF4113 Reference Spurs (1750 MHz, kHz, kHz)
OUTPUT POWER -100 -400Hz -200Hz 1750MHz +200Hz +400Hz -75.2dBc/Hz
REFERENCE LEVEL -8.0dBm
FREQUENCY 30kHz LOOP BANDWIDTH 3kHz
OUTPUT POWER
REFERENCE LEVEL -4.2dBm
FREQUENCY 1MHz LOOP BANDWIDTH 100kHz RES. BANDWIDTH 10Hz VIDEO BANDWIDTH 10Hz SWEEP SECONDS AVERAGES -86.6dBc/Hz
RES. BANDWIDTH 10kHz VIDEO BANDWIDTH 10kHz SWEEP 477ms AVERAGES
-100 -2kHz -1kHz
3100MHz
+1kHz
+2kHz
Figure ADF4113 Phase Noise (1750 MHz, kHz, kHz)
Figure ADF4113 Phase Noise (3100 MHz, MHz, kHz)
REV.
ADF4110/ADF4111/ADF4112/ADF4113
10dB/DIVISION -40dBc/Hz NOISE
PHASE NOISE dBc/Hz
PHASE NOISE dBc/Hz
-100 -110 -120 -130 -140 100Hz
FREQUENCY OFFSET FROM 3100MHz CARRIER
1MHz
-100
TEMPERATURE
Figure ADF4113 Integrated Phase Noise (3100 MHz, MHz, kHz)
Figure ADF4113 Phase Noise Temperature (900 MHz, kHz, kHz)
OUTPUT POWER -100 -2MHz -1MHz REFERENCE LEVEL -17.2dBm
LOOP BANDWIDTH 100kHz RES. BANDWIDTH 1kHz VIDEO BANDWIDTH 1kHz SWEEP SECONDS AVERAGES FIRST REFERENCE SPUR FREQUENCY 1MHz
-80.6dBc
3100MHz
+1MHz
+2MHz
-100
TEMPERATURE
Figure ADF4113 Reference Spurs (3100 MHz, MHz, kHz)
Figure ADF4113 Reference Spurs Temperature (900 MHz, kHz, kHz)
-120
FIRST REFERENCE SPUR
1000 PHASE DETECTOR FREQUENCY 10000
-130
PHASE NOISE dBc/Hz
-140
-150
-160
-170
-180
-105
TUNING VOLTAGE Volts
Figure ADF4113 Phase Noise (Referred Output) Frequency
Figure ADF4113 Reference Spurs (200 kHz) VTUNE (900 MHz, kHz, kHz)
REV.
ADF4110/ADF4111/ADF4112/ADF4113
ADF4113
PHASE NOISE dBc/Hz
AIDD
ADF4112
ADF4110 ADF4111
16/17 PRESCALER VALUE 32/33 64/65
-100
TEMPERATURE
Figure ADF4113 Phase Noise Temperature (836 MHz, kHz, kHz)
Figure AIDD Prescaler Value
FIRST REFERENCE SPUR
DIDD
-100
TEMPERATURE
PRESCALER OUTPUT FREQUENCY
Figure ADF4113 Reference Spurs Temperature (836 MHz, kHz, kHz)
Figure DIDD Prescaler Output Frequency (ADF4110, ADF4111, ADF4112, ADF4113)
REV.
ADF4110/ADF4111/ADF4112/ADF4113
CIRCUIT DESCRIPTION
REFERENCE INPUT SECTION Pulse Swallow Function
reference input stage shown Figure normally-closed switches. normally-open. When power-down initiated, closed opened. This ensures that there loading REFIN power-down.
POWER-DOWN CONTROL 100k COUNTER BUFFER
counters, conjunction with dual modulus prescaler, make possible generate output frequencies that spaced only Reference Frequency divided equation frequency follows: fVCO fREFIN/R fVCO Output frequency external voltage controlled oscillator (VCO). Preset modulus dual modulus prescaler Preset Divide Ratio binary 13-bit counter 8191). Preset Divide Ratio binary 6-bit swallow counter 63).
REFIN
fREFIN Output frequency external reference frequency oscillator. Preset divide ratio binary 14-bit programmable reference counter 16383).
Figure Reference Input Stage
INPUT STAGE
input stage shown Figure followed 2-stage limiting amplifier generate (Current Mode Logic) clock levels needed prescaler.
BIAS GENERATOR RFINA RFINB 1.6V AVDD
COUNTER
14-bit counter allows input reference frequency divided down produce reference clock phase frequency detector (PFD). Division ratios from 16,383 allowed.
13-BIT COUNTER FROM INPUT STAGE PRESCALER MODULUS CONTROL
AGND
LOAD LOAD 6-BIT COUNTER
Figure Input Stage Figure Counters
PRESCALER (P/P+1)
dual-modulus prescaler (P/P+1), along with counters, enables large division ratio, realized dual-modulus prescaler, operating levels, takes clock from input stage divides down manageable frequency CMOS counters. prescaler programmable. software 8/9, 16/17, 32/33, 64/65. based synchronous core.
COUNTERS
PHASE FREQUENCY DETECTOR (PFD) CHARGE PUMP
CMOS counters combine with dual modulus prescaler allow wide ranging division ratio feedback counter. counters specified work when prescaler output less. Thus, with input frequency GHz, prescaler value 16/17 valid value valid.
takes inputs from counter counter produces output proportional phase frequency difference between them. Figure simplified schematic. includes programmable delay element which controls width antibacklash pulse. This pulse ensures that there dead zone transfer function minimizes phase noise reference spurs. bits Reference Counter Latch, ABP2 ABP1 control width pulse. Table III.
-10-
REV.
ADF4110/ADF4111/ADF4112/ADF4113
CHARGE PUMP DIVIDER CLR1
N-channel open-drain analog lock detect should operated with external pull-up resistor nominal. When lock been detected this output will high with narrow lowgoing pulses.
DVDD
PROGRAMMABLE DELAY
ABP1 CLR2 DIVIDER
ABP2
ANALOG LOCK DETECT DIGITAL LOCK DETECT COUNTER OUTPUT COUNTER OUTPUT SDOUT
CONTROL
MUXOUT
DOWN
DGND
Figure MUXOUT Circuit
CPGND
INPUT SHIFT REGISTER
DIVIDER
DIVIDER
OUTPUT
Figure Simplified Schematic Timing Lock)
MUXOUT LOCK DETECT
ADF4110 family digital section includes 24-bit input shift register, 14-bit counter 19-bit counter, comprising 6-bit counter 13-bit counter. Data clocked into 24-bit shift register each rising edge CLK. data clocked first. Data transferred from shift register four latches rising edge destination latch determined state control bits (C2, shift register. These LSBs DB1, shown timing diagram Figure truth table these bits shown Table Table shows summary latches programmed.
Table Truth Table
output multiplexer ADF4110 family allows user access various internal points chip. state MUXOUT controlled function latch. Table shows full truth table. Figure shows MUXOUT section block diagram form.
Lock Detect
Control Bits
Data Latch Counter Counter Function Latch (Including Prescaler) Initialization Latch
MUXOUT programmed types lock detect: digital lock detect analog lock detect. Digital lock detect active high. When counter latch digital lock detect high when phase error three consecutive Phase Detector cycles less than With five consecutive cycles less than required lock detect. will stay high until phase error greater than detected subsequent cycle.
REV.
-11-
ADF4110/ADF4111/ADF4112/ADF4113
Table ADF4110 Family Latch Summary
REFERENCE COUNTER LATCH
RESERVED LOCK DETECT PRECISION
SYNC
TEST MODE BITS
ANTIBACKLASH WIDTH DB16 DB15 DB14 DB13
14-BIT REFERENCE COUNTER, DB12 DB11 DB10
CONTROL BITS
DB23
DB22 DB21 SYNC
DB20 DB19
DB18 DB17
ABP2 ABP1
DON'T CARE
COUNTER LATCH
GAIN
RESERVED DB23 DB22
13-BIT COUNTER DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10
6-BIT COUNTER
CONTROL BITS
DB21 DB20
DON'T CARE
FUNCTION LATCH
FASTLOCK MODE FASTLOCK ENABLE POLARITY COUNTER RESET
POWERDOWN
PRESCALER VALUE DB23
CURRENT SETTING DB20 DB19 CPI6 CPI5
CURRENT SETTING
TIMER COUNTER CONTROL
POWERDOWN
THREESTATE
MUXOUT CONTROL
CONTROL BITS
DB22 DB21
DB18 DB17 CPI4 CPI3
DB16 DB15 DB14 DB13 DB12 DB11 CPI2 CPI1
DB10
INITIALIZATION LATCH
FASTLOCK MODE FASTLOCK ENABLE POLARITY COUNTER RESET
POWERDOWN
PRESCALER VALUE DB23 DB22
CURRENT SETTING DB19 DB18 CPI5 CPI4
CURRENT SETTING DB17 DB16 CPI3 CPI2
TIMER COUNTER CONTROL DB13 DB12
MUXOUT CONTROL
POWERDOWN
THREESTATE
CONTROL BITS
DB21 DB20 CPI6
DB15 DB14 CPI1
DB11 DB10
-12-
REV.
ADF4110/ADF4111/ADF4112/ADF4113
Table III. Reference Counter Latch
RESERVED
LOCK DETECT PRECISION
SYNC
TEST MODE BITS DB19 DB18
ANTIBACKLASH WIDTH DB17 DB16 ABP2 ABP1 DB15 DB14 DB13 DB12
14-BIT REFERENCE COUNTER DB11 DB10
CONTROL BITS
DB23 DB22
DB21 DB20 SYNC
DON'T CARE DIVIDE RATIO 16380 16381 16382 16383
ABP2 ABP1
ANTIBACKLASH PULSEWIDTH 3.0ns 1.5ns 6.0ns 3.0ns
TEST MODE BITS SHOULD NORMAL OPERATION
OPERATION THREE CONSECUTIVE CYCLES PHASE DELAY LESS THAN 15ns MUST OCCUR BEFORE LOCK DETECT SET. FIVE CONSECUTIVE CYCLES PHASE DELAY LESS THAN 15ns MUST OCCUR BEFORE LOCK DETECT SET.
SYNC
OPERATION NORMAL OPERATION OUTPUT PRESCALER RESYNCHRONIZED WITH NONDELAYED VERSION INPUT NORMAL OPERATION OUTPUT PRESCALER RESYNCHRONIZED WITH DELAYED VERSION INPUT
REV.
-13-
ADF4110/ADF4111/ADF4112/ADF4113
Table Counter Latch
GAIN
RESERVED DB23 DB22
13-BIT COUNTER DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10
6-BIT COUNTER
CONTROL BITS
DB21 DB20
DON'T CARE COUNTER DIVIDE RATIO
COUNTER DIVIDE RATIO ALLOWED ALLOWED ALLOWED 8188 8189 8190 8191
(FUNCTION LATCH) FASTLOCK ENABLE*
GAIN
OPERATION CHARGE PUMP CURRENT SETTTING PERMANENTLY USED CHARGE PUMP CURRENT SETTING PERMANENTLY USED CHARGE PUMP CURRENT SETTING USED CHARGE PUMP CURRENT SWITCHED SETTING TIME SPENT SETTING DEPENDENT UPON WHICH FASTLOCK MODE USED. FUNCTION LATCH DESCRIPTION
*SEE TABLE
PRESCALER VALUE FUNCTION LATCH MUST GREATER THAN EQUAL CONTINUOUSLY ADJACENT VALUES FREF), OUTPUT, NMIN (P2-P).
THESE BITS USED DEVICE DON'T CARE BITS
-14-
REV.
ADF4110/ADF4111/ADF4112/ADF4113
Table Function Latch
FASTLOCK MODE
FASTLOCK ENABLE
POLARITY
PRESCALER VALUE DB23 DB22
CURRENT SETTTING DB19 DB18 CPI5 CPI4
CURRENT SETTTING DB17 DB16 CPI3 CPI2
COUNTER RESET
POWERDOWN
POWERDOWN
THREESTATE
TIMER COUNTER CONTROL DB13 DB12
MUXOUT CONTROL
CONTROL BITS
DB21 DB20 CPI6
DB15 DB14 CPI1
DB11 DB10
POLARITY NEGATIVE POSITIVE
COUNTER OPERATION NORMAL COUNTERS HELD RESET
CHARGE PUMP OUTPUT NORMAL THREE-STATE
FASTLOCK MODE FASTLOCK DISABLED FASTLOCK MODE FASTLOCK MODE2
CPI6 CPI3 CPI5 CPI2 CPI4 CPI1 MODE ASYNCHRONOUS POWER-DOWN NORMAL OPERATION ASYNCHRONOUS POWER-DOWN SYNCHRONOUS POWER-DOWN 2.7k 1.09 2.18 3.26 4.35 5.44 6.53 7.62 8.70
(mA) 4.7k 0.63 1.25 1.88 2.50 3.13 3.75 4.38 5.00 0.29 0.59 0.88 1.76 1.47 1.76 2.06 2.35
TIMEOUT (PFD CYCLES) ANALOG LOCK DETECT (N-CHANNEL OPEN-DRAIN) SERIAL DATA OUTPUT DGND OUTPUT THREE-STATE OUTPUT DIGITAL LOCK DETECT (ACTIVE HIGH) DIVIDER OUTPUT DVDD DIVIDER OUTPUT
PAGE
PRESCALER VALUE 16/17 32/33 64/65
REV.
-15-
ADF4110/ADF4111/ADF4112/ADF4113
Table Initialization Latch
FASTLOCK MODE
FASTLOCK ENABLE
POLARITY
PRESCALER VALUE DB23 DB22
CURRENT SETTTING DB19 DB18 CPI5 CPI4
CURRENT SETTTING DB17 DB16 CPI3 CPI2
COUNTER RESET
POWERDOWN
POWERDOWN
THREESTATE
TIMER COUNTER CONTROL DB13 DB12
MUXOUT CONTROL
CONTROL BITS
DB21 DB20 CPI6
DB15 DB14 CPI1
DB11 DB10
POLARITY NEGATIVE POSITIVE
COUNTER OPERATION NORMAL COUNTERS HELD RESET
CHARGE PUMP OUTPUT NORMAL THREE-STATE
FASTLOCK MODE FASTLOCK DISABLED FASTLOCK MODE FASTLOCK MODE2 TIMEOUT (PFD CYCLES) DVDD DIVIDER OUTPUT ANALOG LOCK DETECT (N-CHANNEL OPEN-DRAIN) SERIAL DATA OUTPUT DGND DIGITAL LOCK DETECT (ACTIVE HIGH) DIVIDER OUTPUT OUTPUT THREE-STATE OUTPUT
CPI6 CPI3 CPI5 CPI2 CPI4 CPI1 MODE ASYNCHRONOUS POWERDOWN NORMAL OPERATION ASYNCHRONOUS POWERDOWN SYNCHRONOUS POWER-DOWN 2.7k 1.09 2.18 3.27 4.35 5.44 6.53 7.62 8.70
(mA) 4.7k 0.63 1.25 1.88 2.50 3.13 3.75 4.38 5.00 0.29 0.59 0.88 1.76 1.47 1.76 2.06 2.35
PAGE
PRESCALER VALUE 16/17 32/33 64/65
-16-
REV.
ADF4110/ADF4111/ADF4112/ADF4113
FUNCTION LATCH Fastlock Mode
With on-chip function latch will programmed. Table shows input data format programming Function Latch.
Counter Reset
charge pump current switched contents Current Setting device enters Fastlock having written Gain counter latch. device exits Fastlock under control Timer Counter. After timeout period determined value TC4-TC1, Gain counter latch automatically reset device reverts normal mode instead Fastlock. Table timeout periods.
Timer Counter Control
(F1) counter reset bit. When this "1," counter counters reset. normal operation this should "0." Upon powering needs disabled, counter resumes counting "close" alignment with counter. (The maximum error prescaler cycle.)
Power-Down
(PD1) DB21 (PD2) ADF4110 family, provide programmable power-down modes. They enabled pin. When low, device immediately disabled regardless states PD2, PD1. programmed asynchronous power-down, device powers down immediately after latching into PD1, with condition that been loaded with "0." programmed synchronous power-down, device powerdown gated charge pump prevent unwanted frequency jumps. Once power-down enabled writing into condition that also been loaded PD2), device will into power-down occurrence next charge pump event. When power-down activated (either synchronous asynchronous mode including CE-pin-activated power-down), following events occur: active current paths removed. timeout counters forced their load state conditions. charge pump forced into three-state mode. digital clock detect circuitry reset. RFIN input debiased. reference input buffer circuitry disabled. input register remains active capable loading latching data.
MUXOUT Control
user option programming charge pump currents. intent that Current Setting used when output stable system static state. Current Setting meant used when system dynamic state change (i.e., when output frequency programmed). normal sequence events follows: user initially decides what preferred charge pump currents going example, they choose Current Setting Current Setting same time, they must also decide long they want secondary current stay active before reverting primary current. This controlled Timer Counter Control Bits DB14 DB11 (TC4-TC1) Function Latch. truth table given Table When user wishes program output frequency, simply program counter latch with values same time, Gain "1," which sets charge pump with value CPI6-CPI4 period time determined TC4-TC1. When this time charge pump current reverts value CPI3- CPI1. same time Gain Counter latch reset ready next time user wishes change frequency again. Note that there enable feature Timer Counter. enabled when Fastlock Mode chosen setting Fastlock Mode (DB10) Function Latch "1."
Charge Pump Currents
on-chip multiplexer controlled ADF4110 family. Table shows truth table.
Fastlock Enable
CPI3, CPI2, CPI1 program Current Setting charge pump. CPI6, CPI5, CPI4 program Current Setting charge pump. truth table given Table
Prescaler Value
Function Latch Fastlock Enable Bit. Only when this Fastlock enabled.
Fastlock Mode
DB10 Function Latch Fastlock Enable bit. When Fastlock enabled, this determines which Fastlock Mode used. Fastlock Mode then Fastlock Mode selected Fastlock Mode "1," then Fastlock Mode selected.
Fastlock Mode
Function Latch prescaler values. prescaler value should chosen that prescaler output frequency always less than equal MHz. Thus, with frequency GHz, prescaler value 16/17 valid value not.
Polarity
This sets Polarity Bit. Table
Three-State
charge pump current switched contents Current Setting device enters Fastlock having written Gain counter latch. device exits Fastlock having written Gain counter latch. REV.
This output pin. With high, output into three-state. With low, output enabled.
-17-
ADF4110/ADF4111/ADF4112/ADF4113
INITIALIZATION LATCH
When Initialization Latch programmed. This essentially same Function Latch (programmed when However, when Initialization Latch programmed additional internal reset pulse applied counters. This pulse ensures that counter load point when counter data latched device will begin counting close phase alignment. Latch programmed synchronous power-down High; High; Low), internal pulse also triggers this power-down. prescaler reference oscillator input buffer unaffected internal reset pulse close phase alignment maintained when counting resumes. When first counter data latched after initialization, internal reset pulse again activated. However, successive counter loads after this will trigger internal reset pulse.
DEVICE PROGRAMMING AFTER INITIAL POWER-UP
used power device down order check channel activity. input register does need reprogrammed each time device disabled enabled long been programmed least once after initially applied.
Counter Reset Method
Apply VDD. Function Latch Load ("10" LSBs). part this, load bit. This enables counter reset. Counter Load ("00" LSBs) Counter Load ("01" LSBs). Function Latch Load ("10" LSBs). part this, load bit. This disables counter reset. This sequence provides same close alignment initialization method. offers direct control over internal reset. Note that counter reset holds counters load point threestates charge pump, does trigger synchronous powerdown. counter reset method requires extra function latch load compared initialization latch method.
RESYNCHRONIZING PRESCALER OUTPUT
After initially powering device, there three ways program device.
Initialization Latch Method
Apply VDD. Program Initialization Latch ("11" LSBs input word). Make sure that programmed "0." Then load ("00" LSBs). Then load ("01" LSBs). When Initialization Latch loaded, following occurs: function latch contents loaded. internal pulse resets timeout counters load state conditions also three-states charge pump. Note that prescaler bandgap reference oscillator input buffer unaffected internal reset pulse, allowing close phase alignment when counting resumes. Latching first counter data after initialization word will activate same internal reset pulse. Successive loads will trigger internal reset pulse unless there another initialization.
Method
Table (the Reference Counter Latch Map) shows bits, DB22 DB21 that labelled SYNC respectively. These bits affect operation prescaler. With SYNC "1," prescaler output resynchronized with input. This effect reducing jitter prescaler lead overall improvement synthesizer phase noise performance. Typically, improvement seen ADF4113. lower bandwidth devices show even greater improvement. example, ADF4110 phase noise typically improved when SYNC enabled. With "1," prescaler output resynchronized with delayed version input. SYNC feature used synthesizer, some care must taken. some point, certain temperatures output frequencies), delay through prescaler will coincide with active edge input this will cause SYNC feature break down. important when using SYNC feature aware this. Adding delay signal, programming "1," will extend operating frequency temperature somewhat. Using SYNC feature will also increase value AIDD device. With output, ADF4113 AIDD increases about when SYNC enabled further enabled. typical performance plots data sheet except Figure apply SYNC "0," i.e., resynchronization delay enabled.
Apply VDD. Bring device into power-down. This asynchronous power-down that happens immediately. Program Function Latch (10). Program Counter Latch (00). Program Counter Latch (01). Bring high take device power-down. counters will resume counting close alignment. Note that after goes high, duration required prescaler bandgap voltage oscillator input buffer bias reach steady state.
-18-
REV.
ADF4110/ADF4111/ADF4112/ADF4113
APPLICATIONS SECTION Local Oscillator Base Station Transmitter
following diagram shows ADF4111/ADF4112/ADF4113 being used with produce base station transmitter. reference input signal applied circuit FREFIN and, this case, terminated Typical system would have TCXO driving Reference Input without termination. order have channel spacing (the standard), reference input must divided using on-chip reference divider ADF4111/ADF4112/ADF4113. charge pump output ADF4111/ADF4112/ADF4113 (Pin drives loop filter. calculating loop filter component values, number items need considered. this example, loop filter designed that overall phase margin system would degrees. Other system specifications are:
MHz/V Loop Bandwidth FREF 4500 Extra Reference Spur Attenuation these specifications needed used come with loop filter components values shown Figure loop filter output drives VCO, which, turn, back input synthesizer also drives Output terminal. T-circuit configuration provides matching between output, output RFIN terminal synthesizer. system, important know when system lock. Figure this accomplished using MUXOUT signal from synthesizer. MUXOUT programmed monitor various internal signals synthesizer. these lock-detect signal.
100pF
RFOUT
1000pF 1000pF FREFIN
AVDD DVDD REFIN 3.3k 5.6k 8.2nF 620pF
VCO190-902T 100pF
ADF4111 ADF4112 ADF4113
LOCK DETECT DATA MUXOUT 100pF RFINA RSET RFINB
CPGND AGND DGND
COMPATIBLE SERIAL
4.7k
100pF
DECOUPLING CAPACITORS AVDD, DVDD, ADF411X POSITIVE SUPPLY VCO190-902T HAVE BEEN OMITTED FROM DIAGRAM CLARITY.
Figure Local Oscillator Base Station
REV.
-19-
ADF4110/ADF4111/ADF4112/ADF4113
RFOUT 100pF
FREFIN
REFIN RSET
LOOP FILTER
100pF INPUT OUTPUT
DATA RSET 2.7k
ADF4111 ADF4112 ADF4113
MUXOUT LOCK DETECT
RFINA RFINB
100pF 100pF
AD5320 12-BIT V-OUT
POWER SUPPLY CONNECTIONS DECOUPLING CAPACITORS OMITTED CLARITY.
COMPATIBLE SERIAL
Figure Driving RSET with Converter
USING CONVERTER DRIVE
converter drive RSET ADF4110 family thus increase level control over charge pump current ICP. This advantageous wideband applications where sensitivity varies over tuning range. compensate this, varied maintain good phase margin ensure loop stability. Figure
SHUTDOWN CIRCUIT
wide band applications where local oscillator could have octave tuning range. example, cable tuners have total range about MHz. Figure shows application where ADF4113 used control program Micronetics M3500-2235. loop filter designed output 2900 MHz, loop bandwidth kHz, frequency MHz, (2.5 synthesizer multiplied gain factor MHz/V (sensitivity M3500-2235 output 2900 MHz) phase margin 45°C. narrow-band applications, there generally small variation output frequency (generally less than 10%) also small variation sensitivity over range (typically 15%). However, wide band applications both these parameters have much greater variation. Figure example, have -25% +17% variation output from nominal GHz. sensitivity vary from MHz/V 2750 MHz/V 3400 (+33%, -17%). Variations these parameters will change loop bandwidth. This turn affect stability lock time. changing programmable ICP, possible compensation these varying loop conditions ensure that loop always operating close optimal conditions.
attached circuit Figure shows shut down both ADF4110 family accompanying VCO. ADG701 switch goes closed circuit when Logic applied input. low-cost switch available both SOT-23 micro packages.
WIDEBAND
Many wireless applications synthesizers VCOs PLLs narrowband nature. These applications include various wireless standards like GSM, DSC1800, CDMA WCDMA. each these cases, total tuning range local oscillator less than MHz. However, there also
-20-
REV.
ADF4110/ADF4111/ADF4112/ADF4113
POWER-DOWN CONTROL
RFOUT 100pF
ADG701
AVDD DVDD FREFIN REFIN RSET
LOOP FILTER
100pF
ADF4110 ADF4111 ADF4112 ADF4113
RFINA
4.7k
100pF
CPGND
RFINB
AGND
DGND
100pF
DECOUPLING CAPACITORS INTERFACE SIGNALS HAVE BEEN OMITTED FROM DIAGRAM CLARITY.
Figure Local Oscillator Shutdown Circuit
AVDD DVDD REFIN RSET 2.8nF 4.7k 3.3k 19nF 130pF AD820 V_TUNE RFOUT 100pF 100pF
1000pF 1000pF FREFIN
M3500-2235
ADF4113
DATA
MUXOUT
LOCK DETECT
SPI-COMPATIBLE SERIAL
RFINA
CPGND
100pF
RFINB
AGND DGND
100pF
DECOUPLING CAPACITORS AVDD, DVDD, ADF4113 M3500-2250 HAVE BEEN OMITTED FROM DIAGRAM CLARITY.
Figure Wideband Phase Locked Loop
REV.
-21-
ADF4110/ADF4111/ADF4112/ADF4113
DIRECT CONVERSION MODULATOR
some applications direct conversion architecture used base station transmitters. Figure shows combination available from implement this solution. circuit diagram shows AD9761 being used with AD8346. dual integrated DACs such AD9761 with specified 0.02 0.004 gain offset matching characteristics ensures minimum error contribution (over temperature) from this portion signal chain. Local Oscillator (LO) implemented using ADF4113. this case, 3B1-13M0 provides stable reference frequency. system designed channel spacing output center frequency 1960 MHz.
target application WCDMA base station transmitter. Typical phase noise performance from this dBc/Hz offset. port AD8346 driven single-ended fashion. LOIN ac-coupled ground with capacitor LOIP driven through coupling capacitor from source. drive level between required. circuit Figure gives typical level dBm. output designed drive load must ac-coupled shown Figure inputs driven quadrature signals, resulting output power will around dBm.
REFIO
IOUTA IOUTB
LOW-PASS FILTER
IBBP IBBN VOUT
100pF RFOUT
MODULATED DIGITAL DATA
AD9761 TxDAC
QOUTA 4.7k QOUTB LOW-PASS FILTER QBBP QBBN
AD8346
LOIN 100pF
LOIP 100pF
3B1-13M0 RSET TCXO REFIN 910pF 3.9k 620pF 9.1nF RFINB 100pF RFINA 100pF VCO190-1960T 3.3k 100pF
SERIAL DIGITAL NTERFACE
ADF4113
POWER SUPPLY CONNECTIONS DECOUPLING CAPACITORS OMITTED FROM DIAGRAM CLARITY.
Figure Direct Conversion Transmitter Solution
-22-
REV.
ADF4110/ADF4111/ADF4112/ADF4113
INTERFACING ADSP-2181 Interface
ADF4110 family simple SPI-compatible serial interface writing device. SCLK, SDATA control data transfer. When (Latch Enable) goes high, bits which have been clocked into input register each rising edge SCLK will transferred appropriate latch. Figure Timing Diagram Table Latch Truth Table. maximum allowable serial clock rate MHz. This means that maximum update rate possible device update every microseconds. This certainly more than adequate systems that will have typical lock times hundreds microseconds.
ADuC812 Interface
Figure shows interface between ADF4110 family ADSP-21xx Digital Signal Processor. ADF4110 family needs 24-bit serial word each latch write. easiest accomplish this using ADSP-21xx family Autobuffered Transmit Mode operation with Alternate Framing. This provides means transmitting entire block serial data before interrupt generated.
SCLK SCLK SDATA
ADSP-21xx
ADF4110 ADF4111 ADF4112 ADF4113
Figure shows interface between ADF4110 family ADuC812 microconverter. Since ADuC812 based 8051 core, this interface used with 8051-based microcontroller. microconverter Master Mode with CPHA initiate operation, port driving brought low. Each latch ADF4110 family needs 24-bit word. This accomplished writing three 8-bit bytes from microconverter device. When third byte been written input should brought high complete transfer. first applying power ADF4110 family, needs three writes (one each counter latch, counter latch initialization latch) output become active. port lines ADuC812 also used control powerdown input) detect lock (MUXOUT configured lock detect polled port input). When operating mode described, maximum SCLOCK rate ADuC812 MHz. This means that maximum rate which output frequency changed will kHz.
SCLOCK SCLK SDATA PORTS
FLAGS
MUXOUT (LOCK DETECT)
Figure ADSP-21xx ADF4110 Family Interface
word length bits three memory locations each 24-bit word. program each 24-bit latch, store three 8-bit bytes, enable Autobuffered mode then write transmit register DSP. This last operation initiates autobuffer transfer.
ADuC812
MOSI
ADF4110 ADF4111 ADF4112 ADF4113
MUXOUT (LOCK DETECT)
Figure ADuC812 ADF4110 Family Interface
REV.
-23-
ADF4110/ADF4111/ADF4112/ADF4113
OUTLINE DIMENSIONS
Dimensions shown inches (mm).
Chip Scale (CP-20)
0.159 (4.05) 0.157 (4.00) 0.156 (3.95) 0.079 (2.0) 0.018 (0.45) 0.016 (0.40) 0.014 (0.35) DETAIL 0.020 (0.5) LEAD PITCH 0.014 (0.35)
0.159 (4.05) 0.157 (4.00) 0.156 (3.95)
VIEW
0.079 (2.0)
0.039 (1.00) 0.035 (0.90) 0.031 (0.80) SEATING 0.0079 (0.20) PLANE
0.0083 (0.211) 0.0079 (0.200) 0.0077 (0.195)
BOTTOM VIEW (ROTATED
LEAD OPTION DETAIL
0.011 (0.275) 0.010 (0.250) 0.009 (0.225) 0.018 (0.45) 0.016 (0.40) 0.014 (0.35) 0.0059 (0.15)
0.0059 (0.15) CONTROLLING DIMENSIONS MILLIMETERS
Thin Shrink Small Outline (RU-16)
0.201 (5.10) 0.193 (4.90)
0.177 (4.50) 0.169 (4.30) 0.256 (6.50) 0.246 (6.25)
0.006 (0.15) 0.002 (0.05) 0.0433 (1.10)
SEATING PLANE
0.0256 (0.65)
0.0118 (0.30) 0.0075 (0.19)
-24-
REV.
PRINTED U.S.A.
0.0079 (0.20) 0.0035 (0.090)
0.028 (0.70) 0.020 (0.50)
C3766-5-4/00 (rev.

FEATURES ADF4110: ADF4111: ADF4112: ADF4113: Power Supply Separate Cha

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