VINA VINB Complete 12-Bit, MSPS Converter AD9226 FUNCTIONAL

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VINA VINB Complete 12-Bit, MSPS Converter AD9226 FUNCTIONAL

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FEATURES Signal-to-Noise Ratio: Spurious-Free Dynamic Range: Intermodulation Distortion dBFS ENOB 11.1 Low-Power Dissipation: Missing Codes Guaranteed Differential Nonlinearity Error: Integral Nonlinearity Error: Clock Duty Cycle Stabilizer Patented On-Chip Sample-and-Hold with Full Power Bandwidth Straight Binary Two's Complement Output Data 28-Lead SSOP, 48-Lead LQFP Single Analog Supply, Driver Supply Pin-Compatible AD9220, AD9221, AD9223, AD9224, AD9225
VINA VINB
Complete 12-Bit, MSPS Converter AD9226
FUNCTIONAL BLOCK DIAGRAM
AVDD DRVDD DUTY CYCLE STABILIZER MDAC1 CAPT CAPB VREF SENSE SELECT MODE SELECT MODE AVSS CALIBRATION CORRECTION LOGIC OUTPUT BUFFERS 8-STAGE 1-1/2-BIT PIPELINE
AD9226
DRVSS
(MSB) (LSB)
REFCOM
PRODUCT DESCRIPTION
AD9226 monolithic, single-supply, 12-bit, MSPS analog-to-digital converter with on-chip, high-performance sample-and-hold amplifier voltage reference. AD9226 uses multistage differential pipelined architecture with patented input stage output error correction logic provide 12-bit accuracy MSPS data rates. There missing codes over full operating temperature range (guaranteed). input AD9226 allows easy interfacing both imaging communications systems. With truly differential input structure, user select variety input ranges offsets including single-ended applications. sample-and-hold amplifier (SHA) well suited undersampling schemes such single-channel communication applications with input frequencies well beyond Nyquist frequencies. AD9226 on-board programmable reference. system design flexibility, external reference also chosen. single clock input used control internal conversion cycles. out-of-range signal indicates overflow condition that used with most significant determine high overflow.
AD9226 important mode functions. will data format binary two's complement. second will make immune clock duty cycle variations.
PRODUCT HIGHLIGHTS
Sampling-The patented input configured either single-ended differential inputs. will maintain outstanding performance input frequencies MHz. Power-The AD9226 consumes fraction power presently available existing, high-speed monolithic solutions. Range (OTR)-The output indicates when input signal beyond AD9226's input range. Single Supply-The AD9226 uses single power supply simplifying system power supply design. also features separate digital output driver supply line accommodate logic families. Compatibility-The AD9226 similar AD9220, AD9221, AD9223, AD9224, AD9225 ADCs. Clock Duty Cycle Stabilizer-Makes conversion immune varying clock pulsewidths.
REV.
Information furnished Analog Devices believed accurate reliable. However, responsibility assumed Analog Devices use, infringements patents other rights third parties which result from use. license granted implication otherwise under patent patent rights Analog Devices. Technology Way, P.O. 9106, Norwood, 02062-9106, U.S.A. Tel: 781/329-4700 World Wide Site: http://www.analog.com Fax: 781/326-8703 Analog Devices, Inc., 2000
AD9226-SPECIFICATIONS
SPECIFICATIONS noted.)
Parameter
RESOLUTION ACCURACY Integral Nonlinearity (INL) Differential Nonlinearity (DNL) Missing Codes Guaranteed Zero Error Gain Error TEMPERATURE DRIFT Zero Error Gain Error1 Gain Error2 POWER SUPPLY REJECTION AVDD 0.25 INPUT REFERRED NOISE VREF VREF ANALOG INPUT Input Span (VREF (VREF Input (VINA VINB) Range Input Capacitance INTERNAL VOLTAGE REFERENCE Output Voltage Mode) Output Voltage Tolerance Mode) Output Voltage (2.0 Mode) Output Voltage Tolerance (2.0 Mode) Output Current (Available External Loads) Load Regulation3 REFERENCE INPUT RESISTANCE POWER SUPPLIES Supply Voltages AVDD DRVDD Supply Current IAVDD4 IDRVDD5 POWER CONSUMPTION
(AVDD DRVDD fSAMPLE MSPS, VREF Differential inputs, TMIN TMAX unless otherwise
Temp Test Level Full 25°C Full 25°C Full Full 25°C 25°C Full Full Full Full Full 25°C Full Full Full Full Full Full Full 25°C Full 25°C Full Full 25°C Full 0.05 Unit Bits Bits ppm/°C ppm/°C ppm/°C
0.25 AVDD
Full Full Full 25°C Full 25°C Full 25°C
4.75 2.85
5.25 5.25
AVDD Operating) DRVDD Operating) External VREF) External VREF) External VREF) External VREF) External VREF)
90.5 14.6 16.5
NOTES Includes internal voltage reference error. Excludes internal voltage reference error. Load regulation with load current addition that required AD9226). AVDD DRVDD Specifications subject change without notice.
REV.
AD9226 DIGITAL SPECIFICATIONS (AVDD DRVDD
Parameters LOGIC INPUTS (Clock, Duty Cycle Output Enable1) High-Level Input Voltage Low-Level Input Voltage High-Level Input Current (VIN AVDD) Low-Level Input Current (VIN Input Capacitance Output Enable1 LOGIC OUTPUTS (With DRVDD High-Level Output Voltage (IOH High-Level Output Voltage (IOH Low-Level Output Voltage (IOL Low-Level Output Voltage (IOL Output Capacitance LOGIC OUTPUTS (With DRVDD High-Level Output Voltage (IOH High-Level Output Voltage (IOH Low-Level Output Voltage (IOL Low-Level Output Voltage (IOL
NOTES LQFP package. Specifications subject change without notice.
SAMPLE
MSPS, VREF TMIN TMAX, unless otherwise noted.)
Unit
Temp
Test Level
Full Full Full Full Full Full
DRVDD DRVDD
Full Full Full Full
Full Full Full Full
2.95 2.80 0.05
SWITCHING SPECIFICATIONS
Parameters Conversion Rate Clock Period1 CLOCK Pulsewidth High2 CLOCK Pulsewidth Low2 Output Delay Pipeline Delay (Latency) Output Enable Delay3
(TMIN TMAX with AVDD DRVDD
Temp Full Full Full Full Full Full Full Test Level 15.38 Unit Clock Cycles
NOTES clock period extended without degradation specified performance 25°C. When MODE tied AVDD grounded, AD9226 SSOP affected clock duty cycle. LQFP package. Specifications subject change without notice.
ANALOG INPUT
CLOCK
DATA
Figure Timing Diagram
REV.
AD9226-SPECIFICATIONS
SPECIFICATIONS
Parameter SIGNAL-TO-NOISE RATIO MHz1 SIGNAL-TO-NOISE RATIO DISTORTION MHz1 TOTAL HARMONIC DISTORTION MHz1 SECOND THIRD HARMONIC DISTORTION MHz1 SPURIOUS FREE DYNAMIC RANGE MHz1 ANALOG INPUT BANDWIDTH
NOTES Reference Input Span Specifications subject change without notice.
(AVDD DRVDD fSAMPLE MSPS, VREF TMIN TMAX, Differential Input unless otherwise noted.)
Temp Full
25°C
Test Level
68.9
Unit
68.4 67.4 68.8 67.9 68.3 67.3 -77.0 -82.3 -76.0 -86.5 -86.7 86.4 85.5
Full
25°C
Full Full Full Full
25°C
Full
25°C
Full Full Full Full
25°C
Full
25°C
Full Full Full Full
25°C
Full
25°C
Full Full Full Full
25°C
Full
25°C
Full Full Full 25°C
REV.
AD9226
EXPLANATION TEST LEVELS Test Level ABSOLUTE MAXIMUM RATINGS
100% production tested.
Name
With Respect
-0.3 -0.3 -0.3 -6.5 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3
+6.5 +6.5 +0.3 +6.5 +0.3 AVDD DRVDD AVDD AVDD AVDD AVDD DRVDD AVDD AVDD +150
Unit
100% production tested 25°C sample tested specified temperatures. testing done sample basis. III. Sample tested only. Parameter guaranteed design characterization testing. Parameter typical value only. devices 100% production tested 25°C; sample tested temperature extremes.
AVDD AVSS DRVDD DRVSS AVSS DRVSS AVDD DRVDD REFCOM AVSS CLK, MODE AVSS Digital Outputs DRVSS VINA, VINB AVSS VREF AVSS SENSE AVSS CAPB, CAPT AVSS OEB2 DRVSS LEVEL2 AVSS AVSS Junction Temperature Storage Temperature Lead Temperature sec)
NOTES Stresses above those listed under Absolute Maximum Ratings cause permanent damage device. This stress rating only; functional operation device these other conditions above those indicated operational sections this specification implied. Exposure absolute maximum ratings extended periods affect device reliability. LQFP package.
THERMAL RESISTANCE
SSOP SSOP LQFP LQFP
23°C/W 63.3°C/W 17°C/W 76.2°C/W
ORDERING GUIDE
Model AD9226ARS AD9226AST AD9226-EB AD9226-LQFP-EB
Temperature Range -40°C +85°C -40°C +85°C
Package Description 28-Lead Shrink Small Outline (SSOP) 48-Lead Thin Plastic Quad Flatpack (LQFP) Evaluation Board (SSOP) Evaluation Board (LQFP)
Package Option RS-28 ST-48
CAUTION (electrostatic discharge) sensitive device. Electrostatic charges high 4000 readily accumulate human body test equipment discharge without detection. Although AD9226 features proprietary protection circuitry, permanent damage occur devices subjected high-energy electrostatic discharges. Therefore, proper precautions recommended avoid performance degradation loss functionality.
WARNING!
SENSITIVE DEVICE
REV.
AD9226
CONNECTION 48-Lead LQFP
MODE1 CAPT CAPT CAPB CAPB (AVSS)
CONNECTION 28-Lead SSOP
(LSB) VREF
DRVDD DRVSS AVDD AVSS VINB VINA
VINB VINA LEVEL
AVSS AVSS AVDD AVDD
IDENTIFIER
SENSE
AD9226
(LSB) CONNECT
AD9226
VIEW (Not Scale)
MODE2 AVDD AVSS AVSS
VIEW MODE (Not Scale) CAPT
CAPB REFCOM (AVSS) VREF SENSE AVSS AVDD
(MSB)
AVDD DRVSS
DRVDD (MSB)
DRVSS DRVDD
DRVDD
DRVSS
48-PIN FUNCTION DESCRIPTIONS
28-PIN FUNCTION DESCRIPTIONS
Number 16-21, 24-26
Name AVSS AVDD DRVSS DRVDD BITS 10-5, BITS MODE2 SENSE VREF REFCOM (AVSS) CAPB CAPT MODE1 LEVEL VINA VINB
Description Analog Ground Analog Supply Connect Clock Input Output Enable (Active Low) Least Significant Data (LSB) Data Output Digital Output Driver Ground Digital Output Driver Supply Data Output Bits Most Significant Data (MSB) Range Data Format Select Reference Select Reference In/Out Reference Common Noise Reduction Noise Reduction Clock Stabilizer Midsupply Reference Analog Input Analog Input Noise Reduction
Number 3-12
Name BITS 11-2 AVDD AVSS SENSE VREF REFCOM (AVSS) CAPB CAPT MODE VINA VINB DRVSS DRVDD
Description Clock Input Least Significant Data (LSB) Data Output Bits Most Significant Data (MSB) Range Analog Supply Analog Ground Reference Select Input Span Select (Reference I/O) Reference Common Noise Reduction Noise Reduction Data Format Select /Clock Stabilizer Analog Input Analog Input Digital Output Driver Ground Digital Output Driver Supply
REV.
AD9226
DEFINITIONS SPECIFICATIONS INTEGRAL NONLINEARITY (INL) EFFECTIVE NUMBER BITS (ENOB)
refers deviation each individual code from line drawn from "negative full scale" through "positive full scale." point used "negative full scale" occurs before first code transition. "Positive full scale" defined level beyond last code transition. deviation measured from middle each particular code true straight line.
DIFFERENTIAL NONLINEARITY (DNL, MISSING CODES)
sine wave, SINAD expressed terms number bits. Using following formula, (SINAD 1.76)/6.02 possible obtain measure performance expressed effective number bits. Thus, effective number bits device sine wave inputs given input frequency calculated directly from measured SINAD.
TOTAL HARMONIC DISTORTION (THD)
ideal exhibits code transitions that exactly apart. deviation from this ideal value. Guaranteed missing codes 12-bit resolution indicates that 4096 codes, respectively, must present over operating ranges.
ZERO ERROR
ratio first harmonic components value measured input signal expressed percentage decibels.
SIGNAL-TO-NOISE RATIO (SNR)
major carry transition should occur analog value below VINA VINB. Zero error defined deviation actual transition from that point.
GAIN ERROR
ratio value measured input signal other spectral components below Nyquist frequency, excluding first harmonics value expressed decibels.
SPURIOUS FREE DYNAMIC RANGE (SFDR)
first code transition should occur analog value above negative full scale. last transition should occur analog value below positive full scale. Gain error deviation actual difference between first last code transitions ideal difference between first last code transitions.
TEMPERATURE DRIFT
SFDR difference between amplitude input signal peak spurious signal.
ENCODE PULSEWIDTH DUTY CYCLE
temperature drift zero error gain error specifies maximum change from initial (25°C) value value TMIN TMAX.
POWER SUPPLY REJECTION
Pulsewidth high minimum amount time that clock pulse should left logic state achieve rated performance; pulsewidth minimum time clock pulse should left state. given clock rate, these specs define acceptable clock duty cycle.
MINIMUM CONVERSION RATE
clock rate which lowest analog signal frequency drops more than below guaranteed limit.
MAXIMUM CONVERSION RATE
specification shows maximum change full scale from value with supply minimum limit value with supply maximum limit.
APERTURE JITTER
encode rate which parametric testing performed.
OUTPUT PROPAGATION DELAY
Aperture jitter variation aperture delay successive samples manifested noise input ADC.
APERTURE DELAY
delay between clock logic threshold time when bits within valid logic levels.
TONE SFDR
Aperture delay measure sample-and-hold amplifier (SHA) performance measured from rising edge clock input when input signal held conversion.
SIGNAL-TO-NOISE DISTORTION (S/N+D, SINAD) RATIO
ratio value either input tone value peak spurious component. peak spurious component product. reported (i.e., degrades signal levels lowered) dBFS (always related back converter full scale).
S/N+D ratio value measured input signal other spectral components below Nyquist frequency, including harmonics excluding value S/N+D expressed decibels.
REV.
AD9226
DRVDD DRVDD DRVDD AVDD
DRVSS DRVSS
AVSS
D0-D11,
Three-State (OEB)
AVDD AVDD
AVSS AVSS
CAPT, CAPB, MODE, SENSE, VREF Figure Equivalent Circuits
REV.
Typical Performance Characteristics-AD9226
(AVDD DRVDD fSAMPLE MSPS with Stabilizer Enabled, Differential Input Span, -0.5 dBFS, VREF unless otherwise noted.)
69.9dBc SINAD 69.8dBc ENOB 11.4BITS -86.4dBc SFDR 88.7dBc
SFDR dBFS
dBFS
SFDR dBFS
dBFS
-100 -110 -120 19.5 32.5
dBFS
FREQUENCY
Single-Tone with
Single-Tone SNR/SFDR with
70.4dBFS SFDR 87.5dBFS
SFDR dBFS SFDR
dBFS
dBFS
dBFS
-100 -110 -120 19.5 32.5
dBFS
FREQUENCY
Dual-Tone with fIN-1 fIN-2 (AIN-1 AIN-2 -6.5 dBFS)
Dual-Tone SNR/SFDR with fIN-1 fIN-2
69.5dBc SINAD 69.4dBc ENOB 11.3BITS -85dBc SFDR 87.6dBc
SFDR dBFS
dBFS
-100 -110 -120 19.5 32.5
dBFS
dBFS
SFDR
dBFS
FREQUENCY
Single-Tone with
Single-Tone SNR/SFDR with
REV.
AD9226
SPAN, DIFFERENTIAL SPAN, DIFFERENTIAL
SINAD
12.2
SPAN, DIFFERENTIAL
11.4
ENOB Bits
10.6
SPAN, SINGLE-ENDED SPAN, DIFFERENTIAL
SPAN, SINGLE-ENDED
SPAN, SINGLE-ENDED
SPAN, SINGLE-ENDED FREQUENCY
1000
FREQUENCY
1000
SINAD/ENOB Frequency
Frequency
SPAN, SINGLE-ENDED SPAN, SINGLE-ENDED
SPAN, DIFFERENTIAL
SFDR
SPAN, SINGLE-ENDED
SPAN, DIFFERENTIAL
SPAN, DIFFERENTIAL SPAN, DIFFERENTIAL
SPAN, SINGLE-ENDED
1000 FREQUENCY
FREQUENCY
1000
Frequency
SFDR Frequency
FREQUENCY
FREQUENCY 1000
Temperature Frequency
Temperature Frequency
-10-
REV.
AD9226
70.5
HARMONIC
70.25
2MHz
HARMONICS
SINAD
12MHz
69.75
HARMONIC
69.5 20MHz
HARMONIC
69.25
FREQUENCY 1000
SAMPLE RATE MSPS
Harmonics Frequency
SINAD Sample Rate
SFDR CLOCK STABILIZER
SINAD/SFDR
SFDR CLOCK STABILIZER SINAD CLOCK STABILIZER
2MHz
SFDR
12MHz
20MHz
SINAD CLOCK STABILIZER
SAMPLE RATE MSPS
POSITIVE DUTY CYCLE
SFDR Sample Rate
SINAD/SFDR Duty Cycle
70.5
70.25
2MHz
SINAD
69.75
12MHz
-0.2 -0.4
69.5 20MHz 69.25
-0.6 -0.8
SAMPLE RATE MSPS
1500
2500 CODE
3500
Typical
Typical
REV.
-11-
AD9226-Typical Sampling Performance Characteristics AD9226
(AVDD DRVDD fSAMPLE MSPS with Stabilizer Enabled, Differential Input Span, -6.5 dBFS, VREF unless otherwise noted.)
dBFS
SNR/SFDR dBFS
170.1
70.2dBFS SFDR 89dBFS NOISE FLOOR 145.33dBFS/Hz
SFDR SPAN
165.1
NOISE FLOOR dBFS/Hz
160.1
-100 -110 -120
155.1
SNR/NOISE FLOOR SPAN
150.1
145.1
dBFS
140.1
FREQUENCY
Dual-Tone with fIN-1 44.2 fIN-2 45.6
Dual-Tone SFDR with fIN-1 44.2 fIN-2 45.6
dBFS
165.1 SFDR SPAN
68.5dBFS SFDR 75dBFS NOISE FLOOR 143.6dBFS/Hz
160.1
NOISE FLOOR dBFS/Hz
SNR/SFDR dBFS
SFDR SPAN SNR/NOISE FLOOR SPAN
155.1
150.1
145.1
-100 -110 -120
SNR/NOISE FLOOR SPAN dBFS
140.1
135.1
FREQUENCY
Dual-Tone with fIN-1 69.2 fIN-2 70.6
Dual-Tone SFDR with fIN-1 69.2 fIN-2 70.6
67.5dBFS SFDR 75dBFS NOISE FLOOR 142.6dBFS/Hz
SFDR SPAN
165.1
160.1 NOISE FLOOR dBFS/Hz
SNR/SFDR dBFS
dBFS
SFDR SPAN
155.1
-100 -110 -120
SNR/NOISE FLOOR SPAN SNR/NOISE FLOOR SPAN
150.1
145.1
140.1
dBFS
135.1
FREQUENCY
Dual-Tone with fIN-1 139.2 fIN-2 140.7
Dual-Tone SFDR with fIN-1 139.2 fIN-2 140.7
-12-
REV.
AD9226
SNR/SFDR dBFS
165.1 SFDR SPAN
190.82MHz fSAMPLE 61.44MSPS
160.1
NOISE FLOOR dBFS/Hz NOISE FLOOR dBFS/Hz
dBFS
SFDR SPAN SNR/NOISE FLOOR SPAN
155.1
-100 -110 -120 FREQUENCY
150.1
145.1
SNR/NOISE FLOOR SPAN dBFS
140.1
135.1
Single-Tone MHz-WCDMA (fIN 190.82 MHz, fSAMPLE 61.44 MSPS)
Single-Tone SFDR -WCDMA (fIN-1 190.8 MHz, fSAMPLE 61.44 MSPS)
65.1dBFS SFDR 59dBFS NOISE FLOOR 140.2dBFS/Hz
SFDR SPAN
160.1
155.1
SNR/SFDR dBFS
SNR/NOISE FLOOR SPAN
SFDR SPAN
150.1
dBFS
-100 -110 -120
145.1
SNR/NOISE FLOOR SPAN
140.1
135.1
FREQUENCY
dBFS
130.1
Dual-Tone with fIN-1 239.1 fIN-2 240.7
Dual-Tone SFDR with fIN-1 239.1 fIN-2 240.7
CMRR
INPUT SPAN
INPUT SPAN
FREQUENCY
1000
CMRR Frequency (AIN dBFS
REV.
-13-
AD9226
THEORY OPERATION
AD9226 high-performance, single-supply 12-bit ADC. analog input AD9226 very flexible allowing both single-ended differential inputs varying amplitudes that dc-coupled. utilizes nine-stage pipeline architecture with wideband, sample-and-hold amplifier (SHA) implemented costeffective CMOS process. patented structure used greatly improve high frequency SFDR/distortion. This also improves performance undersampling applications. Each stage pipeline, excluding last stage, consists resolution flash connected switched capacitor interstage residue amplifier (MDAC). residue amplifier amplifies difference between reconstructed output flash input next stage pipeline. redundancy used each stages facilitate digital correction flash errors. last stage simply consists flash ADC. Factory calibration ensures high linearity distortion.
ANALOG INPUT OPERATION
and/or shunt capacitor help limit wideband noise ADC's input forming low-pass filter. source impedance driving VINA VINB should matched. Failure provide matching will result degradation AD9226's SNR, THD, SFDR.
CPIN VINA VINB CPAR CPIN CPAR
Figure Equivalent Input Circuit
VINA 15pF VINB VREF SENSE REFCOM
AD9226
Figure shows equivalent analog input AD9226 which consists differential SHA. differential input structure highly flexible, allowing device easily configured either differential single-ended input. analog inputs, VINA VINB, interchangeable with exception that reversing inputs VINA VINB pins results data inversion (complementing output word). optimum noise linearity performance either differential single-ended inputs achieved with largest input signal voltage span (i.e., input span) matched input impedance VINA VINB. Only slight degradation linearity performance exists between input spans. High frequency inputs find span better suited achieve superior SFDR performance. (See Typical Performance Characteristics.) samples analog input rising edge clock input. During clock time (between falling edge rising edge clock), input sample mode; during clock high time hold. System disturbances just prior rising edge clock and/or excessive clock jitter rising edge cause input acquire wrong value should minimized. When driven capacitive load switched onto output amp, output will momentarily drop effective output impedance. output recovers, ringing occur. remedy situation, series resistor inserted between input shown Figure shunt capacitance also acts like charge reservoir, sinking sourcing additional charge required hold capacitor, further reducing current transients seen amp's output. optimum size this resistor dependent several factors, including sampling rate, selected amp, particular application. most applications, resistor sufficient. noise-sensitive applications, very high bandwidth AD9226 detrimental addition series resistor
Figure Series Resistor Isolates Switched-Capacitor Input from Amp; Matching Resistors Improve Performance
OVERVIEW INPUT REFERENCE CONNECTIONS
overall input span AD9226 equal potential VREF pin. VREF potential obtained from internal AD9226 reference external source (see Reference Operation section). differential applications, center point span obtained common-mode level signals. singleended applications, center point potential applied input while signal applied opposite input pin. Figures 5a-5f show various system configurations.
DRIVING ANALOG INPUTS
AD9226 very flexible input structure allowing interface with single-ended differential input interface circuitry. optimum mode operation, analog input range, associated interface circuitry will determined particular applications performance requirements well power supply options.
DIFFERENTIAL DRIVER CIRCUITS
Differential operation requires that VINA VINB simultaneously driven with equal signals that phase with each other. Differential modes operation (ac- dc-coupled input) provide best SFDR performance over wide frequency range. They should considered most demanding spectral-based applications (e.g., direct conversion digital). REV.
-14-
AD9226
1.5V 0.5V 15pF VREF
VINB
2.5V
AD9226
VINA CAPT
49.9
CMLEVEL 3.0V 2.5V 2.0V 15pF
VINB
AD9226 (LQFP)
VINA CAPT VREF CAPB
CAPB
3.0V 2.5V 2.0V
SENSE REFCOM
SENSE
Figure Single-Ended Input, Common-Mode Voltage
Figure Differential Input, Common-Mode Voltage
1.25V 0.75V 15pF 1.25V 0.75V
VINB
AD9226
VINA
49.9
CAPT
2.75V 2.5V 2.0V 2.5V
AVDD
AD9226
VINA
49.9
VREF
CAPB
15pF
VINB
CAPT VREF CAPB
SENSE
2.75V 2.5V 2.25V
Figure Differential Input, Common-Mode Voltage
SENSE
2.5V 1.5V
49.9
AD9226
VINA 15pF
VINB
Figure Differential Input, Common-Mode Voltage (Recommended Undersampling)
2.5V 1.5V
CAPT
differential input characterization this data sheet performed using configuration shown Figure Since applications have signal preconditioned differential operation, there often need perform singleended-to-differential conversion. systems that need dc-coupled, transformer with center best method generate differential inputs AD9226. provides benefits operating differential mode without contributing additional noise distortion. transformer also added benefit providing electrical isolation between signal source ADC. improvement SFDR performance realized operating AD9226 differential mode. performance enhancement between differential single-ended mode most noteworthy input frequency approaches goes beyond Nyquist frequency (i.e., /2). circuit shown Figure ideal method applying differential drive AD9226. uses AD8138 derive differential signal from single-ended one. Figure illustrates performance. Figure presents schematic suggested transformer circuit. circuit uses Minicircuits transformer, model T1-1T, which impedance ratio four (turns ratio schematic assumes that signal source source impedance. center transformer provides convenient means level-shifting input signal desired common-mode voltage. Figure transformer centertap connected resistor divider midsupply voltage. -15-
VREF CAPB SENSE
Figure Differential Input, Common-Mode Voltage
3.0V 1.0V 15pF VREF
VINB
AD9226
VINA CAPT CAPB
SENSE REFCOM
Figure Single-Ended Input, Common-Mode Voltage
REV.
AD9226
SINGLE-ENDED DRIVER CIRCUITS
AD8138 15pF CAPT
AD9226
CAPB
AD9226 configured single-ended operation using ac-coupling. either case, input must driven from operational amplifier that will degrade ADC's performance. Because operates from single supply, will necessary level-shift ground-based bipolar signals comply with input requirements. Both ac-coupling provide this necessary function, each method results different interface issues which influence system design performance. Single-ended operation requires that VINA dc-coupled input signal source, while VINB AD9226 biased appropriate voltage corresponding middle input span. single-ended specifications AD9226 characterized using Figure circuitry with input spans common-mode level analog inputs exceed supply limits, internal parasitic diodes will turn This will result transient currents within device. Figure shows simple means clamping input. uses series resistor diodes. optional capacitor shown ac-coupled applications. larger series resistor used limit fault current through This cause degradation overall performance. similar clamping circuit also used each input differential input signal being applied. better method ensure input overdriven amplifiers powered single supply such AD8138.
Figure Direct-Coupled Drive Circuit with AD8138 Differential
66.9dBc SFDR 70.0dBc
-100
-120
Figure MSPS, MHz, Input Span
OPTIONAL AC-COUPLING CAPACITOR
AVDD
same midsupply potential obtained from CMLEVEL AD9226 LQFP package. Referring Figure series resistor, inserted between AD9226 secondary transformer. value selected specifically optimize both performance ADC. internal capacitance help provide low-pass filter block high-frequency noise. Transformers with other turns ratios also selected optimize performance given application. example, given input signal source amplifier realize improvement distortion performance reduced output power levels signal swings. selecting transformer with higher impedance ratio (e.g., Minicircuits T16-6T with 1:16 impedance ratio), signal level effectively "stepped thus further reducing driving requirements signal source.
AVDD VINA CAPT 49.9 15pF
AD9226
Figure Simple Clamping Circuit
AC-COUPLING INTERFACE ISSUES
applications where ac-coupling appropriate, output easily level-shifted means coupling capacitor. This advantage allowing amp's common-mode level symmetrically biased midsupply level (i.e., (AVDD/2). amps that operate symmetrically with respect their power supplies typically provide best performance well greatest input/output span. Various highspeed performance amplifiers that restricted V/-5 operation and/or specified single-supply operation easily configured input span AD9226.
Simple Interface
AD9226
CAPB
MINICIRCUITS T1-1T
VINB
Figure Transformer-Coupled Input
Figure shows typical example ac-coupled, singleended configuration SSOP package. bias voltage shifts bipolar, ground-referenced input signal approximately AVDD/2. capacitors, ceramic tantalum capacitors parallel achieve cutoff frequency while maintaining impedance over wide frequency range. combination capacitor resistor form high-pass network with high-pass frequency determined equation, 1/(2 C2))
-16-
REV.
AD9226
low-impedance VREF output used provide bias levels fixed VINB signal VINA. Figure shows VREF configured thus input range Other input ranges could selected changing VREF. When inputs biased from reference (Figure 9b), there slight degeneration dynamic performance. midsupply output level available LEVEL LQFP package.
VINA CAPT 15pF VINB VREF
Figure illustrates relation between common-mode voltage THD. Note that optimal performance occurs when reference voltage (input span
DC-COUPLING INTERFACE ISSUES
Many applications require analog input signal dc-coupled AD9226. operational amplifier configured rescale level-shift input signal make compatible with selected input range ADC. selected input range AD9226 should considered with headroom requirements particular prevent clipping signal. Many high-performance amps specified only operation have limited input/output swing capabilities. Also, since output dual supply amplifier swing below absolute minimum (-0.3 clamping output should considered some applications (see Figure When single-ended, dc-coupling needed, AD8138 differential configuration (Figure highly recommended.
Simple Buffer
AD9226
CAPB
Figure AC-Coupled Input Configuration
simplest case, input signal AD9226 will already biased levels accordance with selected input range. necessary provide adequately source impedance VINA VINB analog pins ADC.
REFERENCE OPERATION
VINA
AD9226
CAPT 15pF CAPB
VINB VREF
AD9226 contains on-board bandgap reference that provides pin-strappable option generate either output. With addition external resistors, user generate reference voltages between Figures 5a-5f summary pin-strapping options AD9226 reference configurations. Another alternative external reference designs requiring enhanced accuracy and/or drift performance described later this section. Figure shows simplified model internal voltage reference AD9226. reference amplifier buffers fixed reference. output from reference amplifier, appears VREF pin. voltage VREF determines full-scale input span ADC. This input span equals, Full-Scale Input Span VREF voltage appearing VREF pin, state internal reference amplifier, determined voltage appearing SENSE pin. logic circuitry contains comparators that monitor voltage SENSE pin. SENSE tied AVSS, switch connected internal resistor network thus providing VREF SENSE tied VREF short resistor, switch will connect SENSE pin. This connection will provide VREF external resistor network will provide alternative VREF between (see Figure 12). Another comparator controls internal circuitry that will disable reference amplifier SENSE tied AVDD. Disabling reference amplifier allows VREF driven external voltage reference.
Figure Alternate AC-Coupled Input Configuration
volts
Figure Common-Mode Voltage Differential Input Span, MHz)
REV.
-17-
AD9226
AD9226
CAPT 2.5V CAPB
sets input span p-p. midscale voltage also VREF connecting VINB VREF. Alternatively, midscale voltage connecting VINB low-impedance source shown Figure
3.25V 1.75V 2.5V 15pF
VINB
AD9226
VINA CAPT VREF SENSE REFCOM CAPB
VREF
1.5V
2.5k
SENSE DISABLE LOGIC REFCOM
Figure Resistor Programmable Reference (1.5 Input Span, Differential Input
USING EXTERNAL REFERENCE
Figure 11a. Equivalent Reference Circuit
VREF CAPT
AD9226
CAPB
Figure 11b. CAPT CAPB DC-Coupling
AD9226 contains internal reference buffer, (see Figure 11b), that simplifies drive requirements external reference. external reference must able drive about 20%) load. Note that bandwidth reference buffer deliberately left small minimize reference noise contribution. result, possible rapidly change reference voltage this mode. Figure shows example external reference driving both VINB VREF. this case, both common-mode voltage input span directly dependent value VREF. Both input span center input span equal external VREF. Thus valid input range extends from (VREF VREF/2) (VREF VREF/2). example, REF191, 2.048 external reference, selected, input span extends 2.048 this case, AD9226 corresponds essential that minimum capacitor, parallel with low-inductance ceramic capacitor, decouple reference output ground. external reference, SENSE must connected AVDD. This connection will disable internal reference.
VINA+VREF/2 VINB-VREF/2 VREF
actual reference voltages used internal circuitry AD9226 appear CAPT CAPB pins. voltages these pins symmetrical about analog supply. proper operation when using internal external reference, necessary capacitor network decouple these pins. Figure shows recommended decoupling network. turn-on time reference voltage appearing between CAPT CAPB approximately should evaluated power-down mode operation.
USING INTERNAL REFERENCE
AD9226 easily configured either input span input span setting internal reference. Other input spans realized with external gainsetting resistors shown Figure this data sheet, using external reference.
Programmable Reference
15pF
AD9226
VINA
VINB
shorting VREF directly SENSE pin, internal reference amplifier placed unity-gain mode resultant VREF output shorting SENSE directly REFCOM pin, internal reference amplifier configured gain resultant VREF output VREF should bypassed REFCOM with tantalum capacitor parallel with low-inductance ceramic capacitor shown Figure 11b.
Resistor Programmable Reference
CAPT CAPB
VREF
SENSE
Figure Using External Reference
MODE CONTROLS Clock Stabilizer
Figure shows example generate reference voltage other than with addition external resistors. equation, VREF R1/R2) determine appropriate values These resistors should range. example shown, equals equals From equation above, resultant reference voltage VREF This
clock stabilizer circuit that desensitizes from clock duty cycle variations. AD9226 eases system clock constraints incorporating circuit that restores internal duty cycle 50%, independent input duty cycle. jitter rising edge (sampling edge) clock preserved while noncritical falling edge generated on-chip. desirable disable clock stabilizer, necessary when clock frequency speed varied completely
-18-
REV.
AD9226
stopped. Once clock frequency changed, over clock cycles required clock stabilizer settle different speed. When stabilizer disabled, internal switching will directly affected clock state. external clock high, will hold. clock pulse low, will track. shows benefits using clock stabilizer. Tables III.
Data Format Select (DFS) Table Output Data Format
Binary Output Mode
0000 0000 0000 0000 0000 0000 1000 0000 0000 1111 1111 1111 1111 1111 1111
Input
VINA-VINB VINA-VINB VINA-VINB VINA-VINB VINA-VINB
Condition
VREF VREF VREF VREF
Two's Complement Mode
1000 0000 0000 1000 0000 0000 0000 0000 0000 0111 1111 1111 0111 1111 1111
AD9226 binary two's complement data output formats. Tables
SSOP Package
Range (OTR)
SSOP mode control (Pin functions. enables/ disables clock stabilizer determines output data format. exact functions mode outlined Table
Table Mode Select (SSOP)
Mode AVDD Resistor
Binary Binary Two's Complement Two's Complement
Clock Duty Cycle Shaping Clock Stabilizer Disabled Clock Stabilizer Enabled Clock Stabilizer Enabled Clock Stabilizer Disabled
LQFP Package
LQFP package determines output data format (DFS). connected AVSS, output word will straight binary. connected AVDD, output data format will two's complement. Table LQFP package controls clock stabilizer function AD9226. connected AVDD, both clock edges will used conversion architecture. When connected AVSS, internal duty cycle will determined clock stabilizer function within ADC. Table III.
Table Controls
out-of-range condition exists when analog input voltage beyond input range converter. digital output that updated along with data output corresponding particular sampled analog input voltage. Hence, same pipeline delay (latency) digital data. when analog input voltage within analog input range. HIGH when analog input voltage exceeds input range shown Figure will remain HIGH until analog input returns within input range another conversion completed. logical ANDing with complement, overrange high underrange conditions detected. Table truth table over/underrange circuit Figure which uses NAND gates. Systems requiring programmable gain conditioning AD9226 input signal immediately detect out-of-range condition, thus eliminating gain selection iterations. Also, used digital offset gain calibration.
Table Out-of-Range Truth Table
DATA OUTPUTS 1111 1111 1111 1111 1111 1111 1111 1111 1110
Analog Input Range Range Underrange Overrange
Function Straight Binary Two's Complement
Connection AVDD AVSS
+1/2 0000 0000 0001 0000 0000 0000 0000 0000 0000
Table III. Clock Stabilizer
Clock Restore Function Clock Stabilizer Enabled Clock Stabilizer Disabled
Connection AVDD AVSS
Figure Relation Input Voltage Output DatMSB OVER
DIGITAL INPUTS OUTPUTS Digital Outputs
UNDER
Table details relationship among input, OTR, straight binary output.
Figure Overrange Underrange Logic
REV.
-19-
AD9226
Digital Output Driver Considerations
AD9226 output drivers configured interface with logic families setting DRVDD respectively. output drivers sized provide sufficient output current drive wide variety logic families. However, large drive currents tend cause glitches supplies affect converter performance. Applications requiring drive large capacitive loads large outs require external buffers latches.
Function (Three-State)
inherent distributed capacitor formed power plane, insulation, ground plane. important design layout that prevents noise from coupling onto input signal. Digital signals should parallel with input signal traces should routed away from input circuitry. While AD9226 features separate analog driver ground pins, should treated analog component. AVSS DRVSS pins must joined together directly under AD9226. solid ground plane under acceptable power ground return currents carefully managed.
LQFP-packaged AD9226 Three-State (OEB) ability. held low, output data drivers enabled. high, output data drivers placed high impedance state. intended rapid access buss.
Clock Input Considerations
AVDD
AD9226
AVSS
High-speed, high-resolution ADCs sensitive quality clock input. clock input should treated analog signal cases where aperture jitter affect dynamic performance AD9226. Power supplies clock drivers should separated from output driver supplies avoid modulating clock signal with digital noise. Low-jitter crystal controlled oscillators make best clock sources. quality clock input, particularly rising edge, critical realizing best possible jitter performance part. Faster rising edges often have less jitter.
Clock Input Power Dissipation
Figure Analog Supply Decoupling
Analog Digital Driver Supply Decoupling
Most power dissipated AD9226 from analog power supplies. However, lower clock speeds will reduce digital current. Figure shows relationship between power clock rate.
AD9226 features separate analog digital supply ground pins, helping minimize digital corruption sensitive analog signals. general, AVDD (analog power) should decoupled AVSS (analog ground). AVDD AVSS pins adjacent another. Also, DRVDD (digital power) should decoupled DRVDD (digital ground). decoupling capacitors (especially should located close pins possible. Figure shows recommended decoupling pair analog supplies; ceramic chip tantalum capacitors should provide adequately impedance over wide frequency range.
AD9226
POWER DISSIPATION
DRVDD DRVDD SAMPLE RATE Msps
Figure Decoupling (LQFP)
Bias Decoupling
analog bias points used internally AD9226. These pins must decoupled with least capacitor shown Figure level approximately AVDD/2. This voltage should buffered used external biasing. outputs only available LQFP package.
DRVDD
AD9226
DRVSS
Figure Power Consumption Sample Rate
GROUNDING DECOUPLING Analog Digital Grounding
Figure Digital Supply Decoupling
Proper grounding essential high-speed, high-resolution system. Multilayer printed circuit boards (PCBs) recommended provide optimal grounding power schemes. ground power planes offers distinct advantages: minimization loop area encompassed signal return path. minimization impedance associated with ground power paths.
LQFP-packaged AD9226 midsupply reference point. This midsupply point used within internal architecture AD9226 must decoupled with capacitor. will source sink load more current required, should buffered with high impedance amplifier.
-20-
REV.
AD9226
internal bias point LQFP package. must decoupled ground with capacitor. digital activity AD9226 chip falls into general categories: correction logic output drivers. internal correction logic draws relatively small surges current, mainly during clock transitions. output drivers draw large current impulses while output bits changing. size duration these currents function load output bits: large capacitive loads avoided. digital decoupling shown Figure ceramic chip tantalum capacitors appropriate. Reasonable capacitive loads data pins less than bit. Applications involving greater digital loads should consider increasing digital decoupling proportionally and/or using external buffers/latches. complete decoupling scheme will also include large tantalum electrolytic capacitors power supply connector reduce low-frequency ripple negligible levels.
EVALUATION BOARD TYPICAL BENCH CHARACTERIZATION TEST SETUP
connector. various input signal options accessible jumper connections. Refer Evaluation Board schematic. clock input signal AD9226 evaluation board applied inputs, CLOCK AUXCLK. CLOCK input should selected frequency input clock signal target sample rate AD9226. input clock signal ac-coupled level-shifted switching threshold 74VHC02 clock driver. AUXCLK input should selected applications requiring lowest jitter performance (i.e., Undersampling characterization). allows user apply clock input signal that target sample rate AD9226. low-jitter, differential divide-by-4 counter, MC100EL33D, provides clock output that subsequently returned back CLOCK input JP7. example, signal (sinusoid) will divided down signal clocking ADC. Note, must removed with AUXCLK interface. Lower jitter often achieved with this interface since many signal generators display improved phase noise higher output frequencies slew rate sinusoidal output signal that signal equal amplitude. Figure shows bench characterization setup used evaluate AD9226's performance many data sheet characterization curves. Signal Clock generators high-frequency, "very" low-phase noise frequency sources. These generators should phase locked sharing same signal (located instruments back panel) allow nonwindowed, coherent FFTs. Also, AUXCLK option AD9226 evaluation board should used achieve best performance. Since distortion broadband noise generator often limiting factor measuring true performance ADC, high passive bandpass filter should inserted between generator AD9226 evaluation board.
AD9226 evaluation board configured operate upon applying both power analog clock input signals. provides three possible analog input interfaces characterize AD9226's performance. characterization, provides transformer coupled input with common-mode input voltage (CMV) AVDD/2. Note, evaluation board shipped with transformer coupled interface input span. differential coupled applications, evaluation board provisions driven AD8138 amplifier. single-ended input desired, driven through
AVDD REFIN SIGNAL SYNTHESIZER 65(OR MHz), HP8644 BANDPASS FILTER INPUT xFMR
AVDD
DVDD
DVDD
AD9226
EVALUATION BOARD
OUTPUT WORD (P1)
EQUIPMENT
REFOUT
SYNTHESIZER 65(OR MHz), HP8644
INPUT CLOCK
CLOCK
Figure Evaluation Board Connections
REV.
-21-
AD9226
DUTAVDD JP23 JP22 0.001 FBEAD DUTAVDD VINA SHEET VINB DUTAVDD FBEAD AVDD 0.001 FBEAD DUTDRVDD DUTDRVDD 0.001 CONNECT FBEAD DVDD TP11 TP12 TP13 TP14
JP25
AD9226LQFP
AVDD1 AVDD2 AVSS1 AVSS2 SENSE VREF REFCOM CAPB1 CAPB2 CAPT1 CAPT2 VINA VINB AVSS3 AVSS4 AVDD3 AVDD4 DRVSS3 DRVDD3 DRVDD1 DRVSS1 MSB-B1
OTR0 D130 D120 D110 D100 AVDD
JP24
DUTAVDDIN
LSB-B14 DUTY DRVDD2 DRVSS2
AGND
DUTCLK
AVDDIN
DRVDDIN
AGND
DVDDIN
Figure AD9226 Evaluation Board
-22-
REV.
AD9226
74VHC541 AUXCLK 49.9
DVDD
T1-1T
1N5712 1N5712
AVDD
MC100EL33D
INCOM
AVDD
AVDD
AVDD DECOUPLING
74VHC541
JP17
AVDD DUTCLK
CLOCK
0.10 49.9 74VHC04
74VHC04
74VHC04 AVDD DECOUPLING
74VHC04
CONNECT
74VHC04
74VHC04
Figure AD9226 Evaluation Board
REV.
-23-
AD9226
OTRO D130 D120 D110
SINGLE INPUT 49.9 AVDD 0.33 JP42
D100
AVDD
AVDD
JP40 VINA SHEET 50pF VINB
JP45 JP46
JP41
INPUT 49.9
JP43
XFMR INPUT 49.9 DUTAVDD
AD8138
T1-1T
0.33
Figure AD9226 Evaluation Board
Figure Evaluation Board Component Side Layout (Not Scale)
-24-
REV.
AD9226
Figure Evaluation Board Solder Side Layout (Not Scale)
Figure Evaluation Board Power Plane
REV.
-25-
AD9226
Figure Evaluation Board Ground Plane
Figure Evaluation Board Component Side (Not Scale)
-26-
REV.
AD9226
Figure Evaluation Board Solder Side (Not Scale)
REV.
-27-
AD9226
OUTLINE DIMENSIONS
Dimensions shown inches (mm).
28-Lead Shrink Small Outline (RS-28)
0.407 (10.34) 0.397 (10.08)
48-Lead Thin Plastic Quad Flatpack (ST-48)
0.063 (1.60) 0.030 (0.75) 0.018 (0.45)
0.354 (9.00)
VIEW
(PINS DOWN)
0.276 (7.00)
COPLANARITY 0.003 (0.08) 0.008 (0.2) 0.004 (0.09)
0.078 (1.98) 0.068 (1.73)
0.07 (1.79) 0.066 (1.67)
0.019 (0.5)
0.011 (0.27) 0.006 (0.17) 0.057 (1.45) 0.053 (1.35)
0.008 (0.203) 0.0256 (0.65) 0.002 (0.050)
0.015 (0.38) SEATING 0.009 (0.229) 0.010 (0.25) PLANE 0.005 (0.127)
0.03 (0.762) 0.022 (0.558)
0.006 (0.15) SEATING 0.002 (0.05) PLANE
-28-
REV.
PRINTED U.S.A.
C01027-3-7/00 (rev.
0.311 (7.9) 0.301 (7.64)
0.212 (5.38) 0.205 (5.21)

VINA VINB Complete 12-Bit, MSPS Converter AD9226 FUNCTIONAL

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