Turbo Codec Demonstration Demonstrates decoder's ability correct
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Turbo Codec Demonstration
Demonstrates decoder's ability correct errors-results displayed 32-bit Niosembedded processor implementation
General Description
turbo encoder/decoder (codec) forward error correction (FEC) demonstration designed show capabilities Altera® turbo encoder/decoder MegaCore® function correcting errors. demonstration with system-on-a-programmable-chip (SOPC) board uses 32-bit Nios family soft-core embedded processors. SOPC board includes APEX20K400E device LCD, which allows monitor demonstration. Nios embedded processor sets codec, controls channel error rate, collates displays error information LCD. channel error rate errors every bits (where cycled from Nios embedded processor). Errors applied randomly information parity bits they pass through channel. channel error generator free running, however turbo codec resets every time there change channel error rate (every runs block. demonstration runs MHz. turbo codec parameters are:
SOFTBITS BLOCK SIZE 5114 ITERATIONS
Figure shows turbo codec demonstration block diagram. Figure Turbo Demonstration Block Diagram
Channel error rate Channel Error Generator
Random Sequence Generator
Encoder
Decoder
Number errors
Nios Embedded Processor Error Counters
Nios Embedded Processor Control
Screen
A-WP-SOPC_DEMO_TURBO-01.1
August 2000
Altera Corporation
Turbo Codec Demonstration
Walkthrough
turbo demonstration need:
SOPC board with APEX 20K400E Advanced SOPC Users Manual with Quartussoftware installed (version 2000.05 higher) Microsoft HyperTerminal ByteBlasterMVcable 0.64-socket-to-0.64-socket lead female-to-female straight-through serial cable
Altera Turbo Encoder/Decoder MegaCore Function User Guide gives further information turbo codec function. SOPC board connect JP11 using 0.64-socket 0.64-socket lead. Connect power supply SOPC board. Connect your SOPC board ByteBlasterMV connector (see Advanced SOPC Users Manual). Connect COM1 COM2) your SOPC board; need female-to-female adaptor this, SOPC board male. Ensure that JP12 SOPC board APEX device. Open Quartus software Open Programmer (Processing Menu). Mode drop-down select JTAG. Under Programming Hardware click Setup (refer Quartus Help details set-up) select ByteBlaster.
program APEX device described. Program APEX device programmer click Device. Select EP20K400EBC652. Right click device, select Change File, find select aukt_sopc_turbo_nios32_top.sof. Click Start. Minimize Quartus open Microsoft HyperTerminal. Enter name connection, e.g., Nios. Connect dialog box, select relevant port. Figure shows port property values. values click
Altera Corporation
Turbo Codec Demonstration
Figure Port Properties
SOPC board four buttons; only SOPC Reset (Button used. Press SOPC Reset. HyperTerminal displays `Welcome Nios. Boot Version 1.6', SOPC board flashes Select Send Text File (Transfer menu), find open TurboCodec.srec file. When click demonstration begins.
Using Demo Once demonstration running, shows `Channel Err: ****' `Error out: ****'. first number number channel errors; second number codec errors. SOPC reset reset demonstration time.
Innovation Drive Jose, 95134 (408) 544-7000 http://www.altera.com
Copyright 2000 Altera Corporation. Altera, APEX, ByteBlaster, MegaCore, Quartus trademarks and/or service marks Altera Corporation United States other countries. Other brands products trademarks their respective holders. specifications contained herein subject change without notice. Altera assumes responsibility liability arising application information, product, service described herein except expressly agreed writing Altera Corporation. Altera customers advised obtain latest version device specifications before relying published information before placing orders products services. rights reserved.
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