Building Blocks Rapid Communication System Development explosive

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Building Blocks Rapid Communication System Development explosive

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Building Blocks Rapid Communication System Development
explosive growth Internet placed huge demands communications industry rapidly develop deploy products that support wide array protocols with highly flexible architecture. aggregate amount Internet data traffic continues climb subscribers online rapid rate, individual subscribers consume more data through graphic rich sites, large file transfers, streaming video content. need increased bandwidth over "last mile" from home central office been well documented, gradual deployment cable modem infrastructure started satisfy some consumer demand. Aggregate backbone capacity continues increase fiber optic cable deployed rapid rate, while data rate individual channels accelerates from Optical Carrier Level (OC-12) OC-48 OC-192, number data streams carried each fiber expands through advancements Dense Wavelength Division Multiplexing (DWDM) technologies. Although demand more bandwidth subscribers accelerated rate growth network backbone capacity, impact edge network been more profound. remain competitive, communication system manufacturers developing products edge network need rapidly develop systems that support growing list access services being deployed, including newer services such cable modem, existing Kbps dial-up, traditional T/E-carrier services used business subscribers. variety different protocols need supported these transmission media, including Frame Relay, Asynchronous Transfer Mode (ATM) Point-to-Point Protocol (PPP). With continuous change both sides edge network, there absolute requirement flexible architectures Metropolitan Area Network (MAN) equipment, including terminal/access multiplexers, edge routers, edge switches, Synchronous Optical Network (SONET) Synchronous Digital Hierarchy (SDH) add-drop multiplexers.
Implementation Options
Vendors Application Specific Standard Products (ASSPs) have attempted satisfy these needs with chipset families multi-mode products. These products low-cost, high-performance, advantageous solutions some applications, disadvantageous many other instances. First, ASSPs usually require multi-chip solutions, increasing board space power consumption. This because individual ASSPs typically provide primary functions such SONET/SDH framing Acell delineation. However, neighboring functions such traffic management switching require additional chips, overall two- three-chip solution. Second, individual ASSPs often targeted broad audience with several similar functions included single chip. example, ASSPs available SONET/SDH Virtual Tributary (VT) mapping, these chips typically provide VT-1.5, VT-2, VT-3 VT-6 mapping, though users typically require only these functions given product implementation. such, users gates that they require, burdened with complicated software programming these multi-mode chips. These problems addressed through high-density Programmable Logic Devices (PLDs). PLDs integrate several functions, such SONET/SDH framer, Acell delineator, traffic manager switch, into single device. Also, users PLDs select only functions they require, consume only gates needed their application. Reducing gate consumption lowers device costs, facilitates higher level integration single PLD, yields more efficient system design. ease integration distinct cores, each function should designed part larger family with strong architectural approach partitioning interfaces. broad portfolio configurable functions with standardized
A-WP-RapidCom-01
March 2001, ver.
Altera Corporation
Building Blocks Rapid Communication System Development
interfaces required. System designers could then select functions they require, configure them their specific requirements, simply connect customized cores proprietary user-logic (through standardized interfaces) highly efficient unique design. example, many companies design line cards that support transport either Acells packets over SONET/SDH variety different data rates (155 Mbps, Mbps, Gbps). transmission convergence layer these line cards partitioned into distinct functions, SONET/ framing, Acell packet delineation. ASSP solutions available that support either transport cells packets over SONET/SDH software configuration option. This approach ideal because only mode (cell packet) used given line card-though board populated with larger device capable both modes-and entirely different chips required different data rates.
Communications Programmable Logic
Altera® invested heavily development intellectual property (IP) cores that optimized PLDs, provide highest degree flexibility possible. Altera MegaCore® functions configured prior synthesis through MegaWizard® Plug-In, easy-to-use graphical user interface which allows designers quickly easily eliminate features that required, thus reducing device consumption simplifying software integration. Configurable MegaCore functions SONET/SDH framing, Acell processing, packet processing available programmable logic. Each core configured before synthesis eliminate unused features. SONET/SDH framers configured with without serial insertion extraction transport overhead (TOH) path overhead (POH) bytes through hardware, section trace byte) monitoring, path trace byte) monitoring, error rate (one second window) monitoring. Acell processors provide cell delineation, optional gates cell insertion extraction, performance monitoring, four generic cell filters, which used monitor specific subscriber's traffic (for trouble shooting), manage Operations, Administration Maintenance (OAM) flows. packet processors provide byte-oriented HDLC-like framing used transport convergence layer Packet over SONET/SDH (PoS). System developers have been forced either chipset from single ASSP vendor, ASSPs from variety vendors, often requiring additional chips bridge incompatible interfaces. avoid similar problems while integrating cores, developers should follow plug play model using standard interfaces between cores. Altera developed published three such interfaces: Middle (Midbus) interface, Access Internal Registers (AIRbus) interface, Atlantic Interface. Figure below illustrates usage these interfaces four typical applications-Aor Packet over SONET/SDH STS-3c/STM-1 STS-12c/STM-4. Figure Typical Applications-Aor Packet over SONET/SDH, STS-12c/STM-4 STS-3c/STM-1.
Midbus rxclk Fiber Optic Module Clock Data Recovery SER/DES SONET/SDH Framer ACell Packet Processor User Logic UTOPIA POSPHY Interface Atlantic Atlantic
txclk External Processor Interface AIRbus Boundary
Inventory costs minimized, while retaining flexibility, storing multiple device programming files flash memory (four this example). programmed boot-up line card with appropriate configuration (Aover SONET/SDH STS-12c/STM-4, Packet over SONET/SDH STS-12c/STM-4, Aover SONET/ STS-3c/STM-1, Packet over SONET/SDH STS-3c/STM-1). User logic these examples could traffic management, routing switching functions. Standard interface cores also available data path,
Altera Corporation
Building Blocks Rapid Communication System Development
including POSPHY UTOPIA, well interfaces that often used processor interface across backplane. loading with only required gates (one four programming files this example), size minimized, while same supports each operating mode. framing, mapping, mapping functions that compliment Altera SONET/SDH, ATM, cores also available. Because these cores designed with standard interfaces, they easily connected variety configurations different applications. example, channels mapped asynchronously into SONET/ using mapper SONET/SDH framer, required application, frame alignment information made available adding framer design. Alternatively, line used transport cells packets, combining framer with either Acell processor, packet processor. Full duplex framer cores VT-1.5 VT-2 mapper cores planned later this year (2001). addition single channel designs, configuration options multi-channel support will provided, including channels framing VT-1.5 mapping, channels framing VT-2 mapping. Time slicing design techniques will used optimize cores programmable logic. Figure illustrates these MegaCore functions could used develop line card SONET/SDH add-drop multiplexer with unprecedented level integration. Figure Typical Applications-Line Card SONET/SDH Add-Drop Mux, lines Add/Dropped to/from STS-1.
Midbus
Framer
Line
Line Interface Unit
VT-1.5 Mapper
Line
Line Interface Unit
SONET STS-3 Framer
SERDES
Serial Data to/from Backplane
Boundary
line card referenced Figure could connected backplane STS-3 switching. Similar line cards could used add/drop lines, replacing framer VT-1.5 mapper with framers mappers, add/drop lines using framers mappers, add/drop lines using framer VT-2 mapper, add/drop access lines such with user designed logic framing mapping. corresponding network card could receive switched STS-3 signals from backplane multiplex them into STS-12 transmission over OC-12 ring, into STS-48 transmission over OC-48 ring. opposite direction, egress traffic from OC-12 ring would de-interleaved into twelve STS-1 signals switched backplane applicable line card. underlying quality core important. Many designers have experiences with discussed earlier, difficult integrate cores from more suppliers with proprietary user logic. Design reuse requires advanced planning standardized interfaces, multiple cores user logic easily integrated. addition, cores must deliver specified functionality performance. Altera embraces these approaches, assure quality, complete hardware testing complex high-performance cores performed compliance with industry standards.
Altera Corporation
Building Blocks Rapid Communication System Development
Cost Implementation
combination SONET framer with channel VT-1.5 mapper channel framer single would require mid-size PLD. This highly integrated system-on-programmable-chip (SOPC) would consume approximately 18,000 logic elements (LEs) APEX20KE device, more specifically, 20K600E-3 part, device that currently lists $460 volume. External Line Interface Units (LIUs) commercially available approximately channel, increasing cost this solution $800. Implementing these functions provides flexibility manage inevitable "feature creep" that arises during development process. comparison, solution using multiple ASSPs would require several chips, including SONET framer, mapper, four framers with integrated LIUs (three octals quad). This six-chip solution lists approximately $800 aggregate, offers considerably less flexibility than PLD-based solution. addition, software integration ASSP-based solution would considerably more complex. PLD-based solution provides cost-competitive solution, especially existing migration paths high volume, lower-cost silicon from vendors considered. Altera offers turn-key migration path lower-cost mask programmed logic devices (HardCopy devices) high-volume, high-density designs. HardCopy implementation process offers guaranteed functionality performance with minimal customer involvement, samples weeks, production volumes 15-16 weeks from start design conversion. Using HardCopy eliminates risks associated with manual migration from Application Specific Integrated Circuit (ASIC), up-front costs significantly less. Design costs migrate design outlined above ASIC would $150-250K range, layout would approximately $50K, non-recurring manufacturing costs would $200-500K depending technology targeted, total design conversion cost $400-800K. This process typically takes least weeks design verification, weeks layout, weeks samples, weeks testing, then weeks volume production, total design conversion cycle least elapsed weeks. addition, risks involved with this manual process significant, possibility re-spin very real. contrast, converting this design HardCopy would require only 15-16 weeks elapsed time volume production, design conversion cost would only $125K, HardCopy unit costs would reduced less than high-volume. With external LIUs costing $335, this solution would cost less than $410, compared competitive multi-ASSP solution that costs $800.
Role Embedded Processors
Flexibility also required interface line cards with host processors. approach would utilize embedded processor PLD. example, embedded processor could implemented designs line cards described above. addition lower performance soft-core processors that have been available many years, Altera embedded high-performance hard-core processors PLDs. This approach does negate requirement host processor, which remains traditional location processor card. local management specific line card functions provides great deal flexibility abstracting actual implementation, eases provisioning lines line cards, reduces burden host processor. example, software framer could processed locally line card, with performance monitoring statistics stored memory resources external memory. local processor would send messages host processor when applicable error conditions have been detected dealt with, provide status reports host processor when requested. Standard software interfaces would developed used with each line card, making development line cards system simple task, with integration completely under control software.
Altera Corporation
Building Blocks Rapid Communication System Development
Conclusion
Programmable logic applications throughout network. Complex functions, such those outlined this discussion, easily implemented PLDs data path Metropolitan Networks, where flexibility provided configurable cores necessary. backbone, where performance premium, complex functions will typically implemented initially ASIC/ASSPs. connect incompatible devices, insert proprietary user logic between ASIC/ASSPs, Altera will offer mid-2001) selection industry standard high-speed interfaces that optimized PLDs, including SPI-4 Phase (FlexBus Level SPI-4 Phase (POSPHY Level selection lower speed interfaces available within compiler, including Level Level Link-side PHY-side interfaces, with ability join together applicable cores interface bridges (e.g. bridge from single POSPHY Level Link-side interface four POSPHY Level PHY-side interfaces). UTOPIA Level Level cores also available. Using configurable MegaCore functions with proprietary logic targeted programmable logic device leads rapid development deployment unique products. This highly flexible approach system design produces architectures that supported while network infrastructure continues evolve sustain explosive growth Internet.
Innovation Drive Jose, 95134 (408) 544-7000 http://www.altera.com
Copyright 2001 Altera Corporation. Altera, APEX, MegaCore, MegaWizard trademarks and/or service marks Altera Corporation United States other countries. Other brands products trademarks their respective holders. specifications contained herein subject change without notice. Altera assumes responsibility liability arising application information, product, service described herein except expressly agreed writing Altera Corporation. Altera customers advised obtain latest version device specifications before relying published information before placing orders products services. rights reserved.

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