4738.1 75A, 80V, 0.010 Ohm, N-Channel, UltraFET Power MOSFET Pack

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4738.1 75A, 80V, 0.010 Ohm, N-Channel, UltraFET Power MOSFET Pack

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HUF75545P3, HUF75545S3S
4738.1
75A, 80V, 0.010 Ohm, N-Channel, UltraFET Power MOSFET Packaging
JEDEC TO-220AB
SOURCE DRAIN GATE
Features
JEDEC TO-263AB
DRAIN (FLANGE)
Ultra On-Resistance rDS(ON) 0.010, Simulation Models Temperature Compensated PSPICE® SABER© Electrical Models Spice SABER© Thermal Impedance Models www.semi.Intersil.com Peak Current Pulse Width Curve
GATE SOURCE DRAIN (FLANGE)
HUF75545P3
HUF75545S3S
Rating Curve
Symbol
Ordering Information
PART NUMBER HUF75545P3 HUF75545S3S
PACKAGE TO-220AB TO-263AB
BRAND 75545P 75545S
NOTE: When ordering, entire part number. suffix obtain TO-263AB variant tape reel, e.g., HUF75545S3ST.
Absolute Maximum Ratings
25oC, Unless Otherwise Specified HUF75545P3, HUF75545S3S UNITS Figure Figures W/oC
Drain Source Voltage (Note VDSS Drain Gate Voltage (RGS 20k) (Note VDGR Gate Source Voltage Drain Current Continuous (TC= 25oC, 10V) (Figure Continuous (TC= 100oC, 10V) (Figure Pulsed Drain Current .IDM Pulsed Avalanche Rating .UIS Power Dissipation Derate Above 25oC Operating Storage Temperature TSTG Maximum Temperature Soldering Leads 0.063in (1.6mm) from Case 10s. Package Body 10s, Techbrief TB334 Tpkg NOTES:
25oC 150oC. CAUTION: Stresses above those listed "Absolute Maximum Ratings" cause permanent damage device. This stress only rating operation device these other conditions above those indicated operational sections this specification implied.
CAUTION: These devices sensitive electrostatic discharge. Follow proper Handling Procedures. UltraFETis trademark Intersil Corporation. PSPICE® registered trademark MicroSim Corporation. SABER© Copyright Analogy Inc. http://www.intersil.com 407-727-9207 Copyright Intersil Corporation 1999
HUF75545P3, HUF75545S3S
Electrical Specifications
PARAMETER STATE SPECIFICATIONS Drain Source Breakdown Voltage Zero Gate Voltage Drain Current BVDSS IDSS 250µA, (Figure 75V, 70V, 150oC Gate Source Leakage Current STATE SPECIFICATIONS Gate Source Threshold Voltage Drain Source Resistance THERMAL SPECIFICATIONS Thermal Resistance Junction Case Thermal Resistance Junction Ambient TO-220 TO-263 0.55
oC/W oC/W
25oC, Unless Otherwise Specified SYMBOL TEST CONDITIONS UNITS
±100
IGSS
±20V
VGS(TH) rDS(ON)
VDS, 250µA (Figure 75A, (Figure
0.0082
0.010
SWITCHING SPECIFICATIONS (VGS 10V) Turn-On Time Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time Turn-Off Time GATE CHARGE SPECIFICATIONS Total Gate Charge Gate Charge Threshold Gate Charge Gate Source Gate Charge Reverse Transfer Capacitance CAPACITANCE SPECIFICATIONS Input Capacitance Output Capacitance Reverse Transfer Capacitance CISS COSS CRSS 25V, 1MHz (Figure 3750 1100 Qg(TOT) Qg(10) Qg(TH) 40V, 75A, Ig(REF) 1.0mA (Figures td(ON) td(OFF) tOFF 40V, 10V, (Figures
Source Drain Diode Specifications
PARAMETER Source Drain Diode Voltage SYMBOL Reverse Recovery Time Reverse Recovered Charge 75A, dISD/dt 100A/µs 75A, dISD/dt 100A/µs TEST CONDITIONS 1.25 1.00 UNITS
HUF75545P3, HUF75545S3S Typical Performance Curves
POWER DISSIPATION MULTIPLIER DRAIN CURRENT CASE TEMPERATURE (oC)
CASE TEMPERATURE (oC)
FIGURE NORMALIZED POWER DISSIPATION CASE TEMPERATURE
FIGURE MAXIMUM CONTINUOUS DRAIN CURRENT CASE TEMPERATURE
THERMAL IMPEDANCE ZJC, NORMALIZED DUTY CYCLE DESCENDING ORDER 0.05 0.02 0.01 SINGLE PULSE 0.01 10-5 10-4 10-3 10-2 RECTANGULAR PULSE DURATION 10-1 NOTES: DUTY FACTOR: t1/t2 PEAK
FIGURE NORMALIZED MAXIMUM TRANSIENT THERMAL IMPEDANCE
2000
25oC TEMPERATURES ABOVE 25oC DERATE PEAK CURRENT FOLLOWS:
IDM, PEAK CURRENT
1000
TRANSCONDUCTANCE LIMIT CURRENT THIS REGION 10-4 10-3 10-2 PULSE WIDTH 10-1
10-5
FIGURE PEAK CURRENT CAPABILITY
HUF75545P3, HUF75545S3S Typical Performance Curves
IAS, AVALANCHE CURRENT
(Continued)
DRAIN CURRENT
(L)(IAS)/(1.3*RATED BVDSS VDD) (L/R)ln[(IAS*R)/(1.3*RATED BVDSS VDD) STARTING 25oC
100µs
OPERATION THIS AREA LIMITED rDS(ON) SINGLE PULSE RATED 25oC VDS, DRAIN SOURCE VOLTAGE
10ms
STARTING 150oC
0.001
0.01
tAV, TIME AVALANCHE (ms)
NOTE: Refer Intersil Application Notes AN9321 AN9322. FIGURE FORWARD BIAS SAFE OPERATING AREA FIGURE UNCLAMPED INDUCTIVE SWITCHING CAPABILITY
PULSE DURATION 80µs DUTY CYCLE 0.5%
DRAIN CURRENT
DRAIN CURRENT
175oC 25oC
-55oC
VGS, GATE SOURCE VOLTAGE
PULSE DURATION 80µs DUTY CYCLE 0.5% 25oC VDS, DRAIN SOURCE VOLTAGE
FIGURE TRANSFER CHARACTERISTICS
FIGURE SATURATION CHARACTERISTICS
NORMALIZED DRAIN SOURCE RESISTANCE PULSE DURATION 80µs 10V, DUTY CYCLE 0.5% NORMALIZED GATE THRESHOLD VOLTAGE
VDS, 250µA
JUNCTION TEMPERATURE (oC)
JUNCTION TEMPERATURE (oC)
FIGURE NORMALIZED DRAIN SOURCE RESISTANCE JUNCTION TEMPERATURE
FIGURE NORMALIZED GATE THRESHOLD VOLTAGE JUNCTION TEMPERATURE
HUF75545P3, HUF75545S3S Typical Performance Curves
NORMALIZED DRAIN SOURCE BREAKDOWN VOLTAGE 250µA CAPACITANCE (pF)
(Continued)
10000 CISS COSS
1000
CRSS 1MHz
JUNCTION TEMPERATURE (oC)
DRAIN SOURCE VOLTAGE
FIGURE NORMALIZED DRAIN SOURCE BREAKDOWN VOLTAGE JUNCTION TEMPERATURE
FIGURE CAPACITANCE DRAIN SOURCE VOLTAGE
GATE SOURCE VOLTAGE
WAVEFORMS DESCENDING ORDER: GATE CHARGE (nC)
NOTE: Refer Intersil Application Notes AN7254 AN7260. FIGURE GATE CHARGE WAVEFORMS CONSTANT GATE CURRENT
Test Circuits Waveforms
BVDSS VARY OBTAIN REQUIRED PEAK
0.01
FIGURE UNCLAMPED ENERGY TEST CIRCUIT
FIGURE UNCLAMPED ENERGY WAVEFORMS
HUF75545P3, HUF75545S3S Test Circuits Waveforms
(Continued)
Qg(TOT)
Qg(10) Qg(TH) Ig(REF)
Ig(REF)
FIGURE GATE CHARGE TEST CIRCUIT
FIGURE GATE CHARGE WAVEFORMS
td(ON)
tOFF td(OFF)
PULSE WIDTH
FIGURE SWITCHING TIME TEST CIRCUIT
FIGURE SWITCHING TIME WAVEFORM
HUF75545P3, HUF75545S3S PSPICE Electrical Model
.SUBCKT HUF75545
5.4e-9 5.3e-9 3.4e-9 DBODY DBODYMOD DBREAK DBREAKMOD DPLCAP DPLCAPMOD
1999
LDRAIN DPLCAP RLDRAIN DBREAK EBREAK DRAIN RSLC1 ESLC
RSLC2
LGATE GATE RLGATE EVTEMP RGATE EVTHRES
LDRAIN 1.0e-9 LGATE 5.1e-9 LSOURCE 4.4e-9 MMED MMEDMOD MSTRO MSTROMOD MWEAK MWEAKMOD RBREAK RBREAKMOD RDRAIN RDRAINMOD 4.80e-3 RGATE 0.87 RLDRAIN RLGATE RLSOURCE RSLC1 RSLCMOD 1e-6 RSLC2 RSOURCE RSOURCEMOD 1.6e-3 RVTHRES RVTHRESMOD RVTEMP RVTEMPMOD S1AMOD S1BMOD S2AMOD S2BMOD
MSTRO LSOURCE RSOURCE RLSOURCE SOURCE
VBAT ESLC .MODEL DBODYMOD 3.6e-12 2.1e-3 TRS1 1.5e-3 TRS2 5.1e-6 4.6e-9 3.3e-8 0.55) .MODEL DBREAKMOD 2.3e-1 TRS1 TRS2 -1.8e-5) .MODEL DPLCAPMOD (CJO 4.8e-9 1e-30 0.8) .MODEL MMEDMOD NMOS (VTO 3.04 1e-30 0.87) .MODEL MSTROMOD NMOS (VTO 1e-30 .MODEL MWEAKMOD NMOS (VTO 2.65 0.12 1e-30 .MODEL RBREAKMOD (TC1 1.3e-3 -1e-6) .MODEL RDRAINMOD (TC1 9e-3 2.8e-5) .MODEL RSLCMOD (TC1 1.53e-3 2e-5) .MODEL RSOURCEMOD (TC1 1e-3 1e-6) .MODEL RVTHRESMOD (TC1 -2.3e-3 -1.2e-5) .MODEL RVTEMPMOD (TC1 -2.9e-3 5e-7) .MODEL S1AMOD VSWITCH (RON 1e-5 .MODEL S1BMOD VSWITCH (RON 1e-5 .MODEL S2AMOD VSWITCH (RON 1e-5 .MODEL S2BMOD VSWITCH (RON 1e-5 .ENDS ROFF ROFF ROFF ROFF VOFF= VOFF= -1.5 VOFF= 0.5) VOFF= -1.5)
NOTE: further discussion PSPICE model, consult PSPICE Sub-Circuit Power MOSFET Featuring Global Temperature Options; IEEE Power Electronics Specialist Conference Records, 1991, written William Hepp Frank Wheatley.
EBREAK 87.4 EVTHRES EVTEMP
RDRAIN
DBODY
MWEAK MMED
RBREAK RVTEMP
VBAT
RVTHRES
HUF75545P3, HUF75545S3S SABER Electrical Model
1999
template huf75545 n2,n1,n3 electrical n2,n1,n3 iscl d.model dbodymod 3.6e-12, 4.6e-9, 3.3e-8, 0.55) d.model dbreakmod d.model dplcapmod (cjo 4.8e-9, 1e-30, vj=1.0, m.model mmedmod (type=_n, 3.04, 1e-30, m.model mstrongmod (type=_n, 3.5, 105, 1e-30, m.model mweakmod (type=_n, 2.65, 0.12, 1e-30, sw_vcsp.model s1amod (ron 1e-5, roff 0.1, voff sw_vcsp.model s1bmod (ron =1e-5, roff 0.1, voff sw_vcsp.model s2amod (ron 1e-5, roff 0.1, -1.5, voff 0.5) sw_vcsp.model s2bmod (ron 1e-5, roff 0.1, 0.5, voff -1.5) c.ca 5.4e-9 c.cb 5.3e-9 c.cin 3.4e-9 d.dbody model=dbodymod d.dbreak model=dbreakmod d.dplcap model=dplcapmod i.it l.ldrain 1e-9 l.lgate 5.1e-9 l.lsource 4.4e-9
GATE RLGATE LGATE
LDRAIN DPLCAP RSLC1 RSLC2 ISCL RLDRAIN RDBREAK DBREAK MWEAK MMED MSTRO EBREAK RDBODY DRAIN
EVTEMP RGATE EVTHRES
RDRAIN
DBODY
LSOURCE RLSOURCE
m.mmed model=mmedmod, l=1u, w=1u m.mstrong model=mstrongmod, l=1u, w=1u m.mweak model=mweakmod, l=1u, w=1u
SOURCE
RSOURCE RBREAK RVTEMP
res.rbreak 1.3e-3, -1e-6 res.rdbody 2.1e-3, 1.5e-3, 5.1e-6 res.rdbreak 2.3e-1, -1.8e-5 res.rdrain 4.8e-3, 9e-3, 2.8e-5 res.rgate 0.87 res.rldrain res.rlgate res.rlsource res.rslc1 1e-6, 1.53e-3, 2e-5 res.rslc2 res.rsource 1.6e-3, 1e-3, 1e-6 res.rvtemp -2.9e-3, 5e-7 res.rvthres -2.3e-3, -1.2e-5 spe.ebreak 87.4 spe.eds spe.egs spe.esg spe.evtemp spe.evthres sw_vcsp.s1a model=s1amod sw_vcsp.s1b model=s1bmod sw_vcsp.s2a model=s2amod sw_vcsp.s2b model=s2bmod v.vbat dc=1
VBAT
RVTHRES
equations (n51->n50) +=iscl iscl: v(n51,n50)
HUF75545P3, HUF75545S3S SPICE Thermal Model
1999 HUF75545T CTHERM1 6.4e-3 CTHERM2 3.0e-2 CTHERM3 1.4e-2 CTHERM4 1.6e-2 CTHERM5 5.5e-2 CTHERM6 RTHERM1 3.2e-3 RTHERM2 8.1e-3 RTHERM3 2.3e-2 RTHERM4 1.3e-1 RTHERM5 1.8e-1 RTHERM6 3.8e-2
JUNCTION
RTHERM1
CTHERM1
RTHERM2
CTHERM2
SABER Thermal Model
SABER thermal model HUF75545T template thermal_model thermal_c ctherm.ctherm1 6.4e-3 ctherm.ctherm2 3.0e-2 ctherm.ctherm3 1.4e-2 ctherm.ctherm4 1.6e-2 ctherm.ctherm5 5.5e-2 ctherm.ctherm6 rtherm.rtherm1 3.2e-3 rtherm.rtherm2 8.1e-3 rtherm.rtherm3 2.3e-2 rtherm.rtherm4 1.3e-1 rtherm.rtherm5 1.8e-1 rtherm.rtherm6 3.8e-2
RTHERM3
CTHERM3
RTHERM4
CTHERM4
RTHERM5
CTHERM5
RTHERM6
CTHERM6
CASE
Intersil semiconductor products manufactured, assembled tested under ISO9000 quality systems certification.
Intersil semiconductor products sold description only. Intersil Corporation reserves right make changes circuit design and/or specifications time without notice. Accordingly, reader cautioned verify that data sheets current before placing orders. Information furnished Intersil believed accurate reliable. However, responsibility assumed Intersil subsidiaries use; infringements patents other rights third parties which result from use. license granted implication otherwise under patent patent rights Intersil subsidiaries.
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4738.1 75A, 80V, 0.010 Ohm, N-Channel, UltraFET Power MOSFET Pack

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