4362.5 66A, 55V, 0.016 Ohm. N-Channel UltraFET Power MOSFETs

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4362.5 66A, 55V, 0.016 Ohm. N-Channel UltraFET Power MOSFETs

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HUF75333G3, HUF75333P3, HUF75333S3S
4362.5
66A, 55V, 0.016 Ohm. N-Channel UltraFET Power MOSFETs
These N-Channel power MOSFETs manufactured using innovative UltraFETprocess. This advanced process technology achieves lowest possible on-resistance silicon area, resulting outstanding performance. This device capable withstanding high energy avalanche mode diode exhibits very reverse recovery time stored charge. designed applications where power efficiency important, such switching regulators, switching convertors, motor drivers, relay drivers, lowvoltage switches, power management portable battery-operated products. Formerly developmental type TA75333.
Features
66A, Simulation Models Temperature Compensated PSPICE® SABER© Models SPICE SABER Thermal Impedance Models Available Peak Current Pulse Width Curve Rating Curve Related Literature TB334, "Guidelines Soldering Surface Mount Components Boards"
Symbol
Ordering Information
PART NUMBER HUF75333G3 HUF75333P3 HUF75333S3S PACKAGE TO-247 TO-220AB TO-263AB BRAND 75333G 75333P 75333S
NOTE: When ordering, entire part number. suffix obtain TO-263AB variant tape reel, e.g., HUF75333S3ST.
Packaging
JEDEC STYLE TO-247
SOURCE DRAIN GATE DRAIN (FLANGE)
JEDEC TO-220AB
SOURCE DRAIN GATE
DRAIN (TAB)
JEDEC TO-263AB
DRAIN (FLANGE) GATE SOURCE
CAUTION: These devices sensitive electrostatic discharge; follow proper Handling Procedures. UltraFETis trademark Intersil Corporation. PSPICE® registered trademark MicroSim Corporation. SABER© Copyright Analogy, Inc. http://www.intersil.com 407-727-9207 Copyright Intersil Corporation 1999
HUF75333G3, HUF75333P3, HUF75333S3S
Absolute Maximum Ratings
25oC, Unless Otherwise Specified Figure Figures UNITS
Drain Source Voltage (Note VDSS Drain Gate Voltage (RGS 20k) (Note VDGR Gate Source Voltage Drain Current Continuous (Figure Pulsed Drain Current .IDM Pulsed Avalanche Rating Power Dissipation Derate Above 25oC Operating Storage Temperature TSTG Maximum Temperature Soldering Leads 0.063in (1.6mm) from Case 10s. Package Body 10s, Techbrief Tpkg
W/oC
CAUTION: Stresses above those listed "Absolute Maximum Ratings" cause permanent damage device. This stress only rating operation device these other conditions above those indicated operational sections this specification implied.
NOTE: 25oC 150oC.
Electrical Specifications
PARAMETER STATE SPECIFICATIONS
25oC, Unless Otherwise Specified SYMBOL TEST CONDITIONS UNITS
Drain Source Breakdown Voltage Zero Gate Voltage Drain Current
BVDSS IDSS
250µA, (Figure 50V, 45V, 150oC
±100
Gate Source Leakage Current STATE SPECIFICATIONS Gate Source Threshold Voltage Drain Source Resistance THERMAL SPECIFICATIONS Thermal Resistance Junction Case Thermal Resistance Junction Ambient
IGSS
±20V
VGS(TH) rDS(ON)
VDS, 250µA (Figure 66A, (Figure
0.013
0.016
(Figure TO-247 TO-220, TO-263
oC/W oC/W oC/W
SWITCHING SPECIFICATIONS (VGS 10V) Turn-On Time Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time Turn-Off Time GATE CHARGE SPECIFICATIONS Total Gate Charge Gate Charge Threshold Gate Charge Gate Source Gate Charge Reverse Transfer Capacitance Qg(TOT) Qg(10) Qg(TH) 30V, 66A, 0.455 Ig(REF) 1.0mA (Figure td(ON) td(OFF) tOFF 30V, 66A, 0.455, 10V,
HUF75333G3, HUF75333P3, HUF75333S3S
Electrical Specifications
PARAMETER CAPACITANCE SPECIFICATIONS Input Capacitance Output Capacitance Reverse Transfer Capacitance CISS COSS CRSS 25V, 1MHz (Figure 1300 25oC, Unless Otherwise Specified SYMBOL TEST CONDITIONS UNITS
Source Drain Diode Specifications
PARAMETER Source Drain Diode Voltage Reverse Recovery Time Reverse Recovered Charge SYMBOL 66A, dISD/dt 100A/µs 66A, dISD/dt 100A/µs TEST CONDITIONS 1.25 UNITS
Typical Performance Curves
POWER DISSIPATION MULTIPLIER CASE TEMPERATURE (oC) DRAIN CURRENT CASE TEMPERATURE (oC)
FIGURE NORMALIZED POWER DISSIPATION CASE TEMPERATURE
FIGURE MAXIMUM CONTINUOUS DRAIN CURRENT CASE TEMPERATURE
THERMAL IMPEDANCE ZJC, NORMALIZED DUTY CYCLE DESCENDING ORDER 0.05 0.02 0.01
NOTES: DUTY FACTOR: t1/t2 PEAK 10-3 10-2 RECTANGULAR PULSE DURATION 10-1
SINGLE PULSE 0.01 10-5 10-4
FIGURE NORMALIZED MAXIMUM TRANSIENT THERMAL IMPEDANCE
HUF75333G3, HUF75333P3, HUF75333S3S Typical Performance Curves
1000
(Continued)
25oC
TEMPERATURES ABOVE 25oC DERATE PEAK CURRENT FOLLOWS:
IDM, PEAK CURRENT
TRANSCONDUCTANCE LIMIT CURRENT THIS REGION 10-4 10-3 10-2 PULSE WIDTH 10-1
10-5
FIGURE PEAK CURRENT CAPABILITY
IAS, AVALANCHE CURRENT RATED 25oC DRAIN CURRENT 100µs
(L)(IAS)/(1.3*RATED BVDSS VDD) (L/R)ln[(IAS*R)/(1.3*RATED BVDSS VDD)
STARTING 25oC
OPERATION THIS AREA LIMITED rDS(ON) VDSS(MAX)
10ms
STARTING 150oC
VDS, DRAIN SOURCE VOLTAGE
0.001
0.01
tAV, TIME AVALANCHE (ms)
NOTE: Refer Intersil Application Notes AN9321 AN9322. FIGURE FORWARD BIAS SAFE OPERATING AREA FIGURE UNCLAMPED INDUCTIVE SWITCHING CAPABILITY
DRAIN CURRENT DRAIN CURRENT
PULSE DURATION 80µs DUTY CYCLE 0.5%
-55oC
25oC 175oC
PULSE DURATION 80µs DUTY CYCLE 0.5% 25oC
VGS, GATE SOURCE VOLTAGE
VDS, DRAIN SOURCE VOLTAGE
FIGURE SATURATION CHARACTERISTICS
FIGURE TRANSFER CHARACTERISTICS
HUF75333G3, HUF75333P3, HUF75333S3S Typical Performance Curves
NORMALIZED DRAIN SOURCE RESISTANCE PULSE DURATION 80µs DUTY CYCLE 0.5% 10V, NORMALIZED GATE THRESHOLD VOLTAGE
(Continued)
VDS, 250µA
JUNCTION TEMPERATURE (oC)
JUNCTION TEMPERATURE (oC)
FIGURE NORMALIZED DRAIN SOURCE RESISTANCE JUNCTION TEMPERATURE
FIGURE NORMALIZED GATE THRESHOLD VOLTAGE JUNCTION TEMPERATURE
NORMALIZED DRAIN SOURCE BREAKDOWN VOLTAGE 250µA CAPACITANCE (pF)
2000 1MHz CISS CRSS COSS CISS 1000
1500
COSS CRSS
JUNCTION TEMPERATURE (oC)
DRAIN SOURCE VOLTAGE
FIGURE NORMALIZED DRAIN SOURCE BREAKDOWN VOLTAGE JUNCTION TEMPERATURE
FIGURE CAPACITANCE DRAIN SOURCE VOLTAGE
GATE SOURCE VOLTAGE
WAVEFORMS DESCENDING ORDER: GATE CHARGE (nC)
NOTE: Refer Intersil Application Notes AN7254 AN7260. FIGURE GATE CHARGE WAVEFORMS CONSTANT GATE CURRENT
HUF75333G3, HUF75333P3, HUF75333S3S Test Circuits Waveforms
BVDSS VARY OBTAIN REQUIRED PEAK
0.01
FIGURE UNCLAMPED ENERGY TEST CIRCUIT
FIGURE UNCLAMPED ENERGY WAVEFORMS
Qg(TOT)
Qg(10) Qg(TH) Ig(REF)
IG(REF)
FIGURE GATE CHARGE TEST CIRCUIT
FIGURE GATE CHARGE WAVEFORM
td(ON)
tOFF td(OFF)
PULSE WIDTH
FIGURE SWITCHING TIME TEST CIRCUIT
FIGURE RESISTIVE SWITCHING WAVEFORMS
HUF75333G3, HUF75333P3, HUF75333S3S PSPICE Electrical Model
.SUBCKT HUF75333
1.8e-9 1.73e-9 1.19e-9
02/24/99
LDRAIN DPLCAP RLDRAIN DBREAK EBREAK DRAIN RSLC1 ESLC
RSLC2
EBREAK 58.85 EVTHRES EVTEMP LDRAIN 1e-9 LGATE 1e-9 LSOURCE 1e-9 LSOURCE LGATE 0.0085 MMED MMEDMOD MSTRO MSTROMOD MWEAK MWEAKMOD RBREAK RBREAKMOD RDRAIN RDRAINMOD 4.50e-3 RGATE RLDRAIN RLGATE RLSOURCE RSLC1 RSLCMOD 1e-6 RSLC2 RSOURCE RSOURCEMOD 5.95e-3 RVTHRES RVTHRESMOD RVTEMP RVTEMPMOD S1AMOD S1BMOD S2AMOD S2BMOD
GATE
LGATE EVTEMP RGATE EVTHRES
RLGATE
MSTRO LSOURCE RSOURCE RLSOURCE SOURCE
VBAT ESLC .MODEL DBODYMOD 1.3e-12 =0.003 TRS1 2.7e-3 TRS2 7e-7 1.7e-9 40e-8 0.45 IKF= XTI= .MODEL DBREAKMOD 0.1e-1 TRS1 -4e-4 TRS2 1.55e-5 IKF= 1e-5) .MODEL DPLCAPMOD (CJO 1.8e-9 1e-30 1.45) .MODEL MMEDMOD NMOS (VTO 3.183 1e-30 .MODEL MSTROMOD NMOS (VTO 3.66 51.5 1e-30 .MODEL MWEAKMOD NMOS (VTO 2.703 0.008 1e-30 .MODEL RBREAKMOD (TC1 1.05e-3 4.5e-7) .MODEL RDRAINMOD (TC1 1.16e-2 1.7e-5) .MODEL RSLCMOD (TC1 3.96e-3 2.7e-6) .MODEL RSOURCEMOD (TC1 1e-3 1e-5) .MODEL RVTHRESMOD -2.8e-3 -1.0e-6) .MODEL RVTEMPMOD (TC1 -2.75e-3 0.5e-6) .MODEL S1AMOD VSWITCH (RON 1e-5 .MODEL S1BMOD VSWITCH (RON 1e-5 .MODEL S2AMOD VSWITCH (RON 1e-5 .MODEL S2BMOD VSWITCH (RON 1e-5 .ENDS ROFF ROFF ROFF ROFF VOFF= VOFF= VOFF= 0.5) VOFF=
NOTE: further discussion PSPICE model, consult PSPICE Sub-Circuit Power MOSFET Featuring Global Temperature Options; IEEE Power Electronics Specialist Conference Records, 1991, written William Hepp Frank Wheatley.
DBODY DBODYMOD DBREAK DBREAKMOD DPLCAP DPLCAPMOD
RDRAIN
DBODY
MWEAK MMED
RBREAK RVTEMP
VBAT
RVTHRES
HUF75333G3, HUF75333P3, HUF75333S3S SABER Electrical Model
August 1997 template huf75333 electrical iscl d.model dbodymod 1.3e-12, 1.7e-9, 40e-8, 0.45, vj=0.75) d.model dbreakmod d.model dplcapmod (cjo 1.8e-9, 1e-30, 0.9, 1.45, fc=0.5) m.model mmedmod (type=_n, 3.183, 1e-30, m.model mstrongmod (type=_n, 3.66, 51.5, 1e-30, DPLCAP m.model mweakmod (type=_n, 2.703, 8e-3, 1e-30, sw_vcsp.model s1amod (ron 1e-5, roff 0.1, voff sw_vcsp.model s1bmod (ron 1e-5, roff 0.1, voff sw_vcsp.model s2amod (ron 1e-5, roff 0.1, voff sw_vcsp.model s2bmod (ron 1e-5, roff 0.1, voff RSLC2 c.ca 1.8e-9 c.cb 1.73e-9 c.cin 1.19e-9 d.dbody model=dbodymod d.dbreak model=dbreakmod d.dplcap model=dplcapmod i.it l.ldrain 1e-9 l.lgate 1e-9 l.lsource 1e-9
GATE RLGATE LGATE EVTEMP RGATE MSTRO
LDRAIN RLDRAIN RDBREAK DBREAK MWEAK MMED EBREAK RDBODY DRAIN RSLC1 ISCL
EVTHRES
RDRAIN
DBODY
LSOURCE RLSOURCE
SOURCE
m.mmed model=mmedmod, m.mstrong model=mstrongmod, m.mweak model=mweakmod, res.rbreak 1.07e-3, 4.5e-7 res.rdbody 3e-3, 2.7e-3, 7e-7 res.rdbreak 1.1e-1, -4e-4, -1.55e-5 res.rdrain 4.5e-3, 1.16e-2, 1.7e-5 res.rgate res.rldrain res.rlgate res.rlsource res.rslc1 1e-6, 3.96e-3, 2.7e-6 res.rslc2 res.rsource 5.95e-3, 1e-3, 1e-5 res.rvtemp -2.75e-3, 0.5e-6 res.rvthres -2.8e-3, -1e-6 spe.ebreak 58.85 spe.eds spe.egs spe.esg spe.evtemp spe.evthres sw_vcsp.s1a model=s1amod sw_vcsp.s1b model=s1bmod sw_vcsp.s2a model=s2amod sw_vcsp.s2b model=s2bmod v.vbat
RSOURCE RBREAK RVTEMP
VBAT
RVTHRES
equations (n51->n50) iscl iscl: v(n51,n50)
HUF75333G3, HUF75333P3, HUF75333S3S SPICE Thermal Model
January 1999 HUF75333 CTHERM1 4.9e-4 CTHERM2 4.5e-3 CTHERM3 6.0e-3 CTHERM4 8.5e-3 CTHERM5 1.0e-2 CTHERM6 5.0e-2 RTHERM1 6.0e-4 RTHERM2 6.8e-3 RTHERM3 3.3e-2 RTHERM4 9.7e-2 RTHERM5 3.3e-1 RTHERM6 3.6e-1
JUNCTION
RTHERM1
CTHERM1
RTHERM2
CTHERM2
SABER Thermal Model
SABER thermal model HUF75333 template thermal_model thermal_c ctherm.ctherm1 4.9e-4 ctherm.ctherm2 4.5e-3 ctherm.ctherm3 6.0e-3 ctherm.ctherm4 8.5e-3 ctherm.ctherm5 1.0e-2 ctherm.ctherm6 5.0e-2 rtherm.rtherm1 6.0e-4 rtherm.rtherm2 6.8e-3 rtherm.rtherm3 3.3e-2 rtherm.rtherm4 9.7e-2 rtherm.rtherm5 3.3e-1 rtherm.rtherm6 3.6e-1
RTHERM3
CTHERM3
RTHERM4
CTHERM4
RTHERM5
CTHERM5
RTHERM6
CTHERM6
CASE
Intersil semiconductor products manufactured, assembled tested under ISO9000 quality systems certification.
Intersil semiconductor products sold description only. Intersil Corporation reserves right make changes circuit design and/or specifications time without notice. Accordingly, reader cautioned verify that data sheets current before placing orders. Information furnished Intersil believed accurate reliable. However, responsibility assumed Intersil subsidiaries use; infringements patents other rights third parties which result from use. license granted implication otherwise under patent patent rights Intersil subsidiaries.
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4362.5 66A, 55V, 0.016 Ohm. N-Channel UltraFET Power MOSFETs

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