Ultrahigh Speed Driver with Inhibit Mode AD53040 39nF DATA DATA D
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FEATURES Driver Operation Driver Inhibit Function Edge Matching Guaranteed Industry Specifications Output Impedance >1.5 V/ns Slew Rate Variable Output Voltages ECL, CMOS High Speed Differential Inputs Maximum Flexibility Ultrasmall 20-Lead Package with Built-In Heat Sink APPLICATIONS Automatic Test Equipment Semiconductor Test Systems Board Test Systems Instrumentation Characterization Equipment
Ultrahigh Speed Driver with Inhibit Mode AD53040
39nF DATA DATA DRIVER VOUT VLDCPL TVCC VHDCPL 39nF
AD53040
THERM
PRODUCT DESCRIPTION
AD53040 complete high speed driver designed digital mixed-signal test systems. Combining high speed monolithic process with unique surface mount package, this product attains superb electrical performance while preserving optimum packaging densities long-term reliability ultrasmall 20-lead, package with built-in heat sink. Featuring unity gain programmable output levels with output swing capability less than AD53040 designed stimulate ECL, CMOS logic families. data rate capacity matched output impedance allows real-time stimulation these digital logic families. test devices, driver switched into high impedance state (Inhibit Mode), electrically removing driver from path. driver leakage current inhibit typically output charge transfer entering inhibit typically less than
AD53040 transition from HI/LO inhibit controlled through data inhibit inputs. input circuitry uses high speed differential inputs with common-mode range This allows direct interface precision differential timing simplicity stimulating driver from single ended CMOS logic source. analog logic HI/LO inputs equally easy interface. Typically requiring bias current, AD53040 directly coupled output digital-to-analog converter. AD53040 available 20-lead, package with built-in heat sink specified operate over ambient commercial temperature range -25°C +85°C.
REV.
Information furnished Analog Devices believed accurate reliable. However, responsibility assumed Analog Devices use, infringements patents other rights third parties which result from use. license granted implication otherwise under patent patent rights Analog Devices. Technology Way, P.O. 9106, Norwood, 02062-9106, U.S.A. Tel: 781/329-4700 World Wide Site: http://www.analog.com Fax: 781/326-8703 Analog Devices, Inc., 1999
(All specifications unless otherwise noted. temperature coefficients measured C-95 capacitor must connected between VHDCPL between VLDCPL.)
Parameter DIFFERENTIAL INPUT CHARACTERISTICS Input Swing (Data DATA, INH) (DATA, DATA) (INH, INH) (INH, INH) (Data, DATA) Bias Current REFERENCE INPUTS Bias Currents OUTPUT CHARACTERISTICS Logic High Range Units Volts Volts Volts Test Conditions
AD53040-SPECIFICATIONS
DATA DATA -0.05 +0.05 DATA DATA DATA DATA DATA IOUT VOUT CBYP Output DATA Output DATA
Logic Range Amplitude Absolute Accuracy Offset Gain Linearity Error Offset Gain Linearity Error Offset Output Resistance Output Leakage Dynamic Current Limit Static Current Limit
Volts Volts
-100 -100
-1.0
+100 +100 mV/°C +1.0
PSRR, Drive Mode DYNAMIC PERFORMANCE, DRIVE Propagation Delay Time Propagation Delay Delay Matching, Edge Edge Rise Fall Time Swing Swing Swing Rise Fall Time Swing Swing Swing Overshoot, Undershoot Preshoot
ps/°C
Measured 50%, +400 -400 Measured 50%, +400 -400 Measured 50%, +400 -400 Measured 20%-80%, Measured 10%-90%, Measured 10%-90%, Measured 20%-80%, Measured 10%-90%, Measured 10%-90%, Pulsewidth ns/7.5 ns/100
ps/°C ps/°C ps/°C Step
Settling Time Delay Change Pulsewidth
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AD53040
Parameter DYNAMIC PERFORMANCE, DRIVE (Continued) Minimum Pulsewidth Swing Swing Toggle Rate DYNAMIC PERFORMANCE, INHIBIT Delay Time, Active Inhibit Delay Time, Inhibit Active Spike Output Capacitance POWER SUPPLIES Total Supply Range Positive Supply Negative Supply Positive Supply Current Negative Supply Current Total Power Dissipation Temperature Sensor Gain Factor Units Test Conditions
Input, 10%/90% Output, Input, 10%/90% Output, -1.8 -0.8 VOUT Measured 50%, Measured 50%, Driver Inhibited
<200
µA/K
1.15
1.43
RLOAD VSOURCE
NOTES Connecting shorting decoupling capacitors ground will result destruction device. Specifications subject change without notice.
ABSOLUTE MAXIMUM RATINGS
Power Supply Voltage Inputs DATA, DATA, INH, DATA DATA, Outputs VOUT Short Circuit Duration Indefinite2 VOUT Range Inhibit Mode VHDCPL Connect Except Capacitor VLDCPL Connect Except Capacitor THERM Environmental Operating Temperature (Junction) +175°C Storage Temperature -65°C +150°C Lead Temperature (Soldering, sec)3 +260°C
NOTES Stresses above those listed under Absolute Maximum Ratings cause permanent damage device. This stress rating only; functional operation device these other conditions above those indicated operational sections this specification implied. Absolute maximum limits apply individually, combination. Exposure absolute maximum rating conditions extended periods affect device reliability. Output short circuit protection guaranteed long proper heat sinking employed ensure compliance with operating temperature limits. ensure lead coplanarity 0.002 inches) solderability, handling with bare hands should avoided device should stored environments (75°F 10°F) with relative humidity exceed 65%.
ORDERING GUIDE
Shipment Method, Quantity Package Shipping Container Option RP-20
Model
Package Description
AD53040KRP 20-Lead Power SOIC Tube, Pieces
CAUTION (electrostatic discharge) sensitive device. Electrostatic charges high 4000 readily accumulate human body test equipment discharge without detection. Although AD53040 features proprietary protection circuitry, permanent damage occur devices subjected high energy electrostatic discharges. Therefore, proper precautions recommended avoid performance degradation loss functionality.
WARNING!
SENSITIVE DEVICE
REV.
AD53040
FUNCTION DESCRIPTIONS CONFIGURATION
VHDCPL VOUT VLDCPL
Name
Number
Functional Description Positive Power Supply. Both pins should connected minimize inductance allow maximum speed operation. should decoupled with inductance capacitor. Negative Power Supply. Both pins should connected keep inductance down allow maximum speed operation. should decoupled with inductance capacitor. Device Ground. These pins should connected circuit board's ground plane pins. Analog Input that sets voltage level Logic driver. Determines driver output DATA DATA. Analog input that sets voltage level Logic driver. Determines driver output DATA DATA. Driver Output. nominal output impedance Internal supply decoupling output stage. This connected through minimum capacitors. Internal supply decoupling output stage. This connected through minimum capacitors. compatible input that control high impedance state driver. When INH, driver goes into high impedance state. compatible inputs that determines high state driver. Driver output high DATA DATA. Temperature Sensor Start-Up Pin. This should connected VCC. Temperature Sensor Output Pin. resistor (10K) should connected between THERM VCC. approximate temperature determined measuring current through resistor. typical scale factor µA/K. DATA
THERM TVCC
AD53040
VIEW (Not Scale) COPPER SLUG
DATA DATA
Table Driver Truth Table
DATA
Output State Hi-Z Hi-Z
Table Package Thermal Characteristics
VOUT VHDCPL
Flow,
VLDCPL
INH,
DATA, DATA
TVCC THERM
REV.
AD53040
APPLICATION INFORMATION Power Supply Distribution, Bypassing Sequencing
AD53040 draws substantial transient currents from power supplies when switching between states careful design power distribution bypassing obtaining specified performance. Supplies should distributed using broad, inductance traces (preferably) planes multilayered board with dedicated ground-plane layer. device's power supply pins should used minimize internal inductance presented part's bond wires. Each supply must bypassed ground with least capacitor; chipstyle capacitors preferable they minimize inductance. more greater) Tantalum capacitors board also advisable provide additional local energy storage. AD53040's current-limit circuitry also requires external bypass capacitors. Figure shows simplified schematic positive current-limit circuit. Excessive collector current output transistor creates voltage drop across resistor, which turns transistor Q48. diverts risingedge slew current, shutting down current mirror removing output stage's base drive. VHDCPL should bypassed positive supply with 0.039 capacitor, while VLDCPL (not shown) requires similar capacitor negative supply- these capacitors ensure that AD53040 doesn't current limit during normal output transitions full rated step size. Both capacitors must have minimumlength connections AD53040. Here again, chip capacitors ideal.
VPOS VHDCPL
Several points about current-limit circuitry should noted. First, limiting currents tightly controlled, they functions both absolute transistor VBES junction temperature; higher output current available lower junction temperatures. Second, essential connect VHDCPL capacitor positive supply (and VLDCPL capacitor negative supply)-failure causes considerable thermal stress current-limiting resistor(s) during normal supply sequencing ultimately cause them fail, rendering part nonfunctional. Finally, AD53040 appear function normally small output steps (less than both these capacitors absent, will exhibit excessive rise fall times steps larger amplitude. AD53040 does require special power-supply sequencing. However, good design practice dictates that digital analog control signals applied part before supplies stable. Violating this guideline will normally destroy part, active inputs draw considerable current until main supplies applied.
Digital Input Range Restrictions
Total range amongst digital signals (DATA, DATA, INH, INH) less than equal meet specified timing. device will function above with reduced performance absolute maximum limit. This performance degradation might noticed modes operation. possible transitions INH, VL), there only that would show degradation, usually delay time. Taken extreme, driver fail achieve proper output voltage, output impedance fail fully inhibit. example scenario that would work AD53040 part driven using single-ended CMOS. each differential input would tied +2.5 reference level logic voltages would applied other. This would meet Absolute Maximum Rating because differential however possible, example applied input applied DATA input. This difference exceeds limitation given above. Even using CMOS difference between logic high logic greater than equal which will properly work. only solution resistive dividers equivalent reduce voltage levels.
RISING-EDGE SLEW CONTROL CURRENT LEVEL-SHIFTED LOGIC DRIVE
VNEG
5.12V
550mV /DIV
Figure Simplified Schematic AD53040 Output Stage Positive Current Limit Circuitry
-380mV 66.25ns
500ps/DIV
71.25ns
Figure Output Swing
REV.
AD53040
NOTE: TERMINATION CLOSE RECEIVER POSSIBLE. (END TRACE MARKED THROUGH CONNECTS BETWEEN MC10EL16 OUTPUTS DUT. VIAS ALLOWED VOUT LINE. VOUT MOUNTED SIDE BEST IMPEDANCE MATCH. DIMENSION BOARD 4-1/2 INCHES. PACKAGE CENTERED BOARD. RESISTORS NONELECTROLYTIC CAPS 0805-SIZE SURFACE MOUNT. DATA SHEET HIDDEN POWER GROUND PINS LOGIC GATES. 100nF BYPASS CAPACITORS LOCATED CLOSE PACKAGE. 4-LAYER WITH POWER INNER PLANES.
VLOW VHIGH DATA MC10EL16 -5.2V MC10EL16 -5.2V 0.01 DB15
SIDESMB TEST_LD
0.01
THERM TVCC
HQG1 VOUT 0.039
SIDESMB VOUT
AD53040
DATA 0.039
VLOW VHIGH THERM -5.2V
-5.2V
Figure Evaluation Board Schematic
REV.
AD53040
OUTLINE DIMENSIONS
Dimensions shown inches (mm).
20-Lead Thermally Enhanced Small Outline Package (PSOP) (RP-20)
0.5118 (13.00) 0.4961 (12.60)
0.2992 (7.60) 0.2914 (7.40)
HEAT SINK
0.1890 (4.80) 0.4193 (10.65) 0.1791 (4.55) 0.3937 (10.00)
0.3340 (8.61) 0.3287 (8.35) 0.1043 (2.65) 0.0926 (2.35) 0.0118 (0.30) 0.0500 (1.27) 0.0040 (0.10) STANDOFF 0.0201 (0.51) SEATING 0.0500 (1.27) 0.0130 (0.33) PLANE 0.0057 (0.40) 0.0295 (0.75) 0.0098 (0.25)
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PRINTED U.S.A.
C3003b-0-11/99
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