2001, ver. Introduction University Program Design Laboratory

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2001, ver. Introduction University Program Design Laboratory

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University Program Design Laboratory Package
2001, ver.
Introduction
University Program Design Laboratory Package designed meet needs universities teaching digital logic design with state-ofthe-art development tools programmable logic devices (PLDs). package provides necessary tools creating implementing digital logic designs, including following features:
MAX+PLUS® version 10.1 Student Edition development software Education Board EPM7128S device 84-pin plastic J-lead chip carrier (PLCC) package EPF10K20 device board EPF10K70 device board 240-pin power quad flat pack (RQFP) package ByteBlasterMVparallel port download cable
MAX+PLUS Version 10.1 Student Edition Software
MAX+PLUS version 10.1 Student Edition software contains many features available commercial version MAX+PLUS software, including completely integrated design flow intuitive graphical user interface. This software supports schematic capture text-based hardware description language (HDL) design entry, including Altera® Hardware Description Language (AHDLTM), VHDL, Verilog HDL. also provides design programming, compilation, verification support devices supported MAX+PLUS BASELINE software including EPM7128S, EPF10K20 EPF10K70 devices. maximize learning, MAX+PLUS software includes complete instantly accessible on-line help. student version MAX+PLUS software freely distributed students installation their personal computers. information install MAX+PLUS version 10.1 Student Edition software your computer, "Software Installation" page
Altera Corporation
A-UG-UP1-01.1
University Program Design Laboratory Package
Education Board
Education Board stand-alone experiment board based Altera's leading device families: MAX® 7000 FLEX® 10K. simple design, when used with MAX+PLUS software, provides superior platform learning digital logic design using high-level development tools PLDs. Education Board designed meet needs educator design laboratory environment. Education Board supports both product-term based look-up table (LUT)-based architectures includes PLDs. EPM7128S device programmed in-system with ByteBlasterMV download cable. EPF10K20 EPF10K70 devices configured in-system with either ByteBlasterMV download cable EPC1 configuration device (not included).
EPM7128S Device
EPM7128S device, mid-density member high-density, highperformance 7000S family, based EEPROM elements. EPM7128S device comes socket-mounted 84-pin PLCC package macrocells. Each macrocell programmable-AND/fixed-OR array well configurable register with independently programmable clock, clock enable, clear, preset functions. With capacity 2,500 gates simple architecture, EPM7128S device ideal introductory designs well larger combinatorial sequential logic functions.
more information 7000 devices, 7000 Programmable Logic Device Family Data Sheet.
EPF10K20 Device
EPF10K20 device, member Altera's high-density FLEX family, based reconfigurable SRAM elements. EPF10K20 device comes 240-pin RQFP package 1,152 logic elements (LEs) embedded array blocks (EABs). Each consists 4-input LUT, programmable flipflop, dedicated signal paths carry cascade functions. Each provides 2,048 bits memory, which used create RAM, ROM, first-in first-out (FIFO) functions. EABs also used implement logic functions, such multipliers, microcontrollers, state machines, digital signal processing (DSP) functions. With typical gate count 20,000 gates, EPF10K20 device ideal introductory digital design courses.
Altera Corporation
University Program Design Laboratory Package
EPF10K70 Device
EPF10K70 device based reconfigurable SRAM elements. EPF10K70 device available 240-pin RQFP package 3,744 EABs. Each consists 4-input LUT, programmable flipflop, dedicated signal paths carry-and-cascade functions. Each provides 2,048 bits memory, which used create RAM, ROM, first-in first-out (FIFO) functions. EABs also used implement logic functions, such multipliers, microcontrollers, state machines digital signal processing (DSP) functions. With typical gate count 70,000, EPF10K70 device ideal intermediate advanced digital design courses, including computer architecture, communications applications.
more information FLEX devices, FLEX Embedded Programmable Logic Family Data Sheet.
ByteBlasterMV Parallel Port Download Cable
Designs easily quickly downloaded into Education Board using ByteBlasterMV download cable, which hardware interface standard parallel port. This cable channels programming configuration data between MAX+PLUS software Education Board. Because design changes downloaded directly devices board, prototyping easy multiple design iterations accomplished quick succession.
Education Board Description
more information ByteBlasterMV download cable, ByteBlasterMV Parallel Port Download Cable Data Sheet. Education Board contains elements described this section. Figure shows block diagram Education Board.
Altera Corporation
University Program Design Laboratory Package
Figure Education Board Block Diagram
JTAG_IN MOUSE
MAX_EXPANSION
DEVICE
BOARD
DC_IN
FLEX_EXPAN_ FLEX_DIGIT
CONF_D POWER
EPC1
MAX_DIGIT JTAG_OUT
EPF10K20 EPF10K70
FLEX_PB1 FLEX_PB2 FLEX_SWITCH FLEX_EXPAN_
EPM7128S
MAX_SW1 MAX_SW2 MAX_PB1
MAX_PB2
FLEX_EXPAN_
DC_IN Power Input
DC_IN power input accepts 2.5-mm 5.55-mm female connector. acceptable input minimum power input consists holes connecting unregulated power source. hole marked with plus sign positive input; hole marked with minus sign board-common.
On-Board Voltage Regulator
on-board voltage regulator, LM340T, regulates positive input input consists holes connecting regulated power source. hole marked with plus sign positive input; hole marked with minus sign board-common. green light-emitting diode (LED) labeled POWER illuminated when current flowing from regulated power source.
Oscillator
Education Board contains 25.175-MHz crystal oscillator. output oscillator drives global clock input EPM7128S device (pin global clock input FLEX device (pin 91).
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University Program Design Laboratory Package
JTAG_IN Header
10-pin female plug ByteBlasterMV download cable connects with JTAG_IN 10-pin male header Education Board. Education Board provides power ground ByteBlasterMV download cable. Data shifted into devices shifted devices pin. Table identifies JTAG_IN names when ByteBlasterMV operating Joint Test Action Group (JTAG) mode. Table JTAG_IN 10-Pin Header Pin-Outs
JTAG Signal
Connect Connect Connect
Jumpers
Education Board contains four three-pin jumpers (TDI, TDO, DEVICE, BOARD) that JTAG configuration. JTAG chain variety configurations (i.e., program only EPM7128S device, configure only FLEX device, configure program both devices, connect multiple Education Boards together). Figure shows positions three connectors (C1, each four jumpers. Figure Position Connectors
DEVICE BOARD
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University Program Design Laboratory Package
Table defines settings each configuration. Table JTAG Jumper Settings Desired Action
Program EPM7128S device only Configure FLEX device only Program/configure both devices Connect multiple boards together Notes:
first device JTAG chain FLEX device, second device EPM7128S device. first device JTAG chain FLEX device, second device EPM7128S device. last board chain must single board configuration (i.e., programming only EPM7128S device, configuring only FLEX device, configuring/programming both devices). last board cannot connecting multiple boards together.
OPEN
DEVICE
BOARD
During configuration, green CONF_D will turn green will modulate indicate that data transferring. After device successfully configured, CONF_D will illuminate. information program configure EPM7128S, EPF10K20 EPF10K70 devices, "Programming Configuring Devices" page
EPM7128S Device
Education Board provides following resources EPM7128S device.
Socket-mounted 84-pin PLCC package Signal pins that accessible female headers JTAG chain connection ByteBlasterMV cable momentary push-button switches octal dual inline package (DIP) switches LEDs Dual-digit seven-segment display On-board oscillator (25.175 MHz) Expansion port with pins dedicated global CLR, OE1, OE2/GCLK2 pins
Altera Corporation
University Program Design Laboratory Package
pins from EPM7128S device pre-assigned switches LEDs board, instead connected female headers. With direct access pins, students concentrate design fundamentals learn about programmability pins PLDs. After successfully compiling verifying design with MAX+PLUS software, students easily connect assigned pins switches LEDs using common hook-up wire. Students then download their design into device compare their design's simulation actual hardware implementation.
EPM7128S Prototyping Headers
EPM7128S prototyping headers female headers that surround device provide access device's signal pins. pins each side 84-pin PLCC package connect 22-pin, dual-row 0.1-inch female headers. numbers EPM7128S device printed Education Board; indicates unassigned pin. Table lists numbers four female headers: power, ground, JTAG signal pins accessible through these female headers. Table Numbers Each Prototyping Header Outside
Note:
Inside refers female headers closest device; outside refers female headers furthest from device.
Note Inside
Inside
Outside
Inside
Outside
Outside
Inside
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University Program Design Laboratory Package
MAX_PB1 MAX_PB2 Push-Buttons
MAX_PB1 MAX_PB2 push-buttons that provide active-low signals pulled-up through 10-K resistors. Connections these signals easily made inserting hook-up wire into push-button female header. other hook-up wire should inserted into appropriate female header assigned EPM7128S device.
MAX_SW1 MAX_SW2 Switches
MAX_SW1 MAX_SW2 each contain eight switches that provide logiclevel signals. These switches pulled-up through 10-K resistors. Connections these signals easily made inserting hook-up wire into female header aligned with appropriate switch. other hook-up wire should inserted into appropriate female header assigned EPM7128S device. switch output logic when switch open logic when switch closed.
through LEDs
Education Board contains LEDs that pulled-up with 330- resistor. illuminated when logic applied female header associated with LED. LEDs through connected same sequence female headers (i.e., connected position connected position etc.). LEDs through connected same sequence female headers (i.e., connected position connected position etc.). Figure Figure Positions
Female Header Position
LEDs
Female Header Position
LEDs
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University Program Design Laboratory Package
MAX_DIGIT Display
MAX_DIGIT dual-digit, seven-segment display connected directly EPM7128S device. Each segment display illuminated driving connected EPM7128S device with logic Figure shows name each segment. Figure Display Segment Name
Digit
Digit
Decimal Point
Table lists assignments each segment. Table MAX_DIGIT Segment Connections Display Segment
Decimal point
Digit
Digit
MAX_EXPANSION
MAX_EXPANSION dual 0.1-inch spaced holes accessing signal pins global signals EPM7128S device, power, ground. Figure shows numbering convention holes.
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University Program Design Laboratory Package
Figure MAX_EXPANSION Numbering Convention
Education Board
MAX_EXPANSION
EPM7128S
Table lists signal names EPM7128S device pins connected each hole. Table MAX_EXPANSION Signal Names Device Connections (Part Hole Number
Signal/Pin
Connect Connect Connect OE1/84
Hole Number
Signal/Pin
Connect Connect GCLRn/1 OE2/GCLK2/2
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University Program Design Laboratory Package
Table MAX_EXPANSION Signal Names Device Connections (Part Hole Number
Signal/Pin
Hole Number
Signal/Pin
FLEX Device
Education Board provides following resources FLEX device. pins from FLEX device pre-assigned switches LEDs board.
JTAG chain connection ByteBlasterMV cable Socket EPC1 configuration device momentary push button switches octal switch Dual-digit seven-segment display On-board oscillator (25.175 MHz) port Mouse port Three expansion ports, each with pins seven global pins
FLEX_PB1 FLEX_PB2 Push-Buttons
FLEX_PB1 FLEX_PB2 push buttons that provide active-low signals general-purpose pins FLEX device. FLEX_PB1 connects FLEX_PB2 connects Each push button pulled-up through 10-K resistor.
FLEX_SW1 Switches
FLEX_SW1 contains eight switches that provide logic-level signals eight general-purpose pins FLEX device. input logic when switch open logic when switch closed. Table lists assignment each switch.
Altera Corporation
University Program Design Laboratory Package
Table FLEX_SW1 Assignments Switch
FLEX_SWITCH-1 FLEX_SWITCH-2 FLEX_SWITCH-3 FLEX_SWITCH-4 FLEX_SWITCH-5 FLEX_SWITCH-6 FLEX_SWITCH-7 FLEX_SWITCH-8
FLEX
FLEX_DIGIT Display
FLEX_DIGIT dual-digit, seven-segment display connected directly FLEX device. Each segment display illuminated driving connected FLEX device with logic Figure page name each segment. Table lists assignment each segment. Table FLEX_DIGIT Segment Connections Display Segment
Decimal point
Digit
Digit
Interface
interface allows FLEX device control external video monitor. This interface composed simple diode-resistor network 15-pin D-sub connector (labeled VGA), where monitor plug into Education Board. diode-resistor network Dsub connector designed generate voltages that conform standard.
Altera Corporation
University Program Design Laboratory Package
Information about color, row, column indexing screen sent from FLEX device monitor five signals. Three signals red, green, blue, while other signals horizontal vertical synchronization. Manipulating these signals allows images written monitor's screen. "VGA Driver Operation" page details interface operates.
Table lists D-sub connector FLEX device connections. Table D-Sub Connections Signal
GREEN BLUE HORIZ_SYNC VERT_SYNC Connect
D-Sub Connector
FLEX
Mouse Connector
mouse interface, which consists 6-pin mini-DIN connector, allows FLEX device receive data from PS/2 mouse PS/2 keyboard. Education Board provides power ground attached mouse keyboard. FLEX device outputs DATA_CLOCK signal mouse inputs data signal from mouse. Table lists signal names mini-DIN FLEX connections. "Mouse Interface Operation" page details mouse interface operates.
Table Mouse Connections Mouse Signal
MOUSE_CLK MOUSE_DATA
Mini-DIN
FLEX
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University Program Design Laboratory Package
FLEX_EXPAN_A, FLEX_EXPAN_B FLEX_EXPAN_C
FLEX_EXPAN_A, FLEX_EXPAN_B, FLEX_EXPAN_C dual rows 0.1-inch spaced holes accessing signal pins global signals FLEX device, power, ground. Figure shows numbering convention these holes. Figure FLEX_EXPAN_A, FLEX_EXPAN_B FLEX_EXPAN_C Numbering Convention
Education Board
AN_C
1113
Tables through list signal name FLEX device connected each hole. Table FLEX_EXPAN_A Signal Names Device Connections (Part Hole Number
Signal/Pin
Connect DI2/92 DI4/212 DEV_OE/213
Hole Number
FLEX_EXP
Signal/Pin
DI1/90 DI3/210 DEV_CLR/209 DEV_CLK2/211 Altera Corporation
University Program Design Laboratory Package
Table FLEX_EXPAN_A Signal Names Device Connections (Part Hole Number
Signal/Pin
Hole Number
Signal/Pin
Table FLEX_EXPAN_B Signal Names Device Connections (Part Hole Number
Signal/Pin
Connect DI2/92 DI4/212 DEV_OE/213
Hole Number
Signal/Pin
DI1/90 DI3/210 DEV_CLR/209 DEV_CLK2/211
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University Program Design Laboratory Package
Table FLEX_EXPAN_B Signal Names Device Connections (Part Hole Number
Signal/Pin
Hole Number
Signal/Pin
Table FLEX_EXPAN_C Signal Names Device Connections (Part Hole Number
Signal/Pin
Connect DI2/92 DI4/212 DEV_OE/213
Hole Number
Signal/Pin
DI1/90 DI3/210 DEV_CLR/209 DEV_CLK2/211
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University Program Design Laboratory Package
Table FLEX_EXPAN_C Signal Names Device Connections (Part Hole Number
Signal/Pin
Hole Number
Signal/Pin
Software Installation
This section describes install MAX+PLUS version 10.1 Student Edition software Windows Windows operating systems. After installation, students register obtain authorization code Altera world-wide site following URL:
complete installation instructions, refer read.me file MAX+PLUS 10.1 Student Edition CD-ROM MAX+PLUS Getting Started manual.
Windows Windows
Follow steps shown below install MAX+PLUS version 10.1 Student Edition software your Insert MAX+PLUS 10.1 Student Edition CD-ROM into your CD-ROM drive. Choose (Start menu). Type: <CD-ROM drive>:\mp2_101se.exe click guided through installation procedure.
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University Program Design Laboratory Package
Programming Configuring Devices
Programming configuring devices Education Board requires setting on-board jumpers JTAG programming options MAX+PLUS software, connecting ByteBlasterMV download cable PC's parallel port JTAG_IN connector Education Board. This section describes these options perform following actions:
Program only EPM7128S device Configure only EPF10K20 EPF20K70 device Configure/program both devices Connect multiple Education Boards together chain
EPM7128S Programming
This section describes procedures programming only EPM7128S device, (i.e., on-board jumpers, connect ByteBlasterMV download cable, options MAX+PLUS software).
Setting On-Board Jumpers EPM7128S Programming
program only EPM7128S device JTAG chain, jumpers TDI, TDO, DEVICE, BOARD shown Figure Figure Jumper Settings Programming Only EPM7128S Device
DEVICE BOARD
Connecting ByteBlasterMV Download Cable EPM7128S Programming
Attach ByteBlasterMV cable directly PC's parallel port JTAG_IN connector Education Board. more information setting ByteBlasterMV cable, ByteBlasterMV Parallel Port Download Cable Data Sheet.
Setting JTAG Options MAX+PLUS EPM7128S Programming
following steps describe MAX+PLUS software program EPM7128S device JTAG chain. more information MAX+PLUS software, MAX+PLUS Help.
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University Program Design Laboratory Package
Turn Multi-Device JTAG Chain command (JTAG menu) MAX+PLUS Programmer program device. Follow this procedure even only programming device. Choose Multi-Device JTAG Chain Setup (JTAG menu). Select EPM7128S Device Name drop-down list Multi-Device JTAG Chain Setup dialog box. Type name programming file EPM7128S device Programming File Name box. Select Programming File button also used browse your computer's directory structure locate appropriate programming file. Click device associated programming file Device Names Programming File Names box. number left device name shows order device JTAG chain. device's associated programming file displayed same line device name. programming file associated with device, "<none>" displayed next device name. Click Detect JTAG Chain Info have ByteBlasterMV cable check device count, JTAG code, total instruction length JTAG chain. message just above Detect JTAG Chain Info button reports information detected ByteBlasterMV cable. must manually verify that this message matches information Device Names Programming File Names box. Click Save JCF. Save dialog box, type name file File Name then select desired directory Directories save current settings JTAG Chain File (.jcf) future use. Click Click save your changes. Click Program MAX+PLUS Programmer.
EPF10K20 EPF10K70 Configuration
This section describes procedures configuring only EPF10K20 EPF10K70 devices, (i.e., on-board jumpers, connect ByteBlasterMV download cable, options MAX+PLUS software).
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University Program Design Laboratory Package
Setting On-Board Jumpers EPF10K20 EPF10K70 Configuration
configure only EPF10K20 EPF10K70 device JTAG chain, jumpers TDI, TDO, DEVICE, BOARD shown Figure Figure Jumper Settings Configuring Only FLEX Device
DEVICE BOARD
Connecting ByteBlasterMV Download Cable EPF10K20 EPF10K70 Configuration
Attach ByteBlasterMV cable directly PC's parallel port JTAG_IN connector Education Board. more information setting ByteBlasterMV cable, ByteBlasterMV Parallel Port Download Cable Data Sheet.
Setting JTAG Options MAX+PLUS Software EPF10K20 EPF10K70 Configuration
following steps describe MAX+PLUS software configure EPF10K20 EPF10K70 device JTAG chain. more information configure device, MAX+PLUS Help. Turn Multi-Device JTAG Chain command (JTAG menu) MAX+PLUS Programmer configure EPF10K20 EPF10K70 devices. Follow this step even only programming device. Choose Multi-Device JTAG Chain Setup (JTAG menu). Select EPF10K20 EPF10K70 Device Name drop-down list Multi-Device JTAG Chain Setup dialog box. Type name programming file EPF10K20 EPF10K70 device Programming File Name box. Select Programming File button also used browse your computer's directory structure locate appropriate programming file.
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University Program Design Laboratory Package
Click device associated programming file Device Names Programming File Names box. number left device name shows order device JTAG chain. device's associated programming file displayed same line device name. programming file associated with device, "<none>" displayed next device name. Click Detect JTAG Chain Info have ByteBlasterMV cable check device count, JTAG code, total instruction length JTAG chain. message just above Detect JTAG Chain Info button reports information detected ByteBlasterMV cable. must manually verify that this message matches information Device Names Programming File Names box. Click Save save current settings future use. Type name file File Name then select desired directory Directories Save dialog box. Click Click save your changes. Click Configure MAX+PLUS Programmer.
Configure/Program Both Devices
This section describes procedures configuring/programming both FLEX EPM7128S devices JTAG chain, (i.e., on-board jumpers, connect ByteBlasterMV download cable, options MAX+PLUS software).
Setting On-Board Jumpers Configuring/Programming Both Devices
configure program FLEX EPM7128S devices multi-device JTAG chain, jumpers TDI, TDO, DEVICE, BOARD shown Figure Figure Jumper Settings Configuring/Programming Both Devices
DEVICE BOARD
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University Program Design Laboratory Package
Connecting ByteBlasterMV Download Cable Configuring Programming Both Devices
Attach ByteBlasterMV cable directly PC's parallel port JTAG_IN connector Education Board. more information setting ByteBlasterMV cable, ByteBlasterMV Parallel Port Download Cable Data Sheet.
Setting JTAG Options MAX+PLUS Software Configuring Programming Both Devices
following steps describe MAX+PLUS software configure program both devices multi-device JTAG chain. more information program configure device, MAX+PLUS Help. Turn Multi-Device JTAG Chain command (JTAG menu). Choose Multi-Device JTAG Chain Setup (JTAG menu). Select first target device name Device Name drop-down list Multi-Device JTAG Chain Setup dialog box. Type name programming file device listed Device Name Programming File Names box. Select Programming File button also used browse your computer's directory structure locate appropriate programming file. Click device associated programming file Device Names Programming File Names box. number left device name shows device's order JTAG chain. device's associated programming file displayed same line device name. programming file associated with device, "<none>" displayed next device name. Repeat steps through information each device JTAG chain. Click Detect JTAG Chain Info have ByteBlasterMV cable check device count, JTAG code, total instruction length multi-device JTAG chain. message just above Detect JTAG Chain Info button reports information detected ByteBlasterMV cable. must manually verify that this message matches information Device Names Programming File Names box.
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University Program Design Laboratory Package
Click Save save current settings future use. Type name file File Name then select desired directory Directories box. Click Click save changes.
Click Configure MAX+PLUS Programmer configure FLEX devices JTAG chain. Then, click Program program EPM7128S devices JTAG chain.
Connect Multiple Education Boards Together Chain
This section describes procedures connecting multiple Education Boards together, (i.e., on-board jumpers, connect ByteBlasterMV download cable, options MAX+PLUS software).
Setting On-Board Jumpers Connecting Multiple Education Boards Together
configure/program EPM7128S FLEX devices multiple Education Boards connected multi-device JTAG chain, jumpers TDI, TDO, DEVICE, BOARD boards except last board chain shown Figure Figure Jumper Settings Boards Except Last Board Chain
DEVICE BOARD
last Education Board chain configure program both devices. However, BOARD jumper must shown Figure
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University Program Design Laboratory Package
Figure Jumper Settings Last Board Chain TDI, TDO, DEVICE settings depend which configuration use.
DEVICE BOARD
Connecting ByteBlasterMV Download Cable Connecting Multiple Education Boards Together
Attach ByteBlasterMV cable directly your PC's parallel port JTAG_IN connector Education Board.
more information setting ByteBlasterMV cable, ByteBlasterMV Parallel Port Download Cable Data Sheet.
Setting JTAG Options MAX+PLUS Software Connecting Multiple Education Boards Together
information JTAG options MAX+PLUS software, "Setting JTAG Options MAX+PLUS Software Configuring Programming Both Devices" page
Driver Operation
standard monitor consists grid pixels that divided into rows columns. monitor typically contains rows, with pixels row, shown Figure Each pixel display various colors, depending state red, green, blue signals. Figure Monitor
pixels (0,0)
pixels
(640, 480)
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University Program Design Laboratory Package
Each monitor internal clock that determines when each pixel updated. This clock operates VGA-specified frequency 25.175 MHz. monitor refreshes screen prescribed manner that partially controlled horizontal vertical synchronization signals. monitor starts each refresh cycle updating pixel left-hand corner screen, which treated origin plane (see Figure 12). After first pixel refreshed, monitor refreshes remaining pixels row. When monitor receives pulse horizontal synchronization, refreshes next pixels. This process repeated until monitor reaches bottom screen. When monitor reaches bottom screen, vertical synchronization pulses, causing monitor begin refreshing pixels screen (i.e., [0,0]).
Timing
monitor work properly, must receive data specific times with specific pulses. Horizontal vertical synchronization pulses must occur specified times synchronize monitor while receiving color data. Figures show timing waveforms color information with respect horizontal vertical synchronization signals. Figure Horizontal Refresh Cycle
RED, GREEN, BLUE
HORIZ_SYNC
Parameters Time
31.77
3.77
1.89
25.17
0.94
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University Program Design Laboratory Package
Figure Vertical Refresh Cycle
Horizontal Refresh Cycles
RED, GREEN, BLUE VERT_SYNC
Parameters Time
16.6
1.02
15.25
0.35
frequency operation number pixels that monitor must update determines time required update each pixel, time required update whole screen. following equations roughly calculate time required monitor perform functions. Tpixel 1/fCLK =B+C+D+E (Tpixel pixels) guard bands 31.77 O=P+Q+R+S (TROW rows) guard bands 16.6 Tpixel fCLK TROW Tscreen Time required update pixel 25.175 Time required update Time required update screen Guard bands Guard bands
TROW Tscreen Where:
monitor writes screen sending red, green, blue, horizontal synchronization, vertical synchronization signals when screen expected location. Once timing horizontal vertical synchronization signals accurate, monitor only needs keep track current location, send correct color data pixel.
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University Program Design Laboratory Package
Mouse Interface Operation
connect mouse Education Board 6-pin mini-DIN connector. data sent using synchronous serial protocol, transmission controlled DATA signals. During non-transmission, logic DATA either logic logic Each transmission contains start bit, eight data bits, parity, stop bit. Data transmission starts from least significant (LSB), i.e., sequence transmission start bit, DATA0 through DATA7, parity, stop bit. Start bits logic stop bits logic Each clock period µsec; data transition falling edge clock µsec. Table shows data packet format.
Table Data Packet Format Packet Number
Note:
Where:
Note
Left button state left mouse button pressed down) Right button state right mouse button pressed down) Movement direction Movement direction Movement data sign negative) Movement data overflow overflow occurred)
mouse operates Cartesian coordinate system (i.e., moving right positive, moving left negative, moving positive, moving down negative). magnitude movement function mouse's rate movement. faster mouse moves, greater magnitude.
Revision History
information contained University Program Design Laboratory Package User Guide version supersedes information published previous versions.
Version Changes
Version contains following changes:
Updated references ByteBlaster download cable ByteBlasterMV download cable Added information about EPF10K70 device
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University Program Design Laboratory Package User Guide
Text changes were made reflect current MAX+PLUS Windows software versions
Version 1.02 Changes
Version 1.02 contains following changes:
Text changes were made reflect current MAX+PLUS Windows software versions. Installation instructions Windows Windows 3.51 were removed. Table updated reflect correct labels holes 33-36, 49-52.
Version 1.01 Changes
Version 1.01 contains following changes:
Tables were updated reflect correct labels Hole Table updated reflect correct number Hole
Innovation Drive Jose, 95134 (408) 544-7000 http://www.altera.com University Program: university@altera.com Literature Services: (888) 3-ALTERA lit_req@altera.com
Altera, MAX, MAX+PLUS, MAX+PLUS 7000S, EPM7128S, FLEX, FLEX 10K, EPF10K20, EPF10K70, ByteBlasterMV, EPC1, AHDL trademarks and/or service marks Altera Corporation United States other countries. Altera acknowledges trademarks other organizations their respective products services mentioned this document. Altera products protected under numerous U.S. foreign patents pending applications, maskwork rights, copyrights. Altera warrants performance semiconductor products current specifications accordance with Altera's standard warranty, reserves right make changes products services time without notice. Altera assumes responsibility liability arising application information, product, service described herein except expressly agreed writing Altera Corporation. Altera customers advised obtain latest version device specifications before relying published information before placing orders products services. Copyright 2001 Altera Corporation. rights reserved.
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2001, ver. Introduction University Program Design Laboratory

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