February 2001 User Guide Version Innovation Drive Jose, 95134 (40

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February 2001 User Guide Version Innovation Drive Jose, 95134 (40

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Mapper MegaCore Function T3MAP
February 2001 User Guide Version
Innovation Drive Jose, 95134 (408) 544-7000 http://www.altera.com
A-UG-IPT3MAPPER-1.0
Mapper MegaCore Function (T3MAP) User Guide
Altera, APEX, APEX 20K, APEX 20KE, MegaCore, MegaWizard, OpenCore, Quartus, Quartus trademarks and/or service marks Altera Corporation United States other countries. Altera Corporation acknowledges trademarks other organizations their respective products services mentioned this document, including following: Verilog registered trademark Cadence Design Systems, Incorporated. Java trademark Microsystems Inc. Microsoft registered trademark Windows trademark Microsoft Corporation. Altera products protected under numerous U.S. foreign patents pending applications, maskwork rights, copyrights. Altera warrants performance semiconductor products current specifications accordance with Altera's standard warranty, reserves right make changes products services time without notice. Altera assumes responsibility liability arising application information, product, service described herein except expressly agreed writing Altera Corporation. Altera customers advised obtain latest version device specifications before relying published information before placing orders products services. Copyright 2001 Altera Corporation. rights reserved.
Altera Corporation
About this User Guide
User Guide
This user guide provides comprehensive information about Altera® Mapper MegaCore® Function (T3MAP). Table shows user guide revision history. Table Revision History Revision
0.01 1.00
Date
January 2001
Description
Initial beta release this document
February 2001 Initial release this document
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Adobe Acrobat Find feature allows search contents file. Click binoculars icon tool open Find dialog box, click right mouse button pull-down menu. Bookmarks serve additional table contents. Thumbnail icons, which provide miniature previews each page, provide link pages. Numerous links, shown green text, allow jump related information.
Altera Corporation
About this User Guide
Mapper MegaCore Function (T3MAP) User Guide
Contact Altera
most up-to-date information about Altera products, Altera world-wide site http://www.altera.com. additional information about Altera products, consult sources shown Table
Table Contact Altera Information Type
Altera Literature Services Non-technical customer service
Access
Electronic mail Telephone hotline
Canada
lit_req@altera.com (800) SOS-EPLD
Other Locations
lit_req@altera.com (408) 544-7000 (7:30 a.m. 5:30 p.m. Pacific Time) (408) 544-7606 (408) 544-7000 (7:30 a.m. 5:30 p.m. Pacific Time) (408) 544-6401 telecom@altera.com ftp.altera.com (408) 544-7104 http://www.altera.com
Technical support Telephone hotline
(408) 544-7606 (800) 800-EPLD (6:00 a.m. 6:00 p.m. Pacific Time) (408) 544-6401 telecom@altera.com ftp.altera.com (408) 544-7104 http://www.altera.com
Electronic mail site General product information Note:
Telephone World-wide site
also contact your local Altera sales office sales representative.
Altera Corporation
Mapper MegaCore Function (T3MAP) User Guide
About this User Guide
Typographic Conventions
Table Conventions Visual
Bold Type with Initial Capital Letters bold type
Mapper MegaCore Function (T3MAP) User Guide uses typographic conventions shown Table
Meaning
Command names, dialog titles, checkbox options, dialog options shown bold, initial capital letters. Example: Save dialog box. External timing parameters, directory names, project names, disk drive names, filenames, filename extensions, software utility names shown bold type. Examples: fMAX, \maxplus2 directory, drive, chiptrip.gdf file. Book titles shown bold italic type with initial capital letters. Example: 1999 Device Data Book. Document titles shown italic type with initial capital letters. Example: (High-Speed Board Design). Internal timing parameters variables shown italic type. Examples: tPIA, Variable names enclosed angle brackets shown italic type. Example: <file name>, <project name>.pof file. Keyboard keys menu names shown with initial capital letters. Examples: Delete key, Options menu. References sections within document titles Quartus MAX+PLUS Help topics shown quotation marks. Example: "Configuring FLEX FLEX 8000 Device with BitBlasterDownload Cable." Signal port names shown lowercase Courier type. Examples: data1, tdi, input. Active-low signals denoted suffix e.g., reset_n. Anything that must typed exactly appears shown Courier type. example: Also, sections actual file, such Report File, references parts files (e.g., AHDL keyword SUBDESIGN), well logic function names (e.g., TRI) shown Courier.
Bold italic type Italic Type with Initial Capital Letters Italic type
Initial Capital Letters "Subheading Title"
Courier type
c.,. Numbered steps used list items when sequence items important, such steps listed procedure. Bullets used list items when sequence items important. checkmark indicates procedure that consists step only. hand points information that requires special attention. angled arrow indicates should press Enter key. feet direct more information particular topic.
Altera Corporation
About this User Guide
Mapper MegaCore Function (T3MAP) User Guide
Abbreviations Acronyms
AHDL AIRbus ACDR FIFO Mbps SONET STS-1 T3FRM UTOPIA VHDL VHSIC
Altera Hardware Description Language Access Internal Registers interface Asynchronous Transfer Mode Clock Data Recovery Central Processing Unit Electronic Design Automation Embedded System Block First First Intellectual Property Logic Element Least Significant Least Significant Byte Megabits second Most Significant Most Significant Byte Data Flag Frame Personal Computer Path Overhead Receive Synchronous Optical Network Synchronous Payload Envelope Synchronous Transport Signal level Framer MegaCore Function Transport Overhead Transmit Universal Test Operations Physical Interface AVoltage Controlled Oscillator VHSIC Hardware Description Language Very High Speed Integrated Circuit
Altera Corporation
Contents
User Guide
Specifications
General Description MegaWizard Generated Files Features EXTRACT INSERT Functional Description EXTRACT Data Rate Data Byte Acceptance Destuffing Extraction INSERT Acceptance Asynchronous Mapping Stuffing Interfaces Protocols Midbus Receive Direction Transmit Direction AIRbus Mapper Interface Receive Transmit Performance Signals Software Interface Memory Registers INSERT Block Register Description INS_CTRL MAP_INSERT Control INS_STAT MAP_INSERT Status INS_IS MAP_INSERT Interrupt Status INS_IE MAP_INSERT Interrupt Enable INS_OH MAP_INSERT Overhead Communications Insert EXTRACT Block Register Description EXT_CTRL MAP_EXTRACT Control EXT_STAT MAP_EXTRACT Status EXT_IS MAP_EXTRACT Interrupt Status
Altera Corporation
Contents
Mapper MegaCore Function (T3MAP) User Guide
EXT_IE MAP_EXTRACT Interrupt Enable EXT_OH MAP_EXTRACT Overhead Communications Extract EXT_FIFO_HIGH MAP_EXTRACT FIFO High Mark EXT_FIFO_LOW MAP_EXTRACT FIFO Mark
Getting Started
Test-drive T3MAP Design Walkthrough Obtaining Installing T3MAP Installing MegaCore Files Generating Custom T3MAP Implementing System Compiling Performing Place Route Performing Synthesis Compilation Post-Routing Simulation Using Third-Party Tools Using Quartus Software Functional Simulations Using Visual Models Downloading Installing Visual Software Licensing Configuring Device
viii
Altera Corporation
Specifications
User Guide
General Description
Mapper MegaCore® Function (T3MAP) uses MegaWizard® Plug-In-within QuartusTMII software generate variants VHDL, AHDL, Verilog HDL, which instantiate into your design. Table shows optional features available T3MAP.
Specifications
Table Optional Features Options
Basic Configuration Note
Note Parameters
Choices
ESBs
numbers ESBs approximate Feb. 2001. Users strongly advised MegaWizard Plug-In Quartus software exact numbers T3MAP.
MegaWizard Generated Files
When finish going through wizard, generates following files:
following files-depending your tool selection- used instantiate T3MAP into your design: AHDL text design file (.tdf); VHDL design file (.vhd); Verilog design file (.v); Sample Verilog instantiation Black (_inst.v); Black module (_bb.v); Symbol files (.bsf) Quartus software used instantiate T3MAP into schematic design; encrypted netlist file (.e.vqm.v).
Altera Corporation
Specifications
Mapper MegaCore Function (T3MAP) User Guide
T3MAP complies with applicable standards, including: Telcordia, Synchronous Optical Network (SONET) Transport Systems: Common Generic Criteria, GR-253-CORE, Issue Revision January 1999.
T3MAP does support following features: SONET/SDH line path overhead processing; framing, including overhead processing; Translation maintenance signals between SONET (translation should performed software between T3FRM SONET overhead blocks); Automatic resynchronization after SONET pointer, events. (The T3MAP requires soft restart.)
Features
T3MAP interfaces data stream data rate 44.736 Mbps bps-via stuffing-to accommodate standard rates. While expected that input stream will within standard limits 44.736 Mbps bps, T3MAP supports rates between 44.712 Mbps 44.784 Mbps. T3MAP supports STS-1, STS-3, STS-12 data paths. comprises major blocks, EXTRACT INSERT-illustrated Figure
EXTRACT
Supports standard rate adaptive control external VCO-illustrated Figure FIFO buffer bytes deep. Accepts data bytes from SONET framer Performs destuffing Extracts stream, forwards optionally T3FRM
INSERT
Performs asynchronous mapping Uses 32-byte FIFO buffer Performs payload stuffing Provides payload bytes SONET framer Accepts stream that either from T3FRM
Altera Corporation
Mapper MegaCore Function (T3MAP) User Guide
Specifications
Figure illustrates T3MAP, including Midbus AIRbus interfaces. Figure Block Diagram
vco_decrease vco_increase
Specifications
ds3_txclk Mapper Interface
Midbus
mrxdat[7:0] mrxena mrxfoh mrxeoh mrxval rxclk_en rxclk rxreset_n
EXTRACT
ds3_txdata
T3MAP Mapper) mtxdat[7:0] mtxena mtxfoh mtxeoh mtxval
Midbus
ds3_rxclk INSERT ds3_rxdata
Mapper Interface
txclk_en txclk txreset_n
Altera Corporation
read dtack rdata[7:0] addr[3:0] wdata[7:0] AIRbus
Specifications
Mapper MegaCore Function (T3MAP) User Guide
Figure shows T3MAP providing asynchronous mapping data over STS1FRM. also depicts interface external VCO, purpose adjusting ds3_txclk clock. Figure Core Clocking
Low-Pass Filter vco_decrease vco_increase
rxclk mrxdat EXTRACT
ds3_txclk ds3_txdata
STS1FRM (SONET STS-1 Framer) txclk mtxdat
T3MAP Mapper)
INSERT INSERT
ds3_rxclk ds3_rxdata
Notes
Mapper also supports STS-3 STS-12 framers. more detailed view Midbus Figure
Functional Description
EXTRACT
Data Rate
T3MAP provides support standard rates maintaining adaptive control external VCO. this case, Phase Lock Loop (PLL) formed using FIFO buffer fill status phase comparator. FIFO buffer stores extracted data from SONET SPE. low-pass filter external core. software programmable threshold-either EXT_FIFO_HIGH EXT_FIFO_LOW-will assert either vco_increase vco_decrease when number bytes FIFO buffer below above those software registers. This indicates change required clock rate, ds3_txclk. "Core Clocking" page
vco_decrease indicates 32-byte FIFO buffer emptying clock should decrease. vco_increase indicates 32-byte FIFO buffer filling clock should increase.
Altera Corporation
Mapper MegaCore Function (T3MAP) User Guide
Specifications
Data Byte Acceptance
T3MAP accepts data bytes from SONET framer Midbus interface. "Midbus" page more details.
Destuffing
destuffing mechanism compensates frequency differences between SONET data paths.
Extraction
T3MAP extracts stream from input SONET SPE. T3MAP also capable forwarding stream T3FRM (optional). EXTRACT block extracts overhead communications bits from stores them register (EXT_OH). EXTRACT block synchronizes with Midbus when EXTRACT software enable (CTRL_ENABLE) register asserted. Synchronization status, EXTRACT block, kept EXT_STAT register.
Specifications
INSERT
Acceptance
T3MAP accepts stream, takes data from T3FRM with overhead intact (optional).
Asynchronous Mapping
order generate output conforming T3-SPE mapping, INSERT block takes data from internal 32-byte deep FIFO buffer containing data collected from Mapper interface. INSERT block also inserts software programmable overhead communication bits (INS_OH) into payload where designated T3-SPE standard. INSERT block synchronizes with Midbus when INSERT software enable (CTRL_ENABLE) register asserted. Synchronization status INSERT block kept INS_STAT register.
Altera Corporation
Specifications
Mapper MegaCore Function (T3MAP) User Guide
Stuffing
T3MAP stuffing mechanism compensates frequency differences between SONET data. T3MAP also handles SONET positive negative stuffing. This stuffing action performed SONET network compensate frequency differences within SONET network. SONET positive/negative stuffing, T3MAP stuffing mechanisms independent each other. SONET pointer event requires soft restart T3MAP. soft restart need toggle INSERT block control enable register, "INS_CTRL MAP_INSERT Control 'h0" page EXTRACT clock control enable register, "EXT_CTRL MAP_EXTRACT Control 'h5" page state detected T3MAP, reflects major movement position mapped data SONET stream requiring T3MAP resynchronize itself payload.
Interfaces Protocols
Three interfaces support T3MAP: Middle interface (Midbus), Access Internal Registers (AIRbus) interface, Mapper interface. These interfaces illustrated Figure
Midbus
Midbus interface simple synchronous full-duplex data path bus. T3MAP Midbus transports data over single-byte lane each direction. required frequency Midbus varies depending SONET framer supported-see Table Table Midbus Clocks Configuration
STS-1 STS-1x3 STS-1x12 Note:
case higher bandwidth interfaces, signals, txclk_en rxclk_en, used match data rate with clock rate. This column shows expected nominal duty cycle enable signal.
Clock Rate (MHz)
6.48 19.44 77.76
Clock Nominal Enable Rate (txclk_en rxclk_en)
Held active every clock Active: clocks Active: clocks
Altera Corporation
Mapper MegaCore Function (T3MAP) User Guide
Specifications
receive direction (RX), data transferred from Midbus master slave (T3MAP). transmit direction (TX), data transferred from slave (T3MAP) Midbus master. each direction Midbus carry eight bits clock cycle. includes midbus receive data (mrxdat[7:0]) midbus receive enable (mrxena) lines indicate valid data transfer direction, midbus transmit data (mtxdat[7:0]) midbus transmit enable (mtxena) lines indicate valid data request direction.
Receive Direction
Figure shows Midbus signals receive direction. T3MAP reads data mrxdat, rising edge rxclk. following position indicators also presented with data.
Specifications
mrxval indicates that following strobes valid, Figure mrxena indicates mrxdat user payload (PL) mrxfoh indicates mrxdat fixed frame overhead (A1, this includes section line overhead, undefined/growth. mrxeoh indicates mrxdat embedded frame overhead (J1, this includes path overhead.
Transmit Direction
Figure shows Midbus signals transmit direction, which provide position commands (listed below) that indicate type byte being processed next clock pulse.
mtxval indicates that following strobes valid, Figure mtxena indicates user payload mtxfoh indicates fixed frame overhead (A1, this includes section line overhead, undefined/growth mtxeoh indicates embedded frame overhead (J1, this includes path overhead
When enabled (INS_CTRL register) synchronized (INS_STAT register) T3MAP puts valid data mtxdat rising edge txclk, following asserted high mtxval.
Altera Corporation
Specifications
Mapper MegaCore Function (T3MAP) User Guide
Figures illustrate Midbus timing T3MAP interfacing STS-1 Framer. Figure T3MAP Receive Midbus Timing Diagram
rxclk rxdat rxena rxval rxfoh rxeoh
Figure T3MAP Transmit Midbus Timing Diagram
txclk txdat txena txval txfoh txeoh
AIRbus
AIRbus interface provides access internal registers using simple synchronous internal processor protocol. This consists separate read (rdata) write (wdata) data buses, data transfer acknowledge (dtack) signal, select (sel) signal. address (addr[3:0]) read (read) signal indicate location type access within block. rdata buses dtack signals merged from multiple blocks using simple function. dtack signal sustained until block removed (four-way handshaking) meaning AIRbus cross clock domain boundaries. T3MAP AIRbus slave with data width eight bits. internal registers current Midbus clock. Thus, EXTRACT side registers using rxclk (rxclk_en), INSERT side registers with txclk (txclk_en).
more detailed information Midbus AIRbus refer Altera site
Altera Corporation
Mapper MegaCore Function (T3MAP) User Guide
Specifications
Mapper Interface
Mapper interface used convey full data. T3MAP also provides users with option receiving transmitting framed data from/to Framer. stream, including overhead bits, then mapped into SONET framer asynchronously.
Receive
expected present ds3_rxdata signal rising edge ds3_rxclk-see Figure Figure Receive Mapper Timing Diagram
ds3_rxclk
Specifications
ds3_rxdat
Transmit
expected present ds3_txdata signal rising edge ds3_txclk-see Figure Figure Transmit Mapper Timing Diagram
ds3_txclk
ds3_txdat
Performance
Table shows required speed estimated gate count T3MAP APEX 20KE device. Table Performance
Notes:
numbers approximate Feb. 2001. T3MAP interfaces STS-12 line rate fMAX will 77.76 MHz.
Note ESBs
fMAX (MHz)
44.784 required
Altera Corporation
Specifications
Mapper MegaCore Function (T3MAP) User Guide
Signals
Table lists signals T3MAP.
Table Signals Port
Signals rxclk rxclk_en rxreset_n Signals txclk txclk_en txreset_n Midbus Signals mrxdat[7:0] mrxena mrxfoh mrxeoh mrxval mtxdat[7:0] mtxena mtxfoh mtxeoh mtxval AIRbus Signals read Input Input Select signal. When this signal goes high, selects internal registers Read/write control signal High: Reads data from data Low: Writes data data Interrupt request signal. When signal `1', this indicates interrupt request Data transfer acknowledge signal that comes from internal registers indicate internal registers ready send accept data Read data signals from internal register Register address Write data signals internal register Mapper Interface receive clock 44.736 Input Input Input Input Input Output Input Input Input Input Midbus receive data Midbus receive enable Midbus receive fixed overhead Midbus receive embedded overhead Midbus receive valid data Midbus transmit data Midbus transmit enable Midbus transmit fixed overhead Midbus transmit embedded overhead Midbus transmit valid data Input Input Input Transmit data clock Transmit clock enable Transmit active reset Input Input Input Receive data clock Receive clock enable Receive active reset
Direction
Description
dtack
Output Output
rdata[7:0] addr[3:0] wdata[7:0] ds3_rxclk
Output Input Input Input
Mapper Interface Signals
Altera Corporation
Mapper MegaCore Function (T3MAP) User Guide
Specifications
Table Signals Port
ds3_rxdata ds3_txclk
Direction
Input Input
Description
Mapper Interface receive data-serial stream Mapper Interface transmit clock 44.736 MHz. This clock controlled Mapper external Mapper Interface transmit data-serial stream This indicates extract block's FIFO buffer emptying clock rate should decreased This indicates extract block's FIFO buffer filling clock rate should increased
ds3_txdata
Output
Specifications
vco_decrease Output
vco_increase Output
Altera Corporation
Specifications
Mapper MegaCore Function (T3MAP) User Guide
Software Interface
Memory
addresses 8-bit accesses shown values. access addresses each register increment units since accesses bits wide. Address
Register
INS_CTRL INS_STAT INS_IS INS_IE INS_OH EXT_CTRL EXT_STAT EXT_IS EXT_IE EXT_OH
Description
MAP_INSERT Control MAP_INSERT Status MAP_INSERT Interrupt Status MAP_INSERT Interrupt Enable MAP_INSERT Overhead Communications Insert MAP_EXTRACT Control MAP_EXTRACT Status MAP_EXTRACT Interrupt Status MAP_EXTRACT Interrupt Enable MAP_EXTRACT Overhead Communications Extract
EXT_FIFO_HIGH MAP_EXTRACT FIFO High Mark EXT_FIFO_LOW MAP_EXTRACT FIFO Mark
Registers
following list access codes used describe type register bits. Code
RW1C RW0S RTCW RTSW RWTC RWTS RWSC RWSS Read/Write Read-Only Read/Write Clear Read/Write Read Clear Read Read Clear/Write Read Set/Write Read/Write value Clear Read/Write value Read/Write Self-Clearing Read/Write Self-Setting Unused bits/Read Unused bits/Read
Description
Altera Corporation
Mapper MegaCore Function (T3MAP) User Guide
Specifications
INSERT Block Register Description
INS_CTRL MAP_INSERT Control Field
ENABLE
Bits
Access
Function
When '0', MAP_INSERT produces static undefined output ('b1111 1111). Initially after rising edge MAP_INSERT will synchronize mtxefp, then produce valid output.
Default
INS_STAT MAP_INSERT Status Field
MAP_SYNC
Bits
Access
Function
When asserted, T3MAP been synchronized mtxeoh pulse.
Default
Specifications
INS_IS MAP_INSERT Interrupt Status Field
FIFO_CORRUPT STS_CORRUPT
Bits
Access
Function
indicates MAP_INSERT's internal FIFO either underflowed overflowed. indicates MAP_INSERT received mtxeoh/mtxena pattern that could handle ticks between strobes with enable intermediate). software resynchronization required.
Default
INS_IE MAP_INSERT Interrupt Enable Field
FIFO_CORRUPT STS_CORRUPT
Bits
Access
Function
This MAP_INSERT FIFO_CORRUPT interrupt enable.
Default
This MAP_INSERT STS_CORRUPT interrupt enable.
INS_OH MAP_INSERT Overhead Communications Insert Field
COMM_INSERT
Bits
Access
Function
This register controls overhead communications bits being inserted into byte
Default
Altera Corporation
Specifications
Mapper MegaCore Function (T3MAP) User Guide
EXTRACT Block Register Description
EXT_CTRL MAP_EXTRACT Control Field
ENABLE
Bits
Access
Function
Default
When '0', MAP_EXTRACT produces static undefined output ('b0). Initially after rising edge MAP_EXTRACT will synchronize mrxeoh, then produce valid output.
EXT_STAT MAP_EXTRACT Status Field
MAP_SYNC
Bits
Access
Function
When asserted, T3MAP been synchronized mrxeoh pulse.
Default
EXT_IS MAP_EXTRACT Interrupt Status Field
FIFO_CORRUPT STS_CORRUPT
Bits
Access
Function
Default
indicates MAP_EXTRACT register's internal FIFO either underflowed overflowed. indicates MAP_EXTRACT register received mrxeoh/mrxena pattern that could handle. software resynchronization required.
EXT_IE MAP_EXTRACT Interrupt Enable Field
FIFO_CORRUPT STS_CORRUPT
Bits
Access
Function
This MAP_EXTRACT FIFO_CORRUPT interrupt enable. This MAP_EXTRACT STS_CORRUPT interrupt enable.
Default
EXT_OH MAP_EXTRACT Overhead Communications Extract Field Bits Access
Function
Default
COMM_EXTRACT
These overhead communications bits extracted from byte
Altera Corporation
Mapper MegaCore Function (T3MAP) User Guide
Specifications
EXT_FIFO_HIGH MAP_EXTRACT FIFO High Mark Field
MARK
Bits
Access
Function
Default
This threshold value number bytes FIFO buffer. When number bytes FIFO buffer exceeds this value, FIFO buffer getting full. vco_increase signal then toggled ds3_txclk increased.
EXT_FIFO_LOW MAP_EXTRACT FIFO Mark Field
MARK
Function Default
Bits
Access
Specifications
This threshold value number bytes FIFO buffer. When number bytes FIFO buffer falls below this value, FIFO buffer getting empty. vco_decrease signal then toggled ds3_txclk decreased.
Altera Corporation
Notes:
Getting Started
User Guide
Test-drive T3MAP
This section describes obtain variant from Mapper MegaCore® Function (T3MAP). explains install T3MAP your walks through process implementing variant design. test-drive T3MAP using Altera® OpenCorefeature- within QuartusTMII software-to instantiate perform place-androute, perform static timing analysis, simulate using thirdparty simulator, within your custom logic. Only when ready generate programming files, need obtain licenses through your local Altera sales representative.
Getting Started
Design Walkthrough
This design walkthrough involves following steps: Obtaining installing T3MAP. Generating custom T3MAP your system using MegaWizard® Plug-In. Implementing rest your system using AHDL, VHDL, Verilog HDL. Compiling your design performing place-and-route. Licensing T3MAP configure device.
instructions assume that:
using familiar with Quartus software most current available version Quartus software installed default location using OpenCore feature test-drive T3MAP, have licensed
Altera Corporation
Getting Started
Mapper MegaCore Function (T3MAP) User Guide
Obtaining Installing T3MAP
order start using T3MAP, need obtain MegaCore package from your local Altera representative. package includes:
MegaWizard Plug-In Encrypted gate level netlist Place-and-route constraints (where necessary) Secure simulation model Sanity testbench Midbus AIRbus Interface Functional Specifications Data Sheet User Guide
Installing MegaCore Files
MegaWizard Plug-In generate files install them your following instructions describe this process. Before MegaWizard Plug-In, your must have Java runtime environment version installed. This file downloaded from Java site, http://www.java.sun.com.
Windows, follow instructions below: Click (Start Menu) Type <path name>\<filename>.exe, where <pathname> location downloaded T3MAP, <filename> filename T3MAP. Click MegaCore Installer dialog appears. Follow wizard instructions finish installation. After have finished installing files, must specify directory which installed them user library Quartus software. Search "User Libraries" Quartus Help instructions these libraries.
Altera Corporation
Mapper MegaCore Function (T3MAP) User Guide
GettingGetting Started
Generating Custom T3MAP
This section describes design flow using Altera T3MAP, Quartus development system. MegaWizard Plug-In Manager provided with T3MAP. MegaWizard Plug-In Manager-used within Quartus software- allows create, modify design files meet needs your application. them instantiate T3MAP your design file. create custom T3MAP using wizard, follow these steps: Start MegaWizard Plug-In choosing MegaWizard Plug-In Manager command (File menu) Quartus software. MegaWizard Plug-In Manager dialog displayed. Refer Quartus Help detailed instructions MegaWizard Plug-In Manager.
Getting Started
Specify that want create custom variant click Next. second page wizard, select T3MAP from folder. Choose type output files, specify folder name files wizard creates, click Next. Select optional parameters choices that require. final screen lists design files that wizard creates. Click Finish.
Implementing System Compiling Performing Place Route
Once have created your custom T3MAP, ready implement files generated MegaWizard your design. Quartus software, other tools create your design. Quartus software compile place-and-route your design. Refer Quartus Help instructions performing compilation. After have verified that your design functionally correct, ready perform system verification.
Performing Synthesis Compilation Post-Routing Simulation
Quartus software works seamlessly with tools from vendors, including: Cadence, Exemplar Logic, Mentor Graphics, Synopsys, Synplicity, Viewlogic. After have licensed T3MAP, generate EDIF, VHDL, Verilog HDL, Standard Delay Output Files from Quartus software them with your existing tools perform functional modeling post-route simulation your design.
Altera Corporation
Getting Started
Mapper MegaCore Function (T3MAP) User Guide
Using Third-Party Tools
synthesize your design third-party tool perform postroute simulation, follow these steps: Create your custom design instantiating T3MAP. Synthesize design using your third-party tool. Your tool should treat T3MAP black either setting attributes ignoring instantiation. After compilation, generate hierarchical netlist file your thirdparty tool. Open your netlist file Quartus software. pre-synthesized encrypted .e.vqm.v file from your working directory.
Using Quartus Software
Select Compile mode (Processing menu). Specify Compiler settings Compiler Settings dialog (Processing menu), Compiler Settings wizard. Specify user libraries project order which Compiler searches libraries. Specify input settings project. Choose Tool Settings (Project menu). Select Custom EDIF Design Entry/Synthesis Tool list. Click Settings. Tool Input Settings dialog box, make sure that relevant tool name option selected Design Entry/Synthesis Tool list. Depending type output file want, specify Verilog output settings VHDL output settings General Settings dialog (Project menu). 1993 VHDL Language option. pre-synthesized encrypted .e.vqm.v file from your working directory. Compile your design. Quartus Compiler synthesizes performs place-and-route your design, generates output programming files. Import your Quartus II-generated output files (.edo, .vho, .vo, .sdo) into your third-party tool post-route, device-level, system-level simulation.
Altera Corporation
Mapper MegaCore Function (T3MAP) User Guide
GettingGetting Started
Functional Simulations Using Visual Models
This section describes Visual Model verification provides instructions using Visual Models. Figure shows example Visual Model arrangement. Figure General Arrangement
(RTL) Hook-Up Visual Model Black Verilog VHDL Wrapper Empty Declaration User Design (RTL)
Getting Started
Utility (RTL)
Utility (RTL)
Utility (RTL)
level Visual Model treated sub-block design, main design unit.
Downloading Installing Visual Software
Visual software facilitates Visual simulation models allowing waveforms viewed using third-party simulation tools. view simulation model, must have Visual software installed your system. download software, instructions refer Altera site,
Licensing Configuring Device
After have compiled analyzed your design, ready configure your targeted Altera semiconductor device. evaluating T3MAP with OpenCore feature, must license function before generate programming files. obtain licence contact your local Altera sales representative. current T3MAP variants single license with ordering code: PLSM-T3MAP.
Altera Corporation
Notes:

February 2001 User Guide Version Innovation Drive Jose, 95134 (40

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