2001 User Guide Version 1.01 Innovation Drive Jose, 95134 (408) 5

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Framer MegaCore Function T3FRM
2001 User Guide Version 1.01
Innovation Drive Jose, 95134 (408) 544-7000 http://www.altera.com
A-UG-IPT3FRM-1.01
Framer MegaCore Function (T3FRM) User Guide
Altera, APEX, APEX 20K, MegaCore, MegaWizard, OpenCore, Quartus, Quartus trademarks and/or service marks Altera Corporation United States other countries. Altera Corporation acknowledges trademarks other organizations their respective products services mentioned this document. Altera products protected under numerous U.S. foreign patents pending applications, maskwork rights, copyrights. Altera warrants performance semiconductor products current specifications accordance with Altera's standard warranty, reserves right make changes products services time without notice. Altera assumes responsibility liability arising application information, product, service described herein except expressly agreed writing Altera Corporation. Altera customers advised obtain latest version device specifications before relying published information before placing orders products services. Copyright 2001 Altera Corporation. rights reserved.
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About this User Guide
User Guide
This user guide provides comprehensive information about Altera® Framer MegaCore® Function (T3FRM). Table shows user guide revision history.
Table Revision History
Revision
1.00 1.01
Date
2000 2001 First release
Description
First revision, added core verification summary
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Framer MegaCore Function (T3FRM) User Guide
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Framer MegaCore Function (T3FRM) User Guide
About this User Guide
Typographic Conventions
Table Conventions
Visual
Bold Type with Initial Capital Letters Bold type
Framer MegaCore Function (T3FRM) User Guide uses typographic conventions shown Table
Meaning
Command names, dialog titles, checkbox options, dialog options shown bold, initial capital letters. Example: Save dialog box. External timing parameters, directory names, project names, disk drive names, filenames, filename extensions, software utility names shown bold type. Examples: fMAX, \maxplus2 directory, drive, chiptrip.gdf file. Book titles shown bold italic type with initial capital letters. Example: 1999 Device Data Book. Document titles shown italic type with initial capital letters. Example: (High-Speed Board Design). Internal timing parameters variables shown italic type. Examples: tPIA, Variable names enclosed angle brackets shown italic type. Example: <file name>, <project name>.pof file. Keyboard keys menu names shown with initial capital letters. Examples: Delete key, Options menu. References sections within document titles Quartus MAX+PLUS Help topics shown quotation marks. Example: "Configuring FLEX FLEX 8000 Device with BitBlasterDownload Cable." Signal port names shown lowercase Courier type. Examples: data1, tdi, input. Active-low signals denoted suffix e.g., reset_n. Anything that must typed exactly appears shown Courier type. example: Also, sections actual file, such Report File, references parts files (e.g., AHDL keyword SUBDESIGN), well logic function names (e.g., TRI) shown Courier.
Bold italic type Italic Type with Initial Capital Letters Italic type
Initial Capital Letters "Subheading Title"
Courier type
c.,. Numbered steps used list items when sequence items important, such steps listed procedure. Bullets used list items when sequence items important. checkmark indicates procedure that consists step only. hand points information that requires special attention. angled arrow indicates should press Enter key. feet direct more information particular topic.
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About this User Guide
Framer MegaCore Function (T3FRM) User Guide
Abbreviations Acronyms
AHDL AIRbus B3ZS FEAC FEBE FIFO HDLC LAPD Mbps PMON PRBS SONET STS-1 VHDL VHSIC
Altera Hardware Description Language Application Identification Channel Access Internal Registers Interface Alarm Indication Signal Alternate Mark Inversion Bipolar Three Zero Substitution Cyclic Redundancy Check Digital Signal Level Digital Signal Level Embedded System Block Electronic Design Automation Excessive Zeros Alarm Control Block Errors First First High-Level Data Link Control Link Access Protocol Line Code Violation Logic Element Line Interface Unit Loss Signal Multiplex Megabits second Non-Return-to-Zero Frame Personal Computer Performance Monitor Pseudo Random Sequence Remote Defect Indication Register Transfer Level Receive Synchronous Optical Network Synchronous Payload Envelope Synchronous Transport Signal level Transmit VHSIC Hardware Description Language Very High Speed Integrated Circuit
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Contents
User Guide
About this User Guide
Find Information Contact Altera Typographic Conventions Abbreviations Acronyms
Specifications
General Description Functional Description RXFRMR B3ZS Decoding Dual Rail Single Rail Signals PMON Frame Searching Detection Parity Check Idle Signal C-bit Parity Functions Detection Application Receive FEAC Receive HDLC External Insertion TXFRMR B3ZS Encoding Dual Rail Single Rail Signals Frame Insertion Idle Signal C-bit Parity Functions Application Diagnostic Insertion Software Insertion C-bits Transmit FEAC Generator Transmit HDLC Generation Detection PRBS Receive Transmit Maintenance System Reset Interfaces Protocols Line Interface Midbus
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Contents
AIRbus Mapper Interface Receive Transmit Overhead Interface Performance Signals Software Interface Memory Registers Master Register Description MSTR_INT Master Interrupt Status MSTR_INT_EN Master Interrupt Enable RESERVED Reserved PRBS_CTRL PRBS control PRBS_INT PRBS Interrupt Status PRBS_INT_EN PRBS Interrupt Enable PRBS_THRES PRBS Threshold PRBS_ERR PRBS Error Counter TXFRMR Register Description TXFRMR_CTRL Transmit Framer control 'h10 TXFRMR_DIAG Transmit Framer Diagnostic 'h12. TFEAC Register Descriptions TFEAC_CTRL Transmit FEAC control 'h14 TFEAC_CODE Transmit FEAC Code 'h16 CINST1 C-Bit Insertion 'h18. CINST2 C-Bit Insertion 'h1A. THDLC Register Descriptions THDLC_CTRL Transmit HDLC Control 'h20. THDLC_STAT Transmit HDLC Status 'h22. THDLC_INT Transmit HDLC Interrupt Status 'h24. THDLC_INTR_EN Transmit HDLC Interrupt Enable 'h26 THDLC_FIFO_DATA Transmit HDLC FIFO Data Write 'h28. RXFRMR Register Description RXFRMR_CTRL Receive Framer Control 'h30 RXFRMR_STAT Receive Framer Status 'h32. RXFRMR_INT Receive Framer Interrupt Status 'h34 RXFRMR_INT_EN Receive Framer Interrupt Enable 'h36 RFEAC Register Descriptions RFEAC_CTRL Receive FEAC control 'h38 RFEAC_STAT Receive FEAC Status 'h3A RFEAC_INT Receive FEAC Interrupt Status 'h3C RFEAC_INT_EN Receive FEAC Interrupt Enable 'h3E. RFEAC_CODE Receive FEAC Code 'h40 Counter Register Descriptions LCVCTR Counter 'h42.
viii
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Contents
OOFCTR Counter 'h44 LOSCTR Counter 'h46. EXZCTR Counter 'h48. PERRCTR PERR Counter 'h4A. CPERRCTR CPERR Counter 'h4C FEBECTR FEBE Counter 'h4E. AISCTR Counter 'h50 RHDLC Register Descriptions RHDLC_CTRL Receive HDLC control 'h60 RHDLC_STAT Receive HDLC Status 'h62 RHDLC_INT Receive HDLC Interrupt Status 'h64. RHDLC_INT_EN Receive HDLC Interrupt Enable 'h66. RHDLC_FIFO_DATA Receive HDLC FIFO Data Read 'h68. Core Verification Summary Simulation Environment Compatibility Testing Environment
Getting Started
Test-Drive T3FRM with OpenCore Design Walkthrough Obtaining Installing T3FRM MegaWizard Generated Files Installing MegaCore Files Generating Custom T3FRM Implementing System Compiling Performing Place Route Performing Synthesis Compilation Post-Routing Simulation Using Third-Party Tools Using Quartus Software Functional Simulations Using Visual Models Downloading Installing Visual Software Licensing Configuring Device
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Notes:
Specifications
User Guide
General Description
Operating standard data rate 44.736 Mbps, Altera® Framer MegaCore® Function (T3FRM) supports unchannelized applications with C-bit parity functions, specialized applications. sub-blocks, receive framer (RXFRMR) transmit framer (TXFRMR) perform multiple functions, including: generation detection PRBS, FEAC detection insertion, B3ZS decoding encoding, generation detection control alarm codes. Performance monitoring (RXFRMR) achieved using interval counters accumulate: LCVs, FEBE events, AIS, LOS, EXZ, P-bit parity errors, C-bit parity errors, errors. RXFRMR also synchronizes frames unchannelized C-bit parity functions specialized applications, while TXFRMR generates frames these applications. Five interfaces support T3FRM functions. "Interfaces Protocols" page Table shows T3FRM optional features.
Specifications
Table Optional Features
Note
Options Parameters Choices
HDLC
1,614
ESBs
Basic Configuration
HDLC Controller-Transmit receive HDLC controllers with data FIFO buffer process overhead HDLC channel. Note:
numbers ESBs approximate 2001. Users strongly advised MegaWizard Plug-In, Quartus software exact numbers T3FRM.
optional HDLC terminates path maintenance data link accumulates data FIFO buffer inside RXFRMR inserts data path maintenance data link channel with data FIFO buffer inside TXFRMR. RXFRMR TXFRMR provide HDLC/LAPD frame generation processing.
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Specifications
Framer MegaCore Function (T3FRM) User Guide
T3FRM complies with applicable standards, including: Telcordia, Transport Systems Generic Requirements (TSGR): Common Requirements GR-499-CORE, Issue December 1998; American National Standards Institute, Digital Hierarchy-Formats Specifications T1.107-1995
Functional Description
This section provides detailed description T3FRM divided into RXFRMR TXFRMR functions. Figure complete block diagram T3FRM, detailing sub-blocks, RXFRMR TXFRMR; five interfaces.
Figure Block Diagram
rxreset_n rclk Line Interface rpdata rndata mrxdat[7:0] alos RCLK DOMAIN CLK44 DOMAIN txreset_n clk44 read wdata[15:0] addr[6:1] rdata[15:0] dtack mtxdat[7:0] mtxclk mtxena tohclk tohfp tohins txsclk txbit Overhead Interface AIRbus Interface mrxclk mrxena Midbus Interface rxsclk RXFRMR rxbit rohclk rohfp Overhead Interface Mapper Interface
tclk Line Interface tpdata tndata
TXFRMR
Midbus Interface
Mapper Interface
Notes
AIRbus interface provides access internal registers entire block. rndata pin. tndata pin.
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Framer MegaCore Function (T3FRM) User Guide
Specifications
RXFRMR
RXFRMR extracts overhead bits from incoming stream; this function compatible with C-bit parity format. frame dissected into distinct blocks information bits; each processed different functional blocks.
B3ZS Decoding Dual Rail Single Rail Signals
dual rail, B3ZS input signal, decoder decodes data, provides indications LCVs. single rail, input signal, separate input signal used indicate line code violations, which detected upstream B3ZS decoder. Figures illustrate dual rail single rail decoding scheme.
Specifications
Figure Receive Dual Rail Decoding Scheme
rclk rpdata rndata data
Figure Receive Single Rail Decoding Scheme
rclk rpdata
PMON
PMON provides internal interval counters RXFRMR register block measure persistent errors. PMON counters interface with RXFRMR accumulate erroneous events including: LCV, LOS, EXZ, P-bit parity error, C-bit parity error, FEAC, error, AIS, interval counters. PMON continues accumulate these events counters until software programmed read particular counter value. After read operation, counter cleared.
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Specifications
Framer MegaCore Function (T3FRM) User Guide
Frame Searching Detection
RXFRMR searches valid frames from incoming signal using F-bits M-bits. framing status reported internal status register. RXFRMR also detects defects incoming signals.
Parity Check
RXFRMR compares P-bits against parity results previous M-frame, calculates parity incoming frame, stores result comparison with next frame.
Idle Signal
incoming signal monitored AIS, idle signal. defect detected when signal consisting pattern, described below, received: signal valid M-frame alignment channel, M-subframe alignment channel, valid P-bits. information bits `b10 sequence. C-bits zero. X-bits idle signal valid M-frame alignment channel, M-subframe alignment channel, valid P-bits. information bits `b1100 sequence. C-bits zero M-subframe remaining C-bits take values.
C-bit Parity Functions
C-bit parity application software programmable. RXFRMR extracts C-bits with their respective functions. C-bits that constitute FEAC channel sent RFEAC block further processing. "Receive FEAC" page Similarly, C-bits that make path maintenance data link sent RHDLC block. "Receive HDLC" page RXFRMR also checks C-bit parity FEBEs. These errors, together with LCVs EXZs indications, accumulated PMON. "Receive Dual Rail Decoding Scheme" page C-bit parity functions disabled software. disabled, C-bits
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Framer MegaCore Function (T3FRM) User Guide
Specifications
Table lists various C-bit channel functions.
Table C-bit Channel Functions
M-Subframe
C-bit
C1C2C3 C1C2C3 C1C2C3 C1C2C3 C1C2C3 C1C2C3
Description
signal. indicate C-bit parity function. Reserved future use. Used FEAC signal. Unused. Combined with P-bits form five CP-bits parity. They should have same value P-bits. Used FEBE functions. Used HDLC/LAPD data link rate 28.2 kbps. Unused. Unused.
Specifications
Detection
both extracted X-bits detected reported internal status register. defect removed both extracted X-bits X-bits equal, status remains previous state.
Application
While T3FRM provides transparent transmission frames, does handle multiplexing, stuffing.The application selected software. RXFRMR monitors signal which toggles every M-frame frames reports result internal status register. Other C-bits ignored sent serial hardware overhead extraction insertion interface. Overhead Interface" page
Receive FEAC
RFEAC detects bit-oriented codes contained C-bit parity FEAC channel received from RXFRMR. FEAC codes received 16-bit sequences, each consisting eight 1's, code bits, trailing valid code detected, RFEAC block asserts corresponding FEAC interrupt status register. RFEAC block receives idle code valid code detected. software programmable feature allows interrupt generated when detected code been validated, when code removed.
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Specifications
Framer MegaCore Function (T3FRM) User Guide
Receive HDLC
RHDLC receives HDLC/LAPD frame bits from RXFRMR. also provides data link AIRbus receive maintenance information. RXFRMR handles framing, frame synchronization optional address matching. Processing address, control, information fields software programmable. RHDLC detects change from flag characters first byte data. then:
Removes stuffed zeros incoming data stream; Converts serial bits into bytes; Calculates CRC.
errors exist, records error HDLC status register. received data placed into 128x10 FIFO buffer. this data processed software. interrupt generated when complete message stored FIFO buffer. FIFO buffer reset cleared software. RHDLC generates interrupts from several sources which are: transmission abort, FIFO buffer half empty, FIFO buffer empty, error, message, FIFO buffer overrun. these events recorded interrupt status registers. FIFO buffer divided follows: bits data bits, Packet (eop), Start Packet (sop).
External Insertion
alos inject errors into incoming data. When alos held high continuously more cycles, RXFRMR should able detect LOS, assert RXFRMR register, generate interrupt, assert LOSI RXFRMR interrupt status register. counter will increment.
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Framer MegaCore Function (T3FRM) User Guide
Specifications
TXFRMR
TXFRMR inserts overhead bits into incoming payload stream, which compatible with C-bit parity format. TXFRMR performs following functions.
B3ZS Encoding Dual Rail Single Rail Signals
software programmable feature allows signal output single rail, signal, dual rail, B3ZS signal. dual rail interface, data encoded with B3ZS coding scheme. signal encoded compliance with coding scheme. Figures illustrate B3ZS dual rail single rail encoding scheme.
Specifications
Figure Transmit Dual Rail Encoding Scheme
tclk tpdata tndata Data
Figure Transmit Single Rail Encoding Scheme
tclk tpdata Start M-frame
Frame Insertion
TXFRMR receives payload data from Midbus interface. M-bits F-bits inserted into M-frame. parity payload data calculated stored next M-frame. Previous results parity calculations M-frames inserted P-bit position.
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Specifications
Framer MegaCore Function (T3FRM) User Guide
RXFRMR detects LOS, AIS. TXFRMR sets both X-bits `00' errors detected. Otherwise, both `11'. They software programmable internal register.
Idle Signal
idle signal inserted according status signals internal register software.
C-bit Parity Functions
C-bit parity application software programmable. TXFRMR inserts C-bits with their respective functions. CP-bits equivalent P-bits. FEBE indications detected RXFRMR status stored internal register.
Application
While T3FRM provides transparent transmission frames, does handle multiplexing, stuffing. application software programmable. TXFRMR toggles signal every M-frame. other C-bits forced unless they overridden hardware insertion-See Overhead Interface" page
Diagnostic Insertion
TXFRMR programmed insert erroneous events diagnostic purpose. These events are: FEBE, P-bit parity error, CP-bit parity error, M-bit error, LCV, LOS. insertion occurs when there transition from diagnostic control register.
Software Insertion C-bits
TXFRMR programmed insert C-bits setting control register. Values C-bits inserted programmed internal registers.
Transmit FEAC Generator
TFEAC Generator transmits codes C-bit parity FEAC channel TXFRMR. idle code used disable transmission other codes. FEAC channel disabled software, TFEAC block sends channel.
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Framer MegaCore Function (T3FRM) User Guide
Specifications
Transmit HDLC
THDLC provides serial data link C-bit parity HDLC/LAPD path maintenance data link. used microprocessor transmit HDLC data frames TXFRMR. THDLC disabled software, keeps sending while disabled. When enabled, continuously transmits flags (`b01111110) until data ready sent. THDLC automatically begins transmission data once least complete message moves into FIFO buffer. THDLC calculates CRC-16 values transmits these values after last byte data been sent. data then serialized flags inserted until next complete message available. FIFO buffer reset cleared software. FIFO buffer divided follows: bits data bits, Packet (eop), Start Packet (sop).
Specifications
THDLC stuffs into serial data output there more than five consecutive transmit data data. This prevents unintentional transmission flag abort sequences. Transmission aborted software setting control send abort sequence, `b01111111. THDLC generates interrupt when FIFO buffer full, half full, underflow occurred.
Generation Detection PRBS
Receive
receive side, PRBS detection software programmable. Software searches PRBS pattern from in-coming payload bits. Once number error-free bits from input reaches programmable threshold value, synchronization register set. Once synchronized, error incoming stream causes error counter increment. Following error, shift register re-filled during time which errors reported. Error reporting resumes when error been purged shift register contains payload data.
Transmit
transmit side, PRBS generation software programmable. Software generates pseudo random payload pattern with length 216-to-1. result back input first stage.
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Specifications
Framer MegaCore Function (T3FRM) User Guide
Maintenance
System Reset
T3FRM provides active reset pins both transmit, txreset_n, receive, rxreset_n. These pins asserted asynchronously, de-asserted synchronously.
Interfaces Protocols
Five interfaces-illustrated Figure 1-support T3FRM: Line interface, Midbus interface, Access Internal Registers (AIRbus) interface, Mapper interface, Overhead interface. Line interface accepts transmits data both single data rail encoded dual data rail. Midbus allows connection SONET framer. 16-bit synchronous microprocessor interface (AIRbus) provides control, maintenance, status monitoring capabilities. serial interface provides connection mapper receiving transmitting payload data. Overhead interface executes overhead extraction insertion. Each interface function detailed further this section. timing diagrams this section, implied that data busses changing state rising edge every clock. Only when nature data carried data busses changes there transition shown data bus.
Line Interface
T3FRM features both single rail dual rail interfaces that connect standalone line interface units, which allow transmission data from T3FRM. T3FRM Line interface slave. transceiver used interface between T3FRM wiring device. direction converts encoded digital signals into appropriate pulses transmission over cable. direction opposite action occurs.
Midbus
Midbus interface simple synchronous full-duplex data path bus. T3FRM Midbus runs approximately over single byte lane each direction. direction, data transferred from Midbus master, RXFRMR, slave. direction, data transferred from slave Midbus master, TXFRMR. each direction Midbus carry eight bits clock cycle. includes midbus receive data (mrxdat[7:0]) midbus receive enable (mrxena) lines indicate valid data transfers receive direction, midbus transmit data (mtxdat[7:0]) midbus transmit enable (mtxena) lines indicate valid data requests transmit direction.
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Framer MegaCore Function (T3FRM) User Guide
Specifications
Figures show example Midbus interface data receive transmit transactions.
Figure Receive Midbus Timing Diagram
mrxclk
Payload Bytes
mrxdat[7:0] mrxena
Specifications
Figure Transmit Midbus Timing Diagram
mtxclk mtxena mtxdat[7:0]
AIRbus
AIRbus interface provides access internal registers using simple synchronous internal processor protocol. This protocol consists separate read (rdata) write (wdata) data buses, data transfer acknowledge (dtack) signal, select (sel) signal. address (addr[6:1]) read (read) signal indicate location type access within block. rdata buses dtack signals merged from multiple blocks using simple function. dtack signal sustained until block removed (four-way handshaking) meaning AIRbus cross clock domain boundaries. T3FRM AIRbus slave with datawidth bits.
More detailed Midbus AIRbus interface information available from Altera site
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Specifications
Framer MegaCore Function (T3FRM) User Guide
Mapper Interface
T3FRM provides serial stream that interfaces with mapper. stream, including overhead bits, mapped into SONET STS-1 asynchronously Mapper interface. mapper responsible providing mechanism compensate frequency differences.
Receive
T3FRM sends bits mapper. Data presented rxbit signal T3FRM rising edge rxsclk. data then retrieved next rising edge rxsclk mapper.
Transmit
mapper transmits bits T3FRM. expected present txbit signal rising edge txsclk. This retrieved T3FRM next rising edge txsclk. Figures show example Mapper interface, receive transmit, transactions.
Figure Receive Mapper Timing Diagram
rxsclk rxbit
Figure Transmit Mapper Timing Diagram
txsclk txbit
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Framer MegaCore Function (T3FRM) User Guide
Specifications
Overhead Interface
T3FRM provides serial hardware interface insertion extraction overhead bits. This interface runs rate kHz. Overhead bits serially inserted frame using Overhead interface. TXFRMR receives overhead bits from interface overrides internally generated bits. Hardware insertion disabled software. This interface provides proper clocking framing serial interface. Figure shows insertion overhead bits.
Specifications
Figure Overhead Insertion Timing Diagram
tohclk tohfp tohins
Overhead bits extracted input from RXFRMR. RXFRMR extracts overhead bits sends them Overhead interface, which shifts overhead bits. interface provides proper clocking framing output overhead stream. Figure shows extraction overhead bits.
Figure Overhead Extraction Timing Diagram
rohclk rohfp
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Specifications
Framer MegaCore Function (T3FRM) User Guide
Performance
Table shows required speed estimated gate count T3FRM APEX 20KE device.
Table Performance
1,614 2,292 Note:
Note
ESBs
fMAX (MHz)
44.736 required
numbers approximate 2001. They reflect range from basic full feature variant.
Signals
following table lists signals T3FRM.
Table Signals (Part
Port Direction Description
Receive Line Interface Signals
rclk rpdata rndata rxsclk rxbit rohclk rohfp
Receive Midbus Signals
Input Input Input Input
Line receive clock nominal rate 44.736 Line receive positive data dual rail interface-NRZ output single rail interface. Line receive negative data dual rail interface Line code violation single rail signal
Receive Mapper Interface Signals Output Output Output Output Output Receive clock-serial stream Receive data-serial stream Receive overhead clock nominal rate 44.736 Receive overhead frame pulse Receive overhead data
mrxdat[7:0] mrxclk mrxena
clk44 Domain Signals
Output Output Output
Receive data Receive clock Receive enable
clk44 tclk
Input
External reference clock nominal rate 44.736
Transmit Line Interface Signals Output Line transmit clock nominal rate 44.736
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Framer MegaCore Function (T3FRM) User Guide
Specifications
Table Signals (Part
tpdata tndata txsclk Port txbit tohclk tohfp tohins
Transmit Midbus Signals Output Output Output Line transmit positive data dual rail interface. output single rail interface. Line transmit negative data dual rail interface. Start M-frame frame pulse single rail interface.
Transmit Mapper Interface Signals Output Transmit clock-serial stream
Direction
Input Output Output Input Input
Description
Transmit data-serial stream Transmit overhead clock Transmit overhead frame pulse Transmit overhead data Transmit overhead insertion enable
Specifications
mtxdat[7:0] mtxclk mtxena
AIRbus Signals
Input Output Output
Transmit data Transmit clock Transmit data enable
read wdata[15:0] addr[6:1] rdata [15:0] dtack
Maintenance Signals
Input Input Input Input Output Output Output
Read Select Write data Address Read data Data transfer acknowledge Interrupt request
rxreset_n txreset_n
Test Signals
Input Input
Active receive reset Active transmit reset
alos
Input
Hardware insertion
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Specifications
Framer MegaCore Function (T3FRM) User Guide
Software Interface
Memory
addresses 16-bit accesses shown values. Note that access addresses each register increment units since accesses bits wide.
Table Memory (Part
Address
'h10 'h12 'h14 'h16 'h18 'h1A 'h20 'h22 'h24 'h26 'h28 'h30 'h32 'h34 'h36 'h38 'h3A 'h3C
Register
MSTR_INT MSTR_INT_EN RESERVED PRBS_CTRL PRBS_INT PRBS_INT_EN PRBS_THRES PRBS_ERR TXFRMR_CTRL TXFRMR_DIAG TFEAC_CTRL TFEAC_CODE CINST1 CINST2 THDLC_CTRL THDLC_STAT THDLC_INT THDLC_INTR_EN THDLC_FIFO_DATA RXFRMR_CTRL RXFRMR_STAT RXFRMR_INT RXFRMR_INT_EN RFEAC_CTRL RFEAC_STAT RFEAC_INT
Description
Master Interrupt Status Master Interrupt Enable Reserved PRBS control PRBS Interrupt Status PRBS Interrupt Enable PRBS Threshold PRBS Error Counter Transmit Framer control Transmit Framer Diagnostic Transmit FEAC control Transmit FEAC Code C-Bit Insertion C-Bit Insertion Transmit HDLC control Transmit HDLC Status Transmit HDLC Interrupt Status Transmit HDLC Interrupt Enable Transmit HDLC FIFO Data Write Receive Framer control Receive Framer Status Receive Framer Interrupt Status Receive Framer Interrupt Enable Receive FEAC control Receive FEAC Status Receive FEAC Interrupt Status
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Framer MegaCore Function (T3FRM) User Guide
Specifications
Table Memory (Part
'h3E 'h40 'h42 'h44 'h46 'h48 'h4A 'h4C 'h4E 'h50 'h60 'h62 'h64 'h66 'h68 RFEAC_INT_EN RFEAC_CODE LCVCTR OOFCTR LOSCTR EXZCTR PERRCTR CPERRCTR FEBECTR AISCTR RHDLC_CTRL RHDLC_STAT RHDLC_INT RHDLC_INT_EN RHDLC_FIFO_DATA Receive FEAC Interrupt Enable Receive FEAC Code counter counter counter counter PERR counter CPERR counter FEBE Counter Counter Receive HDLC control Receive HDLC Status Receive HDLC Interrupt Status Receive HDLC Interrupt Enable Receive HDLC FIFO Data Read
Specifications
Registers
following table lists access codes used describe type register bits.
Table Register Description (Part
Code
RW1C RW0S RTCW RTSW RWTC RWTS Read/Write Read-Only Read/Write Clear Read/Write Read Clear Read Read Clear/Write Read Set/Write Read/Write value Clear Read/Write value
Description
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Specifications
Framer MegaCore Function (T3FRM) User Guide
Table Register Description (Part
RWSC RWSS Read/Write Self-Clearing Read/Write Self-Setting Unused bits/Read Unused bits/Read
Master Register Description
Table 7.MSTR_INT Master Interrupt Status
Field
PRBS RFEAC RHDLC THDLC RXFRMR
Bits
Access
Function
When PRBS block generated interrupt. When RFEAC generated interrupt. When RHDLC generated interrupt. When THDLC generated interrupt. When RXFRMR generated interrupt.
Default
Table 8.MSTR_INT_EN Master Interrupt Enable
Field
PRBS RFEAC RHDLC THDLC RXFRMR
Bits
Access
Function
This PRBS interrupt enable. This RFEAC interrupt enable. This RHDLC interrupt enable. This THDLC interrupt enable. This RXFRMR interrupt enable.
Default
Table 9.RESERVED Reserved
Field
RXFRMR
Bits
Access
Function
This field reserved future use.
Default
Table 10.PRBS_CTRL PRBS control
Field
RXPRBS TXPRBS
Bits
Access
Function
This PRBS detection enable. This PRBS generation enable.
Default
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Framer MegaCore Function (T3FRM) User Guide
Specifications
Table 11.PRBS_INT PRBS Interrupt Status
Field
SYNC
Bits
Access
RW1C
Function
When synchronization achieved. When synchronization lost.
Default
Table 12.PRBS_INT_EN PRBS Interrupt Enable
Field
SYNC
Bits
Access
Function
This synchronization interrupt enable.
Default
Specifications
Table 13.PRBS_THRES PRBS Threshold
Field
THRES
Bits
Access
Function
This upper threshold PRBS synchronization.
Default
8'h40
Table 14.PRBS_ERR PRBS Error Counter
Field
Bits
15:0
Access
Function
This PRBS error counter.
Default
TXFRMR Register Description
Table 15.TXFRMR_CTRL Transmit Framer control 'h10
Field
CINST SONET CBIT IDLE TOHDIS
Bits
Access
Function
When single rail enabled. When dual rail enabled. When C-bits inserted software. When C-bits generated internally.
Default
When data input from Mapper Interface. When data input from Midbus interface. When C-bit parity application enabled. When application enabled. When X1X2='b00. When X1X2-'b11. This indication enable. This idle signal enable.
When overhead insertion disabled. When overhead insertion enabled.
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Specifications
Framer MegaCore Function (T3FRM) User Guide
Table 16.TXFRMR_DIAG Transmit Framer Diagnostic 'h12
Field
DEXZ DFEBE DPARERR DCPARERR
Bits
Access
Function
When transition from insert forcing three consecutive zeros into data stream. When transition form insert FEBE setting three C-bits M-subframe zero.
Default
When transition from P-bits inverted before insertion into stream. When transition from three C-bits M-subframe inverted before insertion into stream.
DMBERR DFBERR DLCV DLOS
When transition from M-bits inverted before insertion into stream. When transition from MF-bits inverted before insertion into stream. When transition from line code violation inserted generating incorrect polarity violation.
When transition from data output forced continuous zero.
TFEAC Register Descriptions
Table 17.TFEAC_CTRL Transmit FEAC control 'h14
Field
Bits
Access
Function
Default
This TFEAC enable. When disabled, TFEAC sends FEAC channel.
Table 18.TFEAC_CODE Transmit FEAC Code 'h16
Field
TCODE
Bits
Access
Function
6-bit FEAC code transferred.
Default
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Framer MegaCore Function (T3FRM) User Guide
Specifications
Table 19.CINST1 C-Bit Insertion 'h18
Field
Bits
14:12 11:9
Access
Function
Default
These C1C2C3 bits M-subframe These C1C2C3 bits M-subframe These C1C2C3 bits M-subframe These C1C2C3 bits M-subframe
Table 20.CINST2 C-Bit Insertion 'h1A
Field
Specifications
Function Default
Bits
Access
These C1C2C3 bits M-subframe These C1C2C3 bits M-subframe
THDLC Register Descriptions
Table 21.THDLC_CTRL Transmit HDLC Control 'h20
Field
CRC_MODE FF_RST
Bits
Access
Function
When select CRC-CCITT. When select CRC-16. When there transition from FIFO buffer reset cleared.
Default
When last byte message been written message FIFO buffer. This automatically cleared next clock cycle. When this register: aborts current transmission, sends abort code with pattern until this reset resets FIFO buffer. This THDLC enable. When disabled, FIFO buffer reset.
ABORT
Table 22.THDLC_STAT Transmit HDLC Status 'h22
Field
UNDERFLOW FF_FULL FF_HFULL
Bits
Access
Function
When message FIFO buffer underflow condition. When message FIFO buffer full. When message FIFO buffer half full.
Default
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Specifications
Framer MegaCore Function (T3FRM) User Guide
Table 23.THDLC_INT Transmit HDLC Interrupt Status 'h24
Field
UNDER FF_FULL FF_HFULL
Bits
Access
RW1C RW1C RW1C
Function
message FIFO buffer underflow occurred. This change message (FIFO buffer full status interrupt). This change message (FIFO buffer half full status interrupt).
Default
Table 24.THDLC_INTR_EN Transmit HDLC Interrupt Enable 'h26
Field
UNDER FF_FULL FF_HFULL
Bits
Access
Function
This message FIFO buffer underflow interrupt enable. This message FIFO buffer full interrupt enable. This message FIFO buffer half full interrupt enable.
Default
Table 25.THDLC_FIFO_DATA Transmit HDLC FIFO Data Write 'h28
Field
TFDATA
Bits
Access
Function
Default
This transmit FIFO buffer data write. Data written into FIFO buffer this register.
RXFRMR Register Description
Table 26.RXFRMR_CTRL Receive Framer Control 'h30
Field
CBEN REFR
Bits
Access
Function
Default
When C-bit parity application enabled. When application enabled. Reframing triggered transition REFR bit. When single rail enabled. When dual rail enabled.
Altera Corporation
Framer MegaCore Function (T3FRM) User Guide
Specifications
Table 27.RXFRMR_STAT Receive Framer Status 'h32
Field
IDLE
Bits
Access
Function
When line code violation occurred. When excessive zeros have occurred. When loss signal occurred. When frame alignment lost. When frame alignment found. When pattern been received. When idle pattern been received.
Default
Specifications
When been detected, i.e. X1X2='b00. When been removed, i.e. X1X2='b11. differs from this remains unchanged. This current status signal, i.e. first C-bit M-subframe. When been logic consecutive occasions, thus indicating presence C-bit parity application. When signal been logic zero more times within consecutive occasions, thus indicating application.
Table 28.RXFRMR_INT Receive Framer Interrupt Status 'h34
Field
LCVI EXZI LOSI OOFI AISI IDLEI RDII CBITI
Bits
Access
RW1C RW1C RW1C RW1C RW1C RW1C RW1C RW1C
Function
This change state status interrupt. This change state status interrupt. This change state status interrupt. This change state status interrupt. This change state status interrupt. This change state IDLE status interrupt. This change state status interrupt. This change state CBIT status interrupt.
Default
Table 29.RXFRMR_INT_EN Receive Framer Interrupt Enable 'h36 (Part
Field
Bits
Access
Function
This change state status interrupt enable. This change state status interrupt enable.
Default
This change state status interrupt enable.
Altera Corporation
Specifications
Framer MegaCore Function (T3FRM) User Guide
Table 29.RXFRMR_INT_EN Receive Framer Interrupt Enable 'h36 (Part
IDLE CBIT This change state status interrupt enable. This change state status interrupt enable. This change state IDLE status interrupt enable.
This change state status interrupt enable. This change state CBIT status interrupt enable.
RFEAC Register Descriptions
Table 30.RFEAC_CTRL Receive FEAC control 'h38
Field
Bits
Access
Function
This RFEAC enable.
Default
Table 31.RFEAC_STAT Receive FEAC Status 'h3A
Field
IDLE
Bits
Access
FEAC idle.
Function
Default
Table 32.RFEAC_INT Receive FEAC Interrupt Status 'h3C
Field
VALID
Bits
Access
RW1C
Function
When valid FEAC code been received.
Default
Table 33.RFEAC_INT_EN Receive FEAC Interrupt Enable 'h3E
Field
VALID
Bits
Access
Function
This valid code interrupt enable.
Default
Table 34.RFEAC_CODE Receive FEAC Code 'h40
Field
RCODE
Bits
Access
Function
6-bit FEAC received.
Default
6'h3f
Counter Register Descriptions
Table 35.LCVCTR Counter 'h42
Field
LCVCNT
Bits
15:0
Access
Function
This line code violation counter.
Default
Altera Corporation
Framer MegaCore Function (T3FRM) User Guide
Specifications
Table 36.OOFCTR Counter 'h44
Field
OOFCNT
Bits
15:0
Access
Function
This frame counter.
Default
Table 37.LOSCTR Counter 'h46
Field
LOSCNT
Bits
15:0
Access
Function
This loss signal counter.
Default
Table 38.EXZCTR Counter 'h48
Field
EXZCNT
Specifications
Function
This excessive zeros counter.
Bits
15:0
Access
Default
Table 39.PERRCTR PERR Counter 'h4A
Field
PERRCNT
Bits
15:0
Access
Function
This P-bit error counter.
Default
Table 40.CPERRCTR CPERR Counter 'h4C
Field
CPERRCNT
Bits
15:0
Access
Function
This CP-bit error counter.
Default
Table 41.FEBECTR FEBE Counter 'h4E
Field
FEBECNT
Bits
15:0
Access
Function
This block error counter.
Default
Table 42.AISCTR Counter 'h50
Field
AISCNT
Bits
15:0
Access
Function
This alarm indication signal counter.
Default
Altera Corporation
Specifications
Framer MegaCore Function (T3FRM) User Guide
RHDLC Register Descriptions
Table 43.RHDLC_CTRL Receive HDLC control 'h60
Field
CRC_MODE ADDM
Bits
Access
Function
When select CRC-CCITT. When select CRC-16.
Default
When RHDLC detects address incoming packet, only stores data FIFO buffer address matches contents address register. When data stored FIFO buffer. When there transition from FIFO buffer reset cleared. When RHDLC enabled. When RHDLC disabled. When disabled, FIFO buffer related interrupts cleared.
FF_RST
Table 44.RHDLC_STAT Receive HDLC Status 'h62
Field
FF_EMTY FF_HEMTY RSVD IDLE
Bits
Access
Function
When message FIFO buffer empty. When message FIFO buffer half empty. This field reserved When RHDLC idle status.
Default
Table 45.RHDLC_INT Receive HDLC Interrupt Status 'h64
Field
FRM_ERR CRC_ERR FF_EMTY FF_HEMTY ABORT
Bits
Access
RW1C RW1C RW1C RW1C RW1C RW1C RW1C
Function
When frame error detected.
Default
When error detected last LAPD frame. When complete message been stored FIFO buffer. This change message (FIFO buffer empty status).
This change message (FIFO buffer half empty status). abort sequence detected this field. When data written over unread data FIFO buffer.
Altera Corporation
Framer MegaCore Function (T3FRM) User Guide
Specifications
Table 46.RHDLC_INT_EN Receive HDLC Interrupt Enable 'h66
Field
FRM_ERR CRC_ERR FF_EMTY FF_HEMTY ABORT
Bits
Access
Function
This frame error interrupt enable. This error interrupt enable. This message interrupt enable. This message FIFO buffer empty interrupt enable. This message FIFO buffer half empty interrupt enable. This abort sequence interrupt enable. This message FIFO buffer overrun enable.
Default
Specifications
Table 47.RHDLC_FIFO_DATA Receive HDLC FIFO Data Read 'h68
Field
PADDR
Bits
15:8
Access
Function
Default
address matching mode, first byte received after flag 8'h01 character compared against contents this register. match occurs, data, including matching first byte, written into FIFO buffer. Only most significant bits compared incoming address. address matching mode, second byte received after 8'h3c flag character compared against contents this register. match occurs, packet data, including matching second byte, written FIFO buffer. Only most significant seven bits compared incoming address.
RFDATA
Core Verification Summary
full-feature variant T3FRM object very thorough verification, thus should operate according industry standards. Testing done environments: simulation third-party compatibility. Both described briefly, including number test programs, their results.
Simulation Environment
T3FRM simulated using behavioral utilities with multiple simulators, including limited ModelSim behavioral utilities consist stream generators monitors, payload generators monitors, AIRbus master model, clock generators.
Altera Corporation
Specifications
Framer MegaCore Function (T3FRM) User Guide
test suite using utilities model T3FRM used verify proper operation features described RXFRMR TXFRMR sections. RXFRM TXFRM were tested full speed: 44.736 MHz. Table lists results simulation full-feature variant T3FRM
Table Results
Number test programs Number test programs passing Number test programs failing Number test cases Number test cases passing Number test cases failing Note:
Each test program contains least test case.
Compatibility Testing Environment
full-feature variant T3FRM evaluated-within APEX EP20K400EFC672 device-against commercial third-party framer with similar features, required industry standards. Altera MegaCore function used interface AIRbus, third-party framer. Figure shows test board used. Software from host used registers T3FRM, third-party framer. effects setting these registers, corresponding registers, were observed determine functionality.
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Framer MegaCore Function (T3FRM) User Guide
Specifications
Figure Test Board
Third-Party ASSP
Specifications
APEX EP20K400EFC672
Tests were extended periods time, thereby testing millions frames. Table lists results hardware verification full-feature variant T3FRM.
Table Results
Number test programs Number test programs passing Number test programs failing Number test cases Number test cases passing Number test cases failing Note:
Each test program contains least test case.
Altera Corporation
Notes:
Getting Started
User Guide
Test-Drive T3FRM with OpenCore
This section describes obtain variant from Altera® Framer MegaCore® Function (T3FRM). explains install T3FRM your walks through process implementing variant design. test-drive T3FRM using Altera OpenCore® feature-within Quartus® software-to instantiate perform place-and-route, perform static timing analysis, simulate using third-party simulator, using your custom logic. Only when ready generate programming files, need obtain licenses through your local Altera sales representative.
Design Walkthrough
This design walkthrough involves following steps: Obtaining installing T3FRM; Generating custom T3FRM your system using MegaWizard® Plug-In; Implementing rest your system using AHDL, VHDL, Verilog HDL; Compiling your design performing place-and-route; Licensing T3FRM configure device.
Getting Started
instructions assume that:
using familiar with Quartus software; Quartus software version higher) installed default location; using OpenCore feature test-drive T3FRM, have licensed
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Getting Started
Framer MegaCore Function (T3FRM) User Guide
Obtaining Installing T3FRM
order start using T3FRM, need obtain MegaCore package from your local Altera representative. package includes:
MegaWizard Plug-In Encrypted gate level netlist Place-and-route constraints (where necessary) Secure simulation model Sanity testbench Midbus AIRbus interface functional specifications Data sheet User guide
T3FRM uses MegaWizard Plug-In-within Quartus software-to generate variants VHDL, AHDL, Verilog HDL, which instantiate into your design.
MegaWizard Generated Files
When finish going through wizard, generates following files:
following files-depending your tool selection- used instantiate T3FRM your design: ADHL text design file (.tdf) VHDL design file (.vhd) Verilog design file (.v) Sample Verilog instantiation Black (_inst.v) Black module (_bb.v) Symbol files (.bsf) Quartus software used instantiate T3FRM into schematic design. encrypted netlist file (.e.vqm.v)
Installing MegaCore Files
MegaWizard Plug-In generate files install them your following instructions describe this process. Before MegaWizard Plug-In, your must have Java runtime environment version installed. This file downloaded from Java site http://www. java.sun.com.
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Framer MegaCore Function (T3FRM) User Guide
Getting Getting Started
Windows, follow instructions below: Click (Start menu). Type <path name>\<filename>.exe, where <path name> location downloaded T3FRM, <filename> filename T3FRM. Click MegaCore Installer dialog appears. Follow wizard instructions finish installation. After have finished installing files, must specify directory which installed them user library Quartus software. Search "User Libraries" Quartus Help instructions these libraries.
Getting Started
Generating Custom T3FRM
This section describes design flow using Altera T3FRM Quartus development system. MegaWizard Plug-In Manager provided with T3FRM. MegaWizard Plug-In Manager-used within Quartus software-allows create, modify design files meet needs your application. then them instantiate T3FRM your design file. create custom T3FRM using wizard, follow these steps: Start MegaWizard Plug-In choosing MegaWizard Plug-In Manager command (File menu) Quartus software. MegaWizard Plug-In Manager dialog displayed. Refer Quartus Help detailed instructions MegaWizard Plug-In Manager.
Specify that want create custom variant click Next. second page wizard, select T3FRM from folder. Choose type output files, specify folder name files wizard creates, click Next. Select optional parameters choices that require. final screen lists design files that wizard creates. Click Finish.
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Getting Started
Framer MegaCore Function (T3FRM) User Guide
Implementing System Compiling Performing Place Route
Once have created your custom T3FRM, ready implement files generated MegaWizard your design. Quartus software, other tools create your design. Quartus software compile place-and-route your design. Refer Quartus Help instructions performing compilation. After have verified that your design functionally correct, ready perform system verification.
Performing Synthesis Compilation Post-Routing Simulation
Quartus software works seamlessly with tools from vendors, including: Cadence, Exemplar Logic, Mentor Graphics, Synopsys, Synplicity, Viewlogic. After have licensed T3FRM, generate EDIF, VHDL, Verilog HDL, Standard Delay Output Files from Quartus software. Then, these files with your existing tools perform functional modeling, post-route simulation your design.
Using Third-Party Tools
synthesize your design third-party tool perform postroute simulation, follow these steps: Create your custom design instantiating T3FRM. Synthesize design using your third-party tool. Your tool should treat T3FRM instantiation black either setting attributes ignoring instantiation. After compilation, generate hierarchical netlist file your thirdparty tool. Open your netlist file Quartus software. pre-synthesized encrypted .e.vqm.v file from your working directory.
Using Quartus Software
Select Compile mode (Processing menu). Specify Compiler settings Compiler Settings dialog (Processing menu), Compiler Settings wizard. Specify user libraries project order which Compiler searches libraries.
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Framer MegaCore Function (T3FRM) User Guide
Getting Getting Started
Specify input settings project. Choose Tool Settings (Project menu). Select Custom EDIF Design Entry/Synthesis Tool list. Click Settings. Tool Input Settings dialog box, make sure that relevant tool name option selected Design Entry/Synthesis Tool list. Depending type output file want, specify Verilog output settings VHDL output settings General Settings dialog (Project menu). 1993 VHDL Language option. pre-synthesized encrypted .e.vqm.v file from your working directory. Compile your design. Quartus Compiler synthesizes performs place-and-route your design, generates output programing files.
Getting Started
Import your Quartus II-generated output files (.edo, .vho, .vo, .sdo) into your third-party tool post-route, device-level, system-level simulation.
Functional Simulations Using Visual Models
This section describes Visual Model verification provides instructions using Visual Models. Figure shows example Visual Model arrangement.
Figure General Arrangement
Testbench Hook-Up Visual Model Black Verilog VHDL Wrapper Empty Declaration User Design
Utility
Utility
Utility
level Visual Model treated sub-block design main design unit.
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Getting Started
Framer MegaCore Function (T3FRM) User Guide
Downloading Installing Visual Software
Visual software facilitates Visual simulation models allowing waveforms viewed using third party simulation tools. view simulation model, must have Visual software installed your system. download software, instructions refer Altera site,
Licensing Configuring Device
After have compiled analyzed your design, ready configure your targeted Altera semiconductor device. evaluating T3FRM with OpenCore feature, must license function before generate programming files. obtain license contact your local Altera sales representative. current T3FRM variants single license with ordering code: PLSM:T3FRM.
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2001 User Guide Version 1.01 Innovation Drive Jose, 95134 (408) 5

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