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STS3CFRM June 2001 User Guide Version 1.01 Innovation Drive


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SONET/SDH STS-3c/STM-1 Framer MegaCore Function
STS3CFRM
June 2001 User Guide Version 1.01
Innovation Drive Jose, 95134 (408) 544-7000 http://www.altera.com
A-UG-IPSTS3CFRM-1.01
SONET/SDH STS-3c/STM-1 Framer MegaCore Function (STS3CFRM) User Guide
Altera, APEX, APEX 20K, MegaCore, MegaWizard, OpenCore, Quartus, Quartus trademarks and/or service marks Altera Corporation United States other countries. Altera Corporation acknowledges trademarks other organizations their respective products services mentioned this document, including following: Verilog registered trademark Cadence Design Systems, Incorporated. Java trademark Microsystems Inc. Microsoft registered trademark Windows trademark Microsoft Corporation. ModelSim registered trademark Model Technology Inc. Altera products protected under numerous U.S. foreign patents pending applications, maskwork rights, copyrights. Altera warrants performance semiconductor products current specifications accordance with Altera's standard warranty, reserves right make changes products services time without notice. Altera assumes responsibility liability arising application information, product, service described herein except expressly agreed writing Altera Corporation. Altera customers advised obtain latest version device specifications before relying published information before placing orders products services. Copyright 2001 Altera Corporation. rights reserved.
Altera Corporation
About this User Guide
User Guide
This user guide provides comprehensive information about Altera® SONET/SDH STS-3c/STM-1 Framer MegaCore® Function (STS3CFRM). Table shows user guide revision history.
Table Revision History
Revision
1.00 1.01
Date
Dec. 2000 June 2001 First release
Description
First revision. Changed rxpause txpause rxclk_en txclk_en. Added "Core Verification Summary" section. Revised "Getting Started" chapter.
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Adobe Acrobat Find feature allows search contents file. Click binoculars icon toolbar open Find dialog box, click right mouse button pull-down menu. Bookmarks serve additional table contents. Thumbnail icons, which provide miniature previews each page, provide link pages. Numerous links, shown green text, allow jump related information.
Altera Corporation
About this User Guide SONET/SDH STS-3c/STM-1 Framer MegaCore Function (STS3CFRM) User Guide
Contact Altera
most up-to-date information about Altera products, Altera world-wide site http://www.altera.com. additional information about Altera products, consult sources shown Table
Table Contact Altera
Information Type
Altera Literature Services Non-technical customer service
Access
Electronic mail Telephone hotline
Canada
lit_req@altera.com (800) SOS-EPLD
Other Locations
lit_req@altera.com (408) 544-7000 (7:30 a.m. 5:30 p.m. Pacific Time) (408) 544-7606 (408) 544-7000 (7:30 a.m. 5:30 p.m. Pacific Time) (408) 544-6401 telecom@altera.com ftp.altera.com (408) 544-7104 http://www.altera.com
Technical support Telephone hotline
(408) 544-7606 (800) 800-EPLD (6:00 a.m. 6:00 p.m. Pacific Time) (408) 544-6401 telecom@altera.com ftp.altera.com (408) 544-7104 http://www.altera.com
Electronic mail site General product information Note:
Telephone World-wide site
also contact your local Altera sales office sales representative.
Altera Corporation
SONET/SDH STS-3c/STM-1 Framer MegaCore Function (STS3CFRM) User Guide About this User Guide
Typographic Conventions
Table Conventions
Visual
Bold Type with Initial Capital Letters bold type
SONET/SDH STS-3c/STM-1 Framer MegaCore Function (STS3CFRM) User Guide uses typographic conventions shown Table
Meaning
Command names, dialog titles, checkbox options, dialog options shown bold, initial capital letters. Example: Save dialog box. External timing parameters, directory names, project names, disk drive names, filenames, filename extensions, software utility names shown bold type. Examples: fMAX, \maxplus2 directory, drive, chiptrip.gdf file. Book titles shown bold italic type with initial capital letters. Example: 1999 Device Data Book. Document titles shown italic type with initial capital letters. Example: (High-Speed Board Design). Internal timing parameters variables shown italic type. Examples: tPIA, Variable names enclosed angle brackets shown italic type. Example: <file name>, <project name>.pof file. Keyboard keys menu names shown with initial capital letters. Examples: Delete key, Options menu. References sections within document titles Quartus MAX+PLUS Help topics shown quotation marks. Example: "Configuring FLEX FLEX 8000 Device with BitBlasterDownload Cable." Signal port names shown lowercase Courier type. Examples: data1, tdi, input. Active-low signals denoted suffix e.g., reset_n. Anything that must typed exactly appears shown Courier type. example: Also, sections actual file, such Report File, references parts files (e.g., AHDL keyword SUBDESIGN), well logic function names (e.g., TRI) shown Courier.
Bold italic type Italic Type with Initial Capital Letters Italic type
Initial Capital Letters "Subheading Title"
Courier type
c.,. Numbered steps used list items when sequence items important, such steps listed procedure.
Bullets used list items when sequence items important. checkmark indicates procedure that consists step only. hand points information that requires special attention. angled arrow indicates should press Enter key. feet direct more information particular topic.
Altera Corporation
About this User Guide SONET/SDH STS-3c/STM-1 Framer MegaCore Function (STS3CFRM) User Guide
Abbreviations Acronyms
AHDL AIS-L AIS-P ABIP-8 ERDI-P FIFO LCD-P LOPC LOPC LSByte Mbps MSByte PLM-P RDI-L RDI-P REI_L REI_P RXPOH RXTOH SONET SRDI-P
Altera Hardware Description Language Alarm Indication Signal-Line Alarm Indication Signal-Path Automatic Protection Switching Asynchronous Transfer Mode Interleaved Parity Cell Loss Priority Central processing unit Electronic Design Automation Enhanced Remote Defect Indicator-Path Embedded System Block First First Intellectual Property Loss Cell Delineation-Path Logic Element Loss Frame Loss Pointer Loss Optical Carrier Loss Pointer Concatenate Loss Signal Least Significant Least Significant Byte Megabits second Most Significant Most Significant Byte Data Flag Frame Personal computer Physical Layer Payload Label Mismatch-Path Path Overhead Path Terminating Equipment Remote Defect Identification-Line Path Remote Defect Indication-Path Remote Error Identification-Line Path Remote Error Indication-Path Receive Path Overhead Receiver Transport Overhead Receiver Signal Degrade Synchronous Digital Hierarchy Severely Errored Frame Signal Fail Synchronous Optical Network Synchronous Payload Envelope Single-bit RDI-P
Altera Corporation
SONET/SDH STS-3c/STM-1 Framer MegaCore Function (STS3CFRM) User Guide About this User Guide
STM-1 STS-1 STS-3c TIM-P TXPOH TXTOH UNEQ-P UTOPIA VHDL VHSIC
Synchronous Transfer Module level Synchronous Transport Signal level Synchronous Transport Signal level concatenated Transmission Convergence Trace Identifier Mismatch-Path Transport Overhead Transmit Path Overhead Transmitter Transport Overhead Transmitter Unequipped-Path Universal Test Operations Physical Interface AVHSIC Hardware Description Language Very High Speed Integrated Circuit
Altera Corporation
Notes:
Contents
User Guide
About this User Guide
Find Information Contact Altera Typographic Conventions Abbreviations Acronyms
Specifications
General Description Features Receiver Features Transmitter Features Functional Description Receiver Description RXTOH LOPC Monitoring Descrambling Frame Synchronization Section Trace B1/B2 Monitoring Error Rate Monitoring with Second window (BM1S) RDI-L AIS-L (K2) Monitoring K1/K2 Monitoring Synchronization Monitoring REI-L Monitoring Automatic AIS-P Insertion Control Capture Serial Hardware extraction (SOH) RXPOH H1/H2 Pointer Processing Automatic Downstream Insertion Control Capture Path Trace Monitoring Signal Label (C2) Monitor RDI-P Monitoring REI-P Monitor Serial Hardware extraction (SOH) Transmitter Description TXTOH
Altera Corporation
Contents
Insertion Scrambling A1/A2 Generation Section Trace (J0) Generation Generation Error Mask Generation RDI-L Control (three least significant bits K1/K2 Generation REI-L Generation (M1) AIS-L Control Data Communications (D1-D12) Selection TXPOH Pointer Adjustments AIS-P Generation Path Trace Generation Generation RDI-P (G1) Generation REI-P (G1) Generation Interfaces Protocols AIRbus Midbus Receive Direction Transmit Direction Hardware Overhead Insertion Extraction SONET Receive Serial Data Outputs Transport Overhead Bytes Data Communications Bytes E1/F1/E2 Bytes Path Overhead Bytes SONET Transmit Serial Data Input Transport Overhead Bytes Data Communications Bytes E1/F1/E2 Bytes Path Overhead Bytes Signals Performance Software Interface Offsets Offsets Memory Maps RXTOH_CTRL Memory RXPOH_CRTL Memory RXPOH_CAP Memory TXTOH_CRTL Memory Map. TXPOH_CTRL Memory Map. Registers
Altera Corporation
Contents
Registers RXTOH Register Description RXTOH_CTRL Receiver Transport Control 'h0. RXTOH_STAT Receiver Transport Status 'h4. RXTOH_IS Receiver Transport Interrupt Status RXTOH_IE Receiver Transport Interrupt Enable 'hC. RXTOH_B1_ERR_CNT Receiver Error Count 'h10 RXTOH_B2_ERR_CNT Receiver Error Count 'h14 RXTOH_REIL_ERR_CNT Receiver REI-L Count 'h18 RXTOH_K1_ACCPT Receiver Value 'h1C RXTOH_K2_ACCPT Receiver Value 'h20 RXTOH_S1_ACCPT Receiver Value 'h24. RXTOH_SEF_FORCE Receiver Force 'h28. RXTOH_LOS_THRSHD Receiver Threshold 'h2C. RXTOH_AUTO_AIS Receiver Transport Auto-AIS Control 'h30. RXTOH_FRAMER_CTRL Receiver Framer Control 'h34 RXTOH_SER_CTRL Receiver Transport Serial Port Control 'h38 RXTOH_J0_CTRL Receiver Control 'h3C. RXTOH_SD_SET_TIME Receiver Monitor Interval 'h40. RXTOH_SF_SET_TIME Receiver Monitor Interval 'h44. RXTOH_SD_SET_TH Receiver Threshold 'h48 RXTOH_SF_SET_TH Receiver Threshold 'h4C RXTOH_SD_BURST_TOL Receiver Burst Tolerance 'h50 RXTOH_SF_BURST_TOL Receiver Burst Tolerance 'h54. RXTOH_SD_CLEAR_TIME Receiver Clear Monitor Interval 'h58 RXTOH_SF_CLEAR_TIME Receiver Clear Monitor Interval 'h5C RXTOH_SD_CLEAR_TH Receiver Clear Threshold 'h60. RXTOH_SF_CLEAR_TH Receiver Clear Threshold 'h64. RXPOH Register Description RXPOH_CTRL Receiver Path Control RXPOH_STAT Receiver Path Status RXPOH_IS Receiver Path Interrupt Status 'h8. RXPOH_IE Receiver Path Interrupt Enable RXPOH_RDIP Receiver RDI-P 'h10. RXPOH_C2 Receiver Path Label (C2) 'h14 RXPOH_B3_ERR_CNT Receiver Error Count 'h18 RXPOH_REIP_ERR_CNT Receiver REI-P Count 'h1C. RXPOH_CUR_PTR Receiver Pointer Value 'h20. RXPOH_LOPC_STAT Receiver LOPC Status 'h24 RXPOH_RESERVED Reserved 'h28 RXPOH_AISC_STAT Receiver AISC Status 'h2C. RXPOH_RESERVED Reserved 'h30 RXPOH_AUTO_AIS Receiver auto 'h34 RXPOH_SER_CTRL Receiver Path Serial Port Control 'h38 RXPOH_J1_CTRL Receiver Control 'h3C. RXPOH_CAP Register Description
Altera Corporation
Contents
RXPOH_CAP_J1 Receiver Capture 'h0. RXPOH_CAP_B3 Receiver Capture RXPOH_CAP_C2 Receiver Capture 'h8. RXPOH_CAP_G1 Receiver Capture RXPOH_CAP_F2 Receiver Capture 'h10 RXPOH_CAP_H4 Receiver Capture 'h14. RXPOH_CAP_Z3 Receiver Capture 'h18 RXPOH_CAP_Z4 Receiver Capture 'h1C RXPOH_CAP_Z5 Receiver Capture 'h20 TXTOH Register Description TXTOH_CTRL Transmitter Transport Control TXTOH_STAT Transmitter Transport Status TXTOH_IS Transmitter Transport Interrupt Status 'h8. TXTOH_IE Transmitter Transport Interrupt Enable TXTOH_A1_ERR_BYTES Transmitter Error Mask 'h10. TXTOH_RESERVED Reserved 'h14 TXTOH_A2_ERR_BYTES Transmitter Error Mask 'h18. TXTOH_RESERVED Reserved 'h1C. TXTOH_B1_ERR_MASK Transmitter Error Mask 'h20 TXTOH_B2_ERR_BYTES Transmitter Byte Error Mask 'h24 TXTOH_B2_ERR_MASK Transmitter Error Mask 'h28 TXTOH_J0 Transmitter Value 'h2C TXTOH_E1 Transmitter Value 'h30 TXTOH_F1 Transmitter Value 'h34 TXTOH_K1K2 Transmitter K1K2 Value 'h38. TXTOH_RDIL_CTRL Transmitter RDI-L Control 'h3C TXTOH_S1 Transmitter Value 'h40 TXTOH_MOM1 Transmitter M0/M1 value 'h44 TXTOH_E2 Transmitter Value 'h48 TXTOH_SER_CTRL Transmitter Serial Port Control 'h4C TXTOH_J0_CTRL Transmitter Control 'h50 TXPOH Register Description TXPOH_CTRL Transmitter Path Control 'h0. TXPOH_STAT Transmitter Path Status 'h4. TXPOH_IS Transmitter Path Interrupt Status TXPOH_IE Transmitter Path Interrupt Enable TXPOH_J1 Transmitter Value 'h10. TXPOH_B3_ERR_MASK Transmitter Error Mask 'h14 TXPOH_C2 Transmitter Value 'h18. TXPOH_G1 Transmitter Value 'h1C TXPOH_F2 Transmitter Value 'h20 TXPOH_H4 Transmitter Value 'h24. TXPOH_Z3 Transmitter Value 'h28 TXPOH_Z4 Transmitter Value 'h2C TXPOH_Z5 Transmitter Value 'h30 TXPOH_PTR_ACT Transmitter Pointer Action 'h34
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Contents
TXPOH_ARB_H1 Transmitter Arbitrary Pointer 'h38 TXPOH_ARB_H2 Transmitter Arbitrary Pointer 'h3C TXPOH_CUR_PTR Transmitter Current Offset 'h40 TXPOH_RDIP_CTRL Transmitter RDI-P Control 'h44 TXPOH_SER_CTRL Transmitter Path Serial Port Control 'h48 TXPOH_J1_CTRL Transmitter Control 'h4C Memories RXTOH_J0_MEM Memory Description SONET Receive Transport Section -`h100. RXTOH_CAP Memory Description SONET Receive Transport Section `h200 TXTOH_J0_MEM Memory Description SONET Transmit Transport Section -`h500. RXPOH_J1_MEM Memory Description SONET Receive Path Section `h700 TXPOH_J1_MEM Memory Description SONET Transmit Path Section `hB00. Core Verification Summary Simulation Environment Compatibility Testing Environment
Getting Started
Design Walkthrough Obtaining Installing STS3CFRM Downloading MegaCore Function Installing MegaCore Files Generating Custom STS3CFRM Implementing System .100 Simulating Your Design .100 Using Verilog Demo Testbench .100 Using Visual Software .101 Synthesis, Compilation Place Route .101 Using Third-Party Tools Synthesis .101 Using Quartus development tool compilation place-and-route .101 Licensing Configuration .102 Performing Post-Routing Simulation .102
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xiii
Notes:
Specifications
User Guide
General Description
SONET/SDH STS-3c/STM-1 Framer MegaCore® Function uses MegaWizard® Plug-In-within Quartus® software-to generate variants AHDL, VHDL, Verilog HDL, which instantiate into your design. Table shows optional features available generate variants STS3CFRM.
Specifications
Table Optional Features
Note
Options Parameters Choices
4,539
ESBs
Basic Configuration
Serial insertion/extraction bytes 64-byte insert, extract, expect buffers Automatic monitoring extracted section trace (transport overhead) 64-byte insert, extract, expect buffers Automatic monitoring extracted path trace (path overhead) error rate monitoring with second window Note:
BM1S
1,578
numbers ESBs approximate 2001. Users strongly advised MegaWizard Plug-in Quartus software exact numbers each STS3CFRM variant.
When finish going through wizard, generates following files:
following depending your tool selection: AHDL text design file (.tdf) VHDL design file (.vhd) Verilog design file (.v) Sample Verilog instantiation Black (_inst.v) Black module (_bb.v) Symbol files (.bsf) Quartus software used instantiate STS3CFRM into schematic design encrypted netlist file (.e.vqm.v)
Altera Corporation
Specifications
SONET/SDH STS-3c/STM-1 Framer MegaCore Function (STS3CFRM) User Guide
STS3CFRM complies with applicable SONET standards, including:
American National Standards Institute (ANSI), Synchronous Optical Network (SONET) -Basic Description including Multiplex Structure, Rates, Formats, ANSI T1-105-1995. American National Standards Institute (ANSI), Synchronous Optical Network (SONET) -Payload Mappings, ANSI T1-105.02-1995. Telcordia, Synchronous Optical Network (SONET) Transport Systems: Common Generic Criteria, GR-253-CORE, Issue September 2000. Telcordia, Synchronous Optical Network (SONET) Transport Systems: Common Generic Criteria Issue List Report, GR-253-ILR, Issue October 2000. International Telecommunication Union, Network node interface synchronous digital hierarchy (SDH), ITU-T Recommendation 707, March 1996 International Telecommunication Union, Characteristics synchronous digital hierarchy (SDH) equipment functional blocks, ITU-T Recommendation 783, January 1994
These SONET/SDH standards naming convention, where byte. This STS3CFRM user guide uses naming convention where byte, Figure
Figure Naming Conventions
SONET Naming Convention
Naming Convention STS3CFRM User Guide
Altera Corporation
SONET/SDH STS-3c/STM-1 Framer MegaCore Function (STS3CFRM) User Guide
GettiSpecifications
Table shows bytes standard names functions.
Specifications
Table Transport Path Overhead Byte Designations
Transport Overhead
Framing Section Overhead Framing Trace/ Growth (STS-ID) J0/Z0 User Undefined Data Undefined Pointer Action Undefined Data Undefined Data Undefined Data D12/ Undefined Orderwire Undefined
Note
Path Overhead
Trace
BIP-8 Undefined Data Undefined Pointer BIP-8 Data Undefined Data Undefined Data D10/ Undefined
Orderwire Undefined Data Undefined Pointer Undefined Data Undefined Data Undefined Data D11/ Undefined
BIP-8 Signal Label Path Status User Channel Indicator Growth Growth Tandem Connection
Line Overhead
Sync Status/ REI-L/ Growth Growth S1/Z1 M1/Z2
Notes:
information this table taken from Telcordia GR-253_CORE standard, Issue Revision January 1999.
BIP-8 always calculated using even parity.
Altera Corporation
Specifications
SONET/SDH STS-3c/STM-1 Framer MegaCore Function (STS3CFRM) User Guide
Features
This user guide aims describe full feature STS3CFRM, options- SOH, J0B, J1B, BM1S-are selected, Table
Receiver Features
Frame byte alignment with SEF, LOS, detection RDI-L AIS-L detection Descrambling BIP-8 (B1, error checking Accumulation counters REI-L, REI-P errors Fully programmable threshold detection condition Section trace buffer (64-byte message) with mismatch detection invalid message detection Pointer processor that supports NDF, positive stuff, negative stuff AIS-P detection Full transport path overhead capture capabilities Signal label monitor with detection Path trace buffer (64-byte message) with TIM-P invalid message detection. RDI-P REI-P detection Loss Pointer Concatenate
Transmitter Features
A1/A2 with optional error insertion generation insertion with optional error mask Scrambling Automatic generation AIS-L, REI-L RDI-L according receiver state with optional software hardware insertion insertion capabilities force software Zero insertions undefined and/or growth bytes Software hardware insertion transport path overhead bytes. Data Communications bytes and/or growth bytes only inserted software. possible write undefined bytes. Section path trace generation from either software hardware buffer Automatic generation RDI-P REI-P signals with optional software/hardware override Pointer generation: software insertion NDF, positive stuff, negative stuff, arbitrary pointer Software insertion AIS-P signal
Altera Corporation
SONET/SDH STS-3c/STM-1 Framer MegaCore Function (STS3CFRM) User Guide
GettiSpecifications
Functional Description
Figure Block Diagram
STS3CFRM operates full-duplex mode, comprises four blocks: RXTOH, RXPOH_0, TXTOH, TXPOH_0. Figure shows block diagram STS3CFRM, including interfaces that support "Interfaces Protocols" page more information.
Specifications
Extract
Extract rxpohval_0 rxpohclk_0 rxpohfp_0
rxtohclk rxtoh rxtohval rxtohfp rxsdcc rxsdccval rxldcc rxldccval rxe1f1e2 rxe1f1e2val rxe1f1e2fp
rxclk rxclk_en rxreset_n
srxdat[7:0] srxval srxfr align_data[7:0] lopc
SONET
RXTOH RXPOH_0 mrxdat_0[7:0] mrxena_0 mrxval_0 mrxffp_0 mrxefp_0 mrxfoh_0 mrxeoh_0 mtxdat_0[7:0] mtxena_0 mtxval_0 mtxffp_0 mtxefp_0 mtxfoh_0 mtxeoh_0
txclk domain TXPOH_0
stxdat[7:0] stxval stxfr stxfp
SONET
TXTOH
txtohclk txtoh txtohen txtohfp txtohrdy txsdcc txsdccrdy txldcc txldccrdy txe1f1e2 txe1f1e2fp txe1f1e2rdy
txpohclk_0
txpoh_0
txpohen_0
txpohfp_0
Insert
read addr[11:2] rdata[31:0] wdata[31:0] dtack
AIRbus
Insert
Receiver Description
STS3CFRM receives SONET data. incoming bytes aligned locking framing bytes. aligned stream then forwarded RXTOH RXPOH_0 blocks where necessary transport path overhead processing performed.
Altera Corporation
txpohrdy_0
txclk txclk_en txreset_n
Midbus
rxclk domain
rxpoh_0
Specifications
SONET/SDH STS-3c/STM-1 Framer MegaCore Function (STS3CFRM) User Guide
RXTOH
RXTOH block processes incoming SONET data stream. following descriptions explain principle functions RXTOH block. more detailed descriptions, "Software Interface" page
LOPC Monitoring
incoming scrambled data monitored absence Continuous incoming data stream used trigger condition. Software used specify number zero bytes needed declare condition. separate input monitored LOPC.
Descrambling
bytes incoming stream descrambled except J0/Z0 bytes. Descrambling disabled software.
Frame Synchronization
framing bytes used determine frame alignment. conditions declared when framing bytes incoming frames contain errored framing patterns. number invalid framing bits needed declare errored frame controlled software. Software force condition reframing. alternative monitoring framing bits, STS3CFRM also monitor frame reset (srxfr). When receive frame reset input asserted, framer automatically assumes current byte input data either byte J0/Z0 byte determined software, resets internal counters accordingly.
Section Trace
byte used section trace. Software specify length section trace message. adds 64-byte buffer expected message, 128-byte buffer received message. contents preserved message access software. interrupt generated when section trace message accepted valid. mismatch flag raised messages identical. RXTOH block also implements unstable counter. unstable counter incremented each byte that differs from previously received byte. invalid condition declared when unstable counter reaches unstable counter cleared when valid accepted.
Altera Corporation
SONET/SDH STS-3c/STM-1 Framer MegaCore Function (STS3CFRM) User Guide
GettiSpecifications
B1/B2 Monitoring
interleaved parity (BIP-8) calculated over line overhead payload envelope, compared with fields transport overhead. errors accumulated 32-bit software accessible saturation counter. Software used specify error event. saturation counter incremented each BIP-8 error, each BIP-8 byte error. number events count selectable software.
Specifications
Error Rate Monitoring with Second window (BM1S)
error rate monitoring optional (BM1S). error rate monitoring performed using BIP-8 byte. conditions dependent error counts. Both used control APS. thresholds timing intervals controlled software.
RDI-L AIS-L (K2) Monitoring
byte consecutive frames monitored RDI_L AIS_L conditions. RDI_L declared after receiving byte consecutive frames. AIS_L declared after five frames.
K1/K2 Monitoring
used monitor APS. Three identical bytes consecutive frames replace current code. Flags notify software when valid code inconsistent byte been received.
Synchronization Monitoring
synchronization status network element monitored byte. timer used determine stability network element detecting changes byte over period time. timer software controlled.
REI-L Monitoring
byte contains REI_L count. byte relays many interleaved parity errors (B2) were received.
Automatic AIS-P Insertion Control
event AIS-L, LOS, LOF, LOPC, mismatch, unstable condition detected, software controlled option automatically relays into path section.
Altera Corporation
Specifications
SONET/SDH STS-3c/STM-1 Framer MegaCore Function (STS3CFRM) User Guide
Capture
contents overhead captured stored access external processor. contents transport overhead memory preserved frame access software.
Serial Hardware extraction (SOH)
available serially through optional hardware serial extraction (SOH). There separate dedicated ports bytes, just line DCC, just section DCC, combined E1/F1/E2.
RXPOH
RXPOH block locates within using pointer bytes.
H1/H2 Pointer Processing
pointer bytes indicate type pointer: normal pointer, pointer, AIS, NDF, increment pointer, decrement pointer, invalid pointer. This monitored software.
Automatic Downstream Insertion Control
event AIS-P, LOP-P, TIM-P, unstable, PLM-P, UNEQ-P, unstable condition detected, software controlled option automatically causes inserted downstream.
Capture
contents path overhead block captured stored access external processor. interrupt occurs when path overhead bytes current frame have been captured. contents path overhead memory preserved frame access software.
Altera Corporation
SONET/SDH STS-3c/STM-1 Framer MegaCore Function (STS3CFRM) User Guide
GettiSpecifications
Path Trace
byte used path trace. Software specify length section trace message. adds 64-byte buffer expected message, 128-byte buffer received message. contents preserved message access software. interrupt generated when section trace message accepted valid. mismatch flag raised messages identical. RXPOH block also implements unstable counter. unstable counter incremented each byte that differs from previously received byte. invalid condition declared when unstable counter reaches unstable counter cleared when valid accepted.
Specifications
Monitoring
BIP-8 calculated over incoming stream compared with field path overhead. byte calculated using even parity before scrambling. Errors accumulated 32-bit software accessible saturation counter. Software used specify error event. saturation counter incremented each BIP-8 error, each BIP-8 byte error.
Signal Label (C2) Monitor
byte allocated indicate contents treated signal label. Table shows signal label mismatch defect conditions.
Table Signal Label Mismatch Defect Conditions
Provisioned Functionality
equipped functionality anything except H00) equipped functionality Equipped-non specific H01) payload specific functionality anything except H01) payload specific functionality
Note
Defect
UNEQ-P none (Matched) none (Matched) none (Matched)
Received Payload Label Byte, hexadecimal)
Unequipped (00) Equipped-non specific (01) value corresponding payload specific functionality value corresponding same payload specific functionality provisioned functionality value corresponding different payload specific functionality provisioned functionality
Note:
information this table taken from Telcordia GR-253_CORE standard, Issue Revision January 1999.
Altera Corporation
Specifications
SONET/SDH STS-3c/STM-1 Framer MegaCore Function (STS3CFRM) User Guide
RXPOH block allows software specify expected signal label compares with observed value. values don't match, error declared. observed value `h00, UNEQ error declared, cleared. observed value matches expected value, cleared. observed value changes, flag software. label considered valid, must received consecutive frames. RXPOH block also implements unstable counter. unstable counter incremented each byte that differs from previously received byte. invalid condition declared when unstable counter reaches unstable counter cleared when consecutive identical bytes received.
RDI-P Monitoring
Telcordia SONET standards have definitions path defect. older version SRDI-P, which uses only (fourth LSB) byte. current version ERDI-P, which uses bits byte. ERDI-P declared when bits byte contains 010, 110.
Table RDI-P Settings Interpretation
Bits
Priority ERDI-P codes
applicable (for SRDI-P only, bits should `00') applicable (for SRDI-P only, bits should `00')
Trigger
defects
Interpretation
RDI-P defect
AIS-P, LOP-P
one-bit RDI-P defect
defects PLM-P, LCD-P AIS-P, LOP-P
RDI-P defect ERDI-P Payload Defect ERDI-P Server Defect
UNEQ-P, TIM-P ERDI-P Connectivity defect
Altera Corporation
SONET/SDH STS-3c/STM-1 Framer MegaCore Function (STS3CFRM) User Guide
GettiSpecifications
RXPOH block allows software specify type RDI-P error monitor. Software also specifies number consecutive consistent RDI-P codes that must observed before accepted valid. When valid RDI-P detected, flag software, RDI-P code that caused condition captured register. RXPOH block also implements RDI-P unstable counter. RDI-P unstable counter incremented each byte that differs from previously received byte. invalid RDI-P condition declared when RDI-P unstable counter reaches software specified threshold. RDI-P unstable counter cleared when valid RDI-P code accepted.
Specifications
REI-P Monitor
four most significant bits byte allocated convey REI-P function. byte relays many interleaved parity errors (B3) were received. RXPOH accumulates REI-P counts 32-bit saturation counter. Software program RXPOH block accumulate either errors, error events. error event defined frame containing non-zero REI-P count.
Serial Hardware extraction (SOH)
available serially through optional hardware serial extraction (SOH). timing diagrams showing serial extraction bytes, "Midbus" page
Transmitter Description
transmitter blocks (TXPOH TXTOH) STS3CFRM allow flexible insertion transport path overhead bytes, through software optional hardware insertion (SOH). blocks also perform primitive SONET tasks such data scrambling, BIP-8 calculation insertion. possible software adjust location STS3CFRM's within STS-1 frame. When transmitter resets frame (stxfr) output asserted, framer resets internal counters starts transmitting from first byte next clock pulse.
TXTOH
TXTOH block accepts payload data from TXPOH block well from H1/H2 pointer. Software control source each byte. Possible sources software registers, optional serial hardware insertion (SOH). case byte, third possibility optional buffer (J0B).
Altera Corporation
Specifications
SONET/SDH STS-3c/STM-1 Framer MegaCore Function (STS3CFRM) User Guide
optional serial hardware insertion (SOH) separate dedicated ports bytes, just line DCC, just section DCC, combined E1/F1/E2. Software also specifies actions such AIS-L insertion, insertion, BIP-8 error insertions.
Software registers available transmitted bytes (D1-D12).
Insertion
TXTOH block allows software specify condition-which sets data bytes zero after scrambling-on transmitted data. insertion, specified, overrides other transmit frame data insertion schemes.
Scrambling
Scrambling performed output bytes except bytes. Software allows scrambling disabled test purposes.
A1/A2 Generation
test purposes, software specify error insertion A1/A2 bytes. A1/A2 errors always inserted frame boundaries. Software must also specify corrupted bytes.
Section Trace (J0) Generation
TXTOH block allows three sources transmission byte:
byte obtained from software register byte obtained from serial hardware input (SOH) byte obtained from message written software into message buffer (J0B) STS3CFRM variant implements parameter, byte insertion should disabled when downloads section trace message, otherwise portions trace message trace message mixed together transmitted stream.
Altera Corporation
SONET/SDH STS-3c/STM-1 Framer MegaCore Function (STS3CFRM) User Guide
GettiSpecifications
Generation
TXTOH block calculates BIP-8 value. Software allows errors inserted into value, calculated using mask stored software register.
Specifications
Error Mask Generation
TXTOH block calculates BIP-8 value. Software allows errors inserted into value, calculated using mask stored software register. Software must also specify corrupted bytes.
RDI-L Control (three least significant bits
These bits usually contain portions transmitted code, however, they overridden with RDI-L pattern 3'b110 following software programmable conditions occur: LOS, AIS-L. Software also force insertion RDI-L.
K1/K2 Generation
K1/K2 bytes contain code. three least significant bits byte overridden RDI-L alarm.
REI-L Generation (M1)
Software allows option automatically extracting error count most recently received frame RXTOH block.
AIS-L Control
TXTOH block allows software insert AIS-L condition transmitted data. AIS-L condition set/cleared frame boundaries. AIS-L insertion overrides other frame data insertion schemes with exception insertion.
Data Communications (D1-D12) Selection
Data Communications bytes only inserted optional serial hardware. absence serial hardware, they 'h00.
Altera Corporation
Specifications
SONET/SDH STS-3c/STM-1 Framer MegaCore Function (STS3CFRM) User Guide
TXPOH
TXPOH block receives user payload data from Midbus. Software control source each byte. Possible sources software registers, optional serial hardware insertion (SOH). case byte, third possibility optional buffer (J1B). Software also specifies actions such AIS-P insertion, BIP-8 error insertions, select automatic REI-P RDI-P calculation insertion. TXPOH block also generates H1/H2 pointer. Software force arbitrary pointer changes, NDF, positive stuff negative stuff.
Pointer Adjustments
TXPOH block allows software request pointer adjustment operations. user request positive stuff, negative stuff, actions performed. addition, user send arbitrary pointer value (H1/H2) without affecting actual alignment debugging purposes. startup, offset zero resulting byte following byte.
AIS-P Generation
TXPOH block allows AIS-P inserted into transmit stream. When software forces AIS-P, (before scrambling) inserted into bytes well bytes SPE. This continues until software releases force.
Path Trace Generation
TXPOH block allows three sources transmission byte:
byte obtained from software register byte obtained from serial hardware input (SOH) byte obtained from message written software into message buffer (J1B) STS3CFRM variant implements parameter, byte insertion should disabled when downloads path trace message, otherwise portions trace message trace message mixed together transmitted stream.
Altera Corporation
SONET/SDH STS-3c/STM-1 Framer MegaCore Function (STS3CFRM) User Guide
GettiSpecifications
Generation
TXPOH block calculates BIP-8 value. Software allows errors inserted into value, calculated using mask stored software register.
Specifications
RDI-P (G1) Generation
RDI-P signal transmitted bits byte. TXPOH block generate RDI-P signal using following three methods:
Software selects insertion software Optional serial hardware (SOH) insertion Automatic alarm monitoring
support definitions RDI-P, TXPOH block provides flexible scheme where software specify RDI-P code that sent each type detected path alarm. RDI-P codes generated according priority shown Table
higher priority alarm detected before current RDI-P code been generated frames, higher priority code generated immediately.
Table RDI-P Insertion Priority
Alarm Type
AIS-P LOP-P UNEQ-P TIM-P PLM-P LCD-P
Priority highest priority)
REI-P (G1) Generation
REI-P signal transmitted bits byte. TXPOH block generate REI-P signal using following three methods:
Software selects insertion software register Optional serial hardware (SOH) error count maintained receiver blocks most recently received frame.
Altera Corporation
Specifications
SONET/SDH STS-3c/STM-1 Framer MegaCore Function (STS3CFRM) User Guide
Interfaces Protocols
AIRbus
AIRbus interface provides access internal registers using simple synchronous internal protocol. This consists separate read data (rdata[31:0]) write data (wdata[31:0]) buses, data transfer acknowledge (dtack) signal, block select (sel). address (addr[11:2]) read (read) signal indicate location type access within block. rdata buses dtack signals merged from multiple blocks using simple function. dtack signal sustained until block removed (four-way handshaking), meaning AIRbus cross clock domain boundaries. this block AIRbus data width bits.
Midbus
Midbus interface simple synchronous full-duplex data path bus. STS3CFRM consists master slave sides, always acts master both directions. STS3CFRM Midbus runs 19.44 over single byte lane each direction. receive (RX) direction, data transferred from Midbus master (RXPOH_0) slave. transmit (TX) direction, data transferred from slave master (TXPOH_0). each direction, Midbus carry eight bits clock cycle. includes midbus receive data (mrxdat_0[7:0]) midbus receive enable(mrxena_0) lines indicate valid data transfers direction, midbus transmit data (mtxdat_0[7:0]) midbus data enable(mtxena_0) lines indicate valid data requests direction.
Receive Direction
Figure shows Midbus signals receive direction. STS3CFRM presents data mrxdat_0, rising edge rxclk. following position indicators also presented along with data.
mrxval indicates that following strobes valid, Figure mrxena indicates mrxdat user payload (PL) mrxffp indicates that mrxdat fixed frame pulse (J0) mrxefp indicates mrxdat embedded frame pulse (J1) mrxfoh indicates mrxdat fixed frame overhead (A1, this includes section line overhead, undefined/growth mrxeoh indicates mrxdat embedded frame overhead (J1, this includes path overhead
Altera Corporation
SONET/SDH STS-3c/STM-1 Framer MegaCore Function (STS3CFRM) User Guide
GettiSpecifications
Figure Receive (Drop) Example STS3CFRM with Zero Pointer Offset
Specifications
rxclk mrxdat mrxena mrxval mrxffp mrxefp mrxfoh mrxeoh
Transmit Direction
Figure shows Midbus signals transmit direction. STS3CFRM provides position commands (listed below) that indicate type byte being processed next clock pulse. mxtdat ignored when mtxena preceding clock cycle.
mtxval indicates that following strobes valid, Figure mtxena indicates user payload (PL) mtxffp indicates fixed frame pulse (J0) mtxefp indicates embedded frame pulse (J1) mtxfoh indicates fixed frame overhead (A1, this includes section line overhead, undefined/growth mtxeoh indicates embedded frame overhead (J1, this includes path overhead
STS3CFRM samples data from mtxdat rising edge txclk, following asserted high mtxena. Therefore, TOH/POH sampled they produced, Figure
Altera Corporation
Specifications
SONET/SDH STS-3c/STM-1 Framer MegaCore Function (STS3CFRM) User Guide
Figure Transmit (Add) Example STS3CFRM with Zero Pointer Offset
txclk mtxdat mtxena mtxval mtxffp mtxefp mtxfoh mtxeoh
Hardware Overhead Insertion Extraction
More detailed information Midbus, AIRbus available from Altera site Hardware Overhead Insertion/Extraction (SOH) options available create custom STS3CFRM. stated earlier, this user guide aims describe full feature STS3CFRM, hence following descriptions figures.
timing diagrams show being transmitted first. grey lines indicate boundaries. timing diagrams represent first STS-1 slot STS-3c, therefore undefined bytes shown. Also, byte occurs third STS-1 slot.
SONET Receive Serial Data Outputs
transport path overhead bytes captured brought serial ports, Figure speed serial clocks serial output ports configurable control registers.
Transport Overhead Bytes
received SONET/SDH section line overhead bytes from STS3CFRM available pins STS3CFRM (see Figure bytes multiplexed onto single stream, shown Figure rxtoh, rxtohfp, rxtohval signals updated falling edge rxtohclk.
Altera Corporation
SONET/SDH STS-3c/STM-1 Framer MegaCore Function (STS3CFRM) User Guide
GettiSpecifications
Figure Transport Overhead: Clock Signal Bits
rxtohclk rxtohfp rxtohval rxtoh
Specifications
Data Communications Bytes
data communications channels also available their pins. frame pulse necessary since they bit-oriented protocol. data valid signals updated falling edge rxtohclk, shown Figure Figure
Figure SDCC: Clock Signal Bytes
rxtohclk rxsdccval rxsdcc
Figure LDCC: Clock Signal Bytes
rxtohclk rxldccval rxldcc
E1/F1/E2 Bytes
orderwire bytes section user channel (F1) byte also brought pins. They byte-oriented require frame pulse. rxe1f1e2val signals updated falling edge rxtohclk, shown Figure
Altera Corporation
Specifications
SONET/SDH STS-3c/STM-1 Framer MegaCore Function (STS3CFRM) User Guide
Figure Orderwire: Clock Signal Bits
rxtohclk rxe1f1e2fp rxe1f1e2val rxe1f1e2
Path Overhead Bytes
nine path overhead bytes available their serial port. rxpohfp, rxpoh, rxpohval updated falling edge rxpohclk, shown Figure
Figure Path Overhead: Clock Signal Bits
rxpohclk rxpohfp rxpohval rxpoh
SONET Transmit Serial Data Input
reverse direction, transmit overhead bytes also inserted from serial ports. STS3CFRM supplies clock frame pulses user supplies data and, case txtoh txpoh lines, enable signal. Whenever enable signal high (asserted), corresponding overhead byte taken from serial stream rather than from internal registers, txldcc/txsdcc/ txe1f1e2 lines. speed serial clock's output ports configurable control registers.
Altera Corporation
SONET/SDH STS-3c/STM-1 Framer MegaCore Function (STS3CFRM) User Guide
GettiSpecifications
Transport Overhead Bytes
Figure shows transport overhead byte being enabled. enable signal particular byte asserted, byte picked from software registers. Software insertion available bytes, except data communications bytes. With exception bytes, bytes picked from txtoh line even when txtohen enable signal low, corresponding control register bits indicate that hardware insertion enabled.
Specifications
bytes never taken from txtoh pins even thought txtohrdy pulses generated those bytes. txtohfp txtohrdy signals updated falling edge txtohclk while txtohen txtoh signals sampled second rising edge txtohclk following assertion txtohrdy. data enable latched falling edge txtohclk data period.
Figure Transmit Transport Overhead: Clock Data Bits
txtohclk txtohfp txtohrdy txtohen txtoh
Data Communications Bytes
data communication bytes transmitted through hardware input only. bytes enabled taken from multiplexed txtoh serial line, they picked from txsdcc txldcc lines. Therefore, bytes used, serial input lines must grounded ensure that transmitted bytes txsdccrdy/txldccrdy signal updated falling edge txtohclk while txsdcc/txldcc signal sampled second rising edge txtohclk following assertion txsdccrdy/txldccrdy, shown Figure Figure
Altera Corporation
Specifications
SONET/SDH STS-3c/STM-1 Framer MegaCore Function (STS3CFRM) User Guide
Figure SDCC: Clock Signal Bytes
txtohclk txsdccrdy txsdcc
Figure LDCC: Clock Signal Bytes
txtohclk txldccrdy txldcc
E1/F1/E2 Bytes
orderwire (E1/E2) bytes bytes inserted both software hardware. corresponding enable signal (txtohen) high multiplexed txtoh serial line, bytes picked from txtoh line. Otherwise they picked from txe1f1e2 line, unless register control bits indicate software insertion enabled. software insertion enabled, bytes picked from registers instead txe1f1e2 line. bytes always picked from txtoh line corresponding enable signal high, regardless whether software insertion enabled not. txe1f1e2fp txe1f1e2rdy signals updated falling edge txtohclk while txe1f1e2 sampled second rising edge txtohclk following assertion txe1f1e2rdy, shown Figure
Figure Orderwire: Clock Signal Bits
txtohclk txe1f1e2fp txe1f1e2rdy txe1f1e2
Altera Corporation
SONET/SDH STS-3c/STM-1 Framer MegaCore Function (STS3CFRM) User Guide
GettiSpecifications
Path Overhead Bytes
path overhead bytes inserted both software hardware. txpohen enable signal high, corresponding bytes always picked from txpoh line. both above conditions false, bytes picked from software registers. txpohfp txpohrdy signals updated falling edge txpohclk while txpoh txpohen signals sampled second rising edge txpohclk after assertion txpohrdy, shown Figure
Specifications
Figure Path Overhead: Clock Signal Bytes
txpohclk txpohfp txpohrdy txpohen txpoh
Signals
following table lists pins used STS3CFRM.
Table Signals (Part
Port Direction Description
Receive Clock Domain Signals rxclk rxclk_en rxreset_n Receive SONET Signals srxdat[7:0] srxval srxfr Input Input Input Input SONET data byte align block. SONET byte alignment required. Indicates input SONET data valid. Forces SONET receiver reset internal row/column/slot counters. Reset value depends FP_POS_SEL RMR_CTRL register. Input Input Input Clock Flops only updated when clk_en asserted. Receive active reset
Receive Hardware Serial Extract Signals rxtohclk rxtoh rxtohval rxtohfp rxsdcc rxsdccval Output Output Output Output Output Output Receive serial Clock Receive serial data Receive serial data valid Receive serial frame pulse Receive serial section bytes Receive serial section valid
Altera Corporation
Specifications
SONET/SDH STS-3c/STM-1 Framer MegaCore Function (STS3CFRM) User Guide
Table Signals (Part
Port
rxldcc rxldccval rxe1fle2 rxe1fle2val rxe1fle2fp
Direction
Output Output Output Output Output Receive serial line bytes
Description
Receive serial section valid Receive serial E1,F1,E2 bytes Receive serial E1,F1,E2 valid Receive serial E1,F1,E2 frame pulse
Receive Hardware Serial Extract Signals rxpohclk_0 rxpoh_0 rxpohval_0 rxpohfp_0 Output Output Output Output Receive serial clock Receive serial data Receive serial data valid Receive serial frame pulse
Midbus Receive Interface Signals mrxdat_0[7:0] mrxena_0 mrxval_0 mrxffp_0 mrxefp_0 mrxfoh_0 mrxeoh_0 Output Output Output Output Output Output Output Payload output data path Indicates SONET receiver valid payload mrxdat_0 read before next rising clock edge. Indicates SONET midbus signals valid current clock cycle. Indicates mrxdat_0 carries first byte. Indicates mrxdat_0 carries first byte. Indicates mrxdat_0 carries byte. Indicates mrxdat_0 carries byte.
Transmit Clock Domain Signals txclk txclk_en txreset_n Transmit SONET Signals stxdat[7:0] stxval stxfr Output Output Input Output Output SONET data from SONET transmitter. Indicates output SONET data valid. Forces SONET transmitter reset frame start transmission from first byte. Indicates first byte frame txdata bus. Input Input Input Clock Flops only updated when clk_en asserted. Transmit active reset
stxfp
Transmit Hardware Serial Insert Signals txtohclk txtoh txtohen txtohfp Output Input Input Output Transmit serial clock Transmit serial data Transmit serial data input enable Transmit serial frame pulse
Altera Corporation
SONET/SDH STS-3c/STM-1 Framer MegaCore Function (STS3CFRM) User Guide
GettiSpecifications
Table Signals (Part
Port
txtohrdy txsdcc txsdccrdy txldcc txldccrdy txe1fle2 txe1fle2fp txe1fle2rdy
Specifications
Description
Direction
Output Input Output Input Output Input Output Output Transmit serial ready
Transmit serial section bytes Transmit serial section ready Transmit serial section bytes Transmit serial line ready Transmit serial bytes Transmit serial frame pulse Transmit serial ready
Transmit Hardware Serial Insert Signals txpohclk_0 txpoh_0 txpohen_0 txpohfp_0 txpohrdy_0 Output Input Input Output Output Transmit serial clock Transmit serial data Transmit serial data input enable Transmit serial frame pulse Transmit serial ready
Midbus Transmit Interface Signals mtxdat_0[7:0] mtxena_0 mtxval_0 mtxffp_0 mtxefp_0 mtxfoh_0 mtxeoh_0 Maintenance Signals align_data lopc AIRbus Interface Signals read addr[11:2] wdata[31:0] Input Input Input Input Select Read: High read cycles; write. Address Write data Output Input Output Output Output byte aligned data being processed SONET receive blocks Indicates Loss Optical Carrier. SONET receiver generate lopc asserted. Indicates SONET receiver Loss Signal condition. Indicates SONET receiver Loss Frame condition. Indicates SONET receiver Severely Errored Frame condition. Input Output Output Output Output Output Output Payload input data path Indicates SONET transmitter will read mtxdat_0 next rising clock edge. Indicates SONET midbus signals valid current clock cycle. Indicates SONET transmitter will generate first byte next rising clock edge. Indicates SONET transmitter will generate byte next rising clock edge. Indicates SONET transmitter will generate byte next rising clock edge. Indicates SONET transmitter will generate byte next rising clock edge.
Altera Corporation
Specifications
SONET/SDH STS-3c/STM-1 Framer MegaCore Function (STS3CFRM) User Guide
Table Signals (Part
Port
rdata[31:0] dtack
Direction
Output Output Output
Description
Read data. zeros asserted. Data transfer acknowledge Interrupt request, active high
Notes:
Required extracting payload. Enable overhead byte location. bytes available mrxdat.
Performance
Table shows required speed estimated gate count STS3CFRM APEX 20KE device.
Table Performance
4,539 7,303 Note:
Note
ESBs
Frequency (MHz)
19.44 required support 155.52 Mbps
numbers ESBs approximate 2001. They reflect range from basic full feature variant.
Software Interface
Offsets
following table lists address offsets. Each block base address thus each register requires that offset added.
Table 8.Offsets
Register Block
RXTOH_CTRL RXTOH_J0_MEM RXTOH_CAP TXTOH_CTRL TXTOH_J0_MEM RXPOH_CTRL RXPOH_J1_MEM RXPOH_CAP TXPOH_CTRL TXPOH_J1_MEM
Offset
`h000 `h100 `h200 `h400 `h500 `h600 `h700 `h800 `hA00 `hB00
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SONET/SDH STS-3c/STM-1 Framer MegaCore Function (STS3CFRM) User Guide
GettiSpecifications
Memory Maps
addresses access 32-bit registers shown hexadecimal values. value byte address, thus used. addresses even.
Specifications
Table 9.RXTOH_CTRL Memory
Address
'h10 'h14 'h18 'h1C 'h20 'h24 'h28 'h2C 'h30 'h34 'h38 'h3C 'h40 'h44 'h48 'h4C 'h50 'h54 'h58 'h5C 'h60 'h64
Register
RXTOH_CTRL RXTOH_STAT RXTOH_IS RXTOH_IE RXTOH_B1_ERR_CNT RXTOH_B2_ERR_CNT RXTOH_REIL_ERR_CNT RXTOH_K1_ACCPT RXTOH_K2_ACCPT RXTOH_S1_ACCPT RXTOH_SEF_FORCE RXTOH_LOS_THRSHD RXTOH_AUTO_AIS RXTOH_FRAMER_CTRL RXTOH_SER_CTRL RXTOH_J0_CTRL RXTOH_SD_SET_TIME RXTOH_SF_SET_TIME RXTOH_SD_SET_TH RXTOH_SF_SET_TH RXTOH_SD_BURST_TOL RXTOH_SF_BURST_TOL RXTOH_SD_CLEAR_TIME RXTOH_SF_CLEAR_TIME RXTOH_SD_CLEAR_TH RXTOH_SF_CLEAR_TH
Description
Receiver Transport Control Receiver Transport Status Receiver Transport Interrupt Status Receiver Transport Interrupt Enable Receiver Error Count Receiver Error Count Receiver REI-L Count Receiver Value Receiver Value Receiver Value Receiver Force Receiver Threshold Receiver Transport Auto-AIS Control Receiver Framer Control Receiver Transport Serial Port Control Receiver Control Receiver Monitor Interval Receiver Monitor Interval Receiver Threshold Receiver Threshold Receiver Burst Tolerance Receiver Burst Tolerance Receiver Clear Monitor Interval Receiver Clear Monitor Interval Receiver Clear Threshold Receiver Clear Threshold
Altera Corporation
Specifications
SONET/SDH STS-3c/STM-1 Framer MegaCore Function (STS3CFRM) User Guide
Table 10.RXPOH_CRTL Memory
Address
'h10 'h14 'h18 'h1C 'h20 'h24 'h28 'h2C 'h30 'h34 'h38 'h3C
Register
RXPOH_CTRL RXPOH_STAT RXPOH_IS RXPOH_IE RXPOH_RDIP RXPOH_C2 RXPOH_B3_ERR_CNT RXPOH_REIP_ERR_CNT RXPOH_CUR_PTR RXPOH_LOPC_STAT RXPOH_RESERVED RXPOH_AISC_STAT RXPOH_RESERVED RXPOH_AUTO_AIS RXPOH_SER_CTRL RXPOH_J1_CTRL
Description
Receiver Path Control Receiver Path Status Receiver Path Interrupt Status Receiver Path Interrupt Enable Receiver RDI-P Receiver Path Label (C2) Receiver Error Count Receiver REI-P Count Receiver Pointer Value Receiver LOPC Status Reserved Receiver AISC Status Reserved Receiver auto Receiver Path Serial Port Control Receiver Control
Table 11.RXPOH_CAP Memory
Address
'h10 'h14 'h18 'h1C 'h20
Register
RXPOH_CAP_J1 RXPOH_CAP_B3 RXPOH_CAP_C2 RXPOH_CAP_G1 RXPOH_CAP_F2 RXPOH_CAP_H4 RXPOH_CAP_Z3 RXPOH_CAP_Z4 RXPOH_CAP_Z5
Description
Receiver Capture Receiver Capture Receiver Capture Receiver Capture Receiver Capture Receiver Capture Receiver Capture Receiver Capture Receiver Capture
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SONET/SDH STS-3c/STM-1 Framer MegaCore Function (STS3CFRM) User Guide
GettiSpecifications
Table 12.TXTOH_CRTL Memory
Address
'h10 'h14 'h18 'h1C 'h20 'h24 'h28 'h2C 'h30 'h34 'h38 'h3C 'h40 'h44 'h48 'h4C 'h50
Specifications
Description
Transmitter Transport Control Transmitter Transport Status Transmitter Transport Interrupt Status Transmitter Transport Interrupt Enable Transmitter Error Mask Reserved Transmitter Error Mask Reserved Transmitter Error Mask Transmitter Byte Error Mask Transmitter Error Mask Transmitter Value Transmitter Value Transmitter Value Transmitter K1K2 Value Transmitter RDI-L Control Transmitter Value Transmitter M0/M1 value Transmitter Value Transmitter Serial Port Control Transmitter Control
Register
TXTOH_CTRL TXTOH_STAT TXTOH_IS TXTOH_IE TXTOH_A1_ERR_BYTES TXTOH_RESERVED TXTOH_A2_ERR_BYTES TXTOH_RESERVED TXTOH_B1_ERR_MASK TXTOH_B2_ERR_BYTES TXTOH_B2_ERR_MASK TXTOH_J0 TXTOH_E1 TXTOH_F1 TXTOH_K1K2 TXTOH_RDIL_CTRL TXTOH_S1 TXTOH_MOM1 TXTOH_E2 TXTOH_SER_CTRL TXTOH_J0_CTRL
Table 13.TXPOH_CTRL Memory
Address
'h10 'h14 'h18 'h1C
Register
TXPOH_CTRL TXPOH_STAT TXPOH_IS TXPOH_IE TXPOH_J1 TXPOH_B3_ERR_MASK TXPOH_C2 TXPOH_G1
Description
Transmitter Path Control Transmitter Path Status Transmitter Path Interrupt Status Transmitter Path Interrupt Enable Transmitter Value Transmitter Error Mask Transmitter Value Transmitter Value
Altera Corporation
Specifications
SONET/SDH STS-3c/STM-1 Framer MegaCore Function (STS3CFRM) User Guide
Table 13.TXPOH_CTRL Memory
Address
'h20 'h24 'h28 'h2C 'h30 'h34 'h38 'h3C 'h40 'h44 'h48 'h4C
Register
TXPOH_F2 TXPOH_H4 TXPOH_Z3 TXPOH_Z4 TXPOH_Z5 TXPOH_PTR_ACT TXPOH_ARB_H1 TXPOH_ARB_H2 TXPOH_CUR_PTR TXPOH_RDIP_CTRL TXPOH_SER_CTRL TXPOH_J1_CTRL
Description
Transmitter Value Transmitter Value Transmitter Value Transmitter Value Transmitter Value Transmitter Pointer Action Transmitter Arbitrary Pointer Transmitter Arbitrary Pointer Transmitter Current Offset Transmitter RDI-P Control Transmitter Path Serial Port Control Transmitter Control
Altera Corporation
SONET/SDH STS-3c/STM-1 Framer MegaCore Function (STS3CFRM) User Guide
GettiSpecifications
Registers
following table lists access codes used describe type register bits.
Specifications
Table 14.Registers
Code
RW1C RW0S RTCW RTSW RWTC RWTS RWSC RWSS Read/Write Read-Only Read/Write Clear Read/Write Read Clear Read Read Clear/Write Read Set/Write Read/Write value Clear Read/Write value Read/Write Self-Clearing Read/Write Self-Setting Unused bits/Read Unused bits/Read
Description
undefined bits within software interface registers should considered reserved future use. Their access code should considered being UR0. Reading from them will return zero, writing them will have effect.
Altera Corporation
Specifications
SONET/SDH STS-3c/STM-1 Framer MegaCore Function (STS3CFRM) User Guide
RXTOH Register Description
following tables describe registers used RXTOH block. Offsets table required offset each register.
Table 15.RXTOH_CTRL Receiver Transport Control (Part
Field
SF_EN
Bits
Access
Function
This allows software enable/disable detection SONET receiver. Writing disables detection SONET receiver. Writing enables detection SONET receiver. This allows software enable/disable detection SONET receiver. Writing disables detection SONET receiver. Writing enables detection SONET receiver. This allows software enable/disable descrambling SONET receiver. generating polynomial sequence length 127. Writing enables descrambling SONET receiver. Writing disables descrambling SONET receiver.
Default
SD_EN
DESCRAM_DIS
REIL_ERRTYPE
This allows software select between frame error monitoring REI-L (M0/M1) code. configured error, SONET receiver increments RXTOH_REIL_ERR_CNT register with M0/M1 code. configured frame error, SONET receiver increments RXTOH_REIL_ERR_CNT register each nonzero M0/M1 code. This allows software select between frame error monitoring BIP-8. configured error, SONET receiver increments RXTOH_B2_ERR_CNT register each code which error. configured frame error, SONET receiver increments RXTOH_B2_ERR_CNT register each frame which contains error. Writing configures SONET receiver count errors. Writing configures SONET receiver count frame errors.
B2_ERRTYPE
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SONET/SDH STS-3c/STM-1 Framer MegaCore Function (STS3CFRM) User Guide
GettiSpecifications
Table 15.RXTOH_CTRL Receiver Transport Control (Part
Field
B1_ERRTYPE
Specifications
Default
Bits
Access
Function
This allows software select between frame error monitoring section BIP-8. configured error, SONET receiver increments RXTOH_B1_ERR_CNT register each code which error. configured frame error, SONET receiver increments RXTOH_B1_ERR_CNT register each frame which contains error. Writing configures SONET receiver count errors. Writing configures SONET receiver count frame errors. This allows software select between SONET mode operation. mode operation determines filtering thresholds bytes such K1/K2, J0/J1 also affects pointer processing. Writing configures SONET receiver operate SONET mode. Writing configures SONET receiver operate mode.
SONET_SDH_SEL
Table 16.RXTOH_STAT Receiver Transport Status (Part
Field
Bits
Access
Function
Default
This when defect been detected. defect detected when number errors observed over given interval exceeds given threshold. This when defect been detected. defect detected when number errors observed over given interval exceeds given threshold. This when unstable counter reaches unstable counter incremented each message that differs from previously received message. This when accepted message (one which received consecutive messages) different from expected message downloaded software.
J0_INV
J0_MIS
APS_INV
This when three consecutive K1/K2 code last successive frames identical, starting with last frame containing previously consistent code.
Altera Corporation
Specifications
SONET/SDH STS-3c/STM-1 Framer MegaCore Function (STS3CFRM) User Guide
Table 16.RXTOH_STAT Receiver Transport Status (Part
Field
S1_INV
Bits
Access
Function
Default
This when unstable counter reaches unstable counter incremented each byte that differs from previously received byte. This when SONET receiver detects RDI-L incoming stream. RDI-L detected when bits (the three least significant bits) byte contains `110' pattern consecutive frames. This when SONET receiver detects AIS-L incoming stream. AIS-L detected when bits 8(the three least significant bits) byte contains `111' pattern consecutive frames. This when defect been detected SONET receiver. defect detected when timer reaches ms). This when defect been detected SONET receiver. defect detected when SONET receiver does detect correct A1/A2 bytes consecutive frames, where This when defect detected SONET receiver. defect detected when SONET receiver detects consecutive zero bytes where 1.This when SONET receiver detects correct A1/A2 bytes consecutive frames where and, during this interval, defect detected.
RDIL
AISL
Altera Corporation
SONET/SDH STS-3c/STM-1 Framer MegaCore Function (STS3CFRM) User Guide
GettiSpecifications
Table 17.RXTOH_IS Receiver Transport Interrupt Status (Part
Field
REIL APS_CONS
Specifications
Default
Bits
Access
RW1C RW1C RW1C RW1C
Function
This interrupt enabled change occurs RXTOH_STAT register. This interrupt enabled change occurs RXTOH_STAT register. This REIL interrupt enabled SONET receiver detects non-zero REI-L (M0/M1) code.
This APS_CONS interrupt enabled change occurs APS_INV RXTOH_STAT register. This J0_CONS interrupt enabled change occurs J0_INV RXTOH_STAT register. This J0_MIS interrupt enabled change occurs J0_MIS RXTOH_STAT register.
J0_CONS
RW1C
J0_MIS
RW1C
J0_NEW
RW1C
This J0_NEW interrupt enabled different consistent message detected SONET receiver. consistent message which received times succession. This S1_CONS interrupt enabled change occurs S1_INV RXTOH_STAT register. This S1_NEW interrupt enabled different consistent value detected SONET receiver. consistent value which detected consecutive frames. This K1K2_NEW interrupt enabled different consistent K1K2 value detected SONET receiver. consistent K1K2 value which detected consecutive frames. This AIS-L interrupt enabled change occurs RDIL RXTOH_STAT register. This AIS-L interrupt enabled change occurs AISL RXTOH_STAT register. This interrupt enabled SONET receiver detects error (either frame). This interrupt enabled SONET receiver detects error (either frame).
S1_CONS
RW1C
S1_NEW
RW1C
K1K2_NEW
RW1C
RDIL AISL
RW1C RW1C RW1C RW1C RW1C
This interrupt enabled change occurs RXTOH_STAT register.
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Specifications
SONET/SDH STS-3c/STM-1 Framer MegaCore Function (STS3CFRM) User Guide
Table 17.RXTOH_IS Receiver Transport Interrupt Status (Part
Field
TOH_CAP_DONE
Bits
Access
RW1C RW1C RW1C
Function
Default
This interrupt enabled change occurs RXTOH_STAT register. This interrupt enabled change occurs RXTOH_STAT register. This after RXTOH block captured last byte stored memory. captured bytes stored frame before being replaced captured bytes.
Table 18.RXTOH_IE Receiver Transport Interrupt Enable
Field
REIL APS_CONS J0_CONS J0_MIS J0_NEW S1_CONS S1_NEW K1K2_NEW RDIL AISL TOH_CAP_DONE
Bits
Access
Function
Writing enables interrupt. Writing enables interrupt. Writing enables REI-L interrupt. Writing enables consistency interrupt. Writing enables mismatch interrupt. Writing enables change interrupt. Writing enables consistency interrupt. Writing enables change interrupt. Writing enables K1/K2 change interrupt. Writing enables RDI-L interrupt. Writing enables AIS-L interrupt. Writing enables error interrupt. Writing enables error interrupt. Writing enables interrupt. Writing enables interrupt. Writing enables interrupt. Writing enables capture done.
Default
Writing enables (APS) K1/K2 consistency interrupt.
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Table 19.RXTOH_B1_ERR_CNT Receiver Error Count 'h10
Field
Specifications
Default
Bits
31:0
Access
RTCW
Function
This register contains error count accumulated since last read software. counter will stop (saturate) when count reaches 32'hffffffff. counter counts either frames errors depending value B1_ERRTYPE RXTOH_CTRL. Writing this register will load counter with value written. Reading from this register will return current count reset counter.
Table 20.RXTOH_B2_ERR_CNT Receiver Error Count 'h14
Field
Bits
31:0
Access
RTCW
Function
Default
This register contains error count accumulated since last read software. counter will stop (saturate) when count reaches 32'hffffffff. counter counts either frame errors depending value B2_ERRTYPE RXTOH_CTRL. Writing this register will load counter with value written. Reading from this register will return current count reset counter.
Table 21.RXTOH_REIL_ERR_CNT Receiver REI-L Count 'h18
Field
Bits
31:0
Access
RTCW
Function
This register contains REI-L error count accumulated since last read software. counter will stop (saturate) when count reaches 32'hffffffff. counter counts either frame errors depending value REIL_ERRTYPE RXTOH_CTRL. Writing this register will load counter with value written. Reading from this register will return current count reset counter.
Default
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SONET/SDH STS-3c/STM-1 Framer MegaCore Function (STS3CFRM) User Guide
Table 22.RXTOH_K1_ACCPT Receiver Value 'h1C
Field
Bits
Access
Function
This register provides access filtered (valid) value from SONET receiver. value valid K1/K2 pair which belongs received frames succession. This register should polled software determine various codes.
Default
Table 23.RXTOH_K2_ACCPT Receiver Value 'h20
Field
Bits
Access
Function
Default
This register provides access filtered (valid) value from SONET receiver. value valid K1/K2 pair which belongs received frames succession. This register should polled software determine various codes.
Table 24.RXTOH_S1_ACCPT Receiver Value 'h24
Field
Bits
Access
Function
This register provides access filtered (valid) value from SONET receiver. value valid received frames succession.
Default
Table 25.RXTOH_SEF_FORCE Receiver Force 'h28
Field
Bits
Access
Function
Default
Writing this will force SONET receiver framer declare defect. framer will then attempt rediscover frame. This automatically cleared when framer detects consecutive frames with correct frame alignment patterns. Writing this will have effect.
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Table 26.RXTOH_LOS_THRSHD Receiver Threshold 'h2C
Field
Specifications
Default
Bits
15:0
Access
Function
This register allows software specify number 16'hfff consecutive all-zero bytes that must seen before SONET receiver declares defect. Writing this register sets threshold. Reading from this register returns current threshold this register will result faulty operation SONET receiver.
Table 27.RXTOH_AUTO_AIS Receiver Transport Auto-AIS Control 'h30 (Part
Field
Bits
Access
Function
This enables/disables downstream path insertion when SONET receiver detects alarm (SF) when this register been This enables/disables downstream path insertion when SONET receiver detects alarm (SD) when this register been This enables/disables downstream path insertion when SONET receiver detects unstable alarm (J0_INV) when this register been
Default
J0_INV
J0_MIS
This enables/disables downstream path insertion when SONET receiver detects mismatch alarm (J0_MIS) when this register been This enables/disables downstream path insertion when SONET receiver detects loss frame alarm (LOF) when this register been This enables/disables downstream path insertion when SONET receiver detects loss signal alarm (LOS) when this register been This enables/disables downstream path insertion when loss optical carrier (LOPC) input SONET receiver becomes active when this register been
LOPC
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SONET/SDH STS-3c/STM-1 Framer MegaCore Function (STS3CFRM) User Guide
Table 27.RXTOH_AUTO_AIS Receiver Transport Auto-AIS Control 'h30 (Part
Field
Bits
Access
Function
Default
This enables/disables downstream path insertion when SONET receiver detects AIS-L alarm. This also serves global enable other auto-AIS insertion conditions SONET receiver transport section. Path inserted setting bytes 8'hff.
Table 28.RXTOH_FRAMER_CTRL Receiver Framer Control 'h34
Field
PAT_OUT
Bits
Access
Function
Default
This field allows user select from different framing algorithms when framer trying detect (OOF): '00' '01': method bits (last byte first byte) '10': method bits (last bytes first bytes) '11': method bits (last three bytes first three bytes) This field allows user select from different framing algorithms when framer trying locate frame: '00' '01': method bits (last byte first byte) '10': method bits (last bytes first bytes) '11': method bits (last three bytes first three bytes) This selects location frame reset input (srxfr). Writing this location selects input frame reset (srxfr) first byte. Writing this location selects input frame reset (srxfr) first byte (first byte following last J0/Z0 byte). This enables/disables frame reset input from being used framer locate frame byte alignment. Writing this disables frame reset input (srxfr). Writing this enables frame reset input (srxfr). Reading from this returns current value.
PAT_IN
FPPOS
FP_EN
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Table 29.RXTOH_SER_CTRL Receiver Transport Serial Port Control 'h38
Field
TOH_CLK_SPD
Specifications
Default
Bits
Access
Function
This field allows software control speed serial output ports RXTOH block. period serial clocks Period(RCLK) (TOH_CLK_SPD+1) Writing this field sets serial clock speed RXTOH block. Reading from this field returns current serial clock speed RXTOH block.
Table 30.RXTOH_J0_CTRL Receiver Control 'h3C
Field
THRSHD
Bits
Access
Function
Default
This field determines message acceptance threshold when SONET receiver filtering message. (SONET) SONET receiver accepts message after received times succession. (SDH) SONET receiver accepts message after received times succession. This field sets algorithm used SONET receiver find message alignment byte. SONET termination) ('1' most significant first byte) This field determines segment receiver trace buffer memory that accessed read using receiver trace buffer memory address range. This field sets length message being received. message length message length 10/11 message length
TYPE
READSEL
MSG_LEN
Altera Corporation
Specifications
SONET/SDH STS-3c/STM-1 Framer MegaCore Function (STS3CFRM) User Guide
Table 31.RXTOH_SD_SET_TIME Receiver Monitor Interval 'h40
Field
Bits
23:0
Access
Function
Default
This register sets sub-interval size monitor. monitor implemented using sliding window scheme where window size composed sub-intervals. declared total error count accumulated sub-intervals current window exceeds value specified RXTOH_SD_SET_TH. Writing this register will load sub-interval size monitor. sub-interval size specified units frames (125 ms). Reading from this register will return current sub-interval size.
Table 32.RXTOH_SF_SET_TIME Receiver Monitor Interval 'h44
Field
Bits
23:0
Access
Function
Default
This register sets sub-interval size monitor. monitor implemented using sliding window scheme where window size composed sub-intervals. declared total error count accumulated sub-intervals current window exceeds value specified RXTOH_SF_SET_TH. Writing this register will load sub-interval size monitor. sub-interval size specified units frames (125 ms). Reading from this register will return current sub-interval size.
Table 33.RXTOH_SD_SET_TH Receiver Threshold 'h48
Field
Bits
15:0
Access
Function
Default
This register sets threshold monitor. declared total error count current window (see SD_SET_WIN) exceeds value contained this register. Writing this register will load threshold. Reading from this register will return current threshold.
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Table 34.RXTOH_SF_SET_TH Receiver Threshold 'h4C
Field
Specifications
Default
Bits
15:0
Access
Function
This register sets threshold monitor. declared total error count current window (see SF_SET_WIN) exceeds value contained this register. Writing this register will load threshold. Reading from this register will return current threshold.
Table 35.RXTOH_SD_BURST_TOL Receiver Burst Tolerance 'h50
Field
Bits
15:0
Access
Function
Default
This register specifies maximum number errors that accumulated sub-interval purpose setting/clearing alarm signal. sub-interval contains more errors than value contained this register, error count will capped value contained this register. Writing this register loads burst tolerance. Reading from this register returns current burst tolerance.
Table 36.RXTOH_SF_BURST_TOL Receiver Burst Tolerance 'h54
Field
Bits
15:0
Access
Function
Default
This register specifies maximum number errors that accumulated sub-interval purpose setting/clearing alarm signal. sub-interval contains more errors than value contained this register, error count will capped value contained this register. Writing this register loads burst tolerance. Reading from this register returns current burst tolerance.
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SONET/SDH STS-3c/STM-1 Framer MegaCore Function (STS3CFRM) User Guide
Table 37.RXTOH_SD_CLEAR_TIME Receiver Clear Monitor Interval 'h58
Field
Bits
23:0
Access
Function
Default
This register sets sub-interval size clear monitor. clear monitor implemented using sliding window scheme where window size composed sub-intervals. declared total error count accumulated sub-intervals current window exceeds value specified RXTOH_SD_SET_TH. Writing this register will load sub-interval size clear monitor. sub-interval size specified units frames (125 ms). Reading from this register will return current sub-interval size.
Table 38.RXTOH_SF_CLEAR_TIME Receiver Clear Monitor Interval 'h5C
Field
Bits
23:0
Access
Function
Default
This register sets sub-interval size clear monitor. clear monitor implemented using sliding window scheme where window size composed sub-intervals. declared total error count accumulated sub-intervals current window exceeds value specified RXTOH_SF_SET_TH. Writing this register will load sub-interval size clear monitor. sub-interval size specified units frames (125 ms). Reading from this register will return current sub-interval size.
Table 39.RXTOH_SD_CLEAR_TH Receiver Clear Threshold 'h60
Field
Bits
15:0
Access
Function
Default
This register sets threshold clear monitor. declared total error count current window (see SD_CLR_WIN) below value contained this register. Writing this register will load threshold. Reading from this register will return current threshold.
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Table 40.RXTOH_SF_CLEAR_TH Receiver Clear Threshold 'h64
Field
Specifications
Default
Bits
15:0
Access
Function
This register sets threshold clear monitor. declared total error count current window (see SF_CLR_WIN) below value contained this register. Writing this register will load threshold. Reading from this register will return current threshold.
RXPOH Register Description
following tables describe registers used RXPOH block. Offsets table required offset each register.
Table 41.RXPOH_CTRL Receiver Path Control (Part
Field
CHECK_STUFF
Bits
Access
Function
Default
This allows software enable/disable implementation SONET standard recommendation that pointer increment decrement operation detected within frames another pointer change operation (i.e., positive stuff, negative stuff, NDF) shall ignored. Writing disables implementation above recommendation.All pointer increment/decrement operations detected during normal pointer state will accepted. Writing enables implementation above recommendation. pointer increment/decrement operations detected within frames another pointer change operation will ignored interpreted invalid pointers. multiple positive/negative pointers received succession within frames pointer change operation, them will interpreted invalid pointers. This allows software specify RDI-P type monitored SONET receiver. Writing sets RDI-P type single RDI-P. SRDI-P uses byte. Writing sets RDI-P type enhanced RDI-P. ERDI-P uses bits byte.
RDIP_TYPE
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Table 41.RXPOH_CTRL Receiver Path Control (Part
Field
REIP_ERRTYPE
Bits
Access
Function
Default
This allows software select between frame error monitoring REI-P code. REI-P code bits through byte. configured error, SONET receiver increments RXPOH_REIP_ERR_CNT register with value REI-P code. configured frame error, SONET receiver increments RXPOH_REIP_ERR_CNT register each non-zero REI-P code. Writing configures SONET receiver count REI-P errors. Writing configures SONET receiver count REI-P frame errors. This allows software select between frame error monitoring path BIP-8. configured error, SONET receiver increments RXPOH_B3_ERR_CNT register each code which error. configured frame error, SONET receiver increments RXPOH_B3_ERR_CNT register each frame which contains error. definition code. Writing configures SONET receiver count errors. Writing configures SONET receiver count frame errors.
B3_ERRTYPE
Table 42.RXPOH_STAT Receiver Path Status (Part
Field
TIMP
Bits
Access
Function
Default
This when accepted message (one which received consecutive messages, depending THRSHD RXPOH_J1_CTRL) different from expected message downloaded software. This when accepted message (one which received consecutive messages, depending THRSHD RXPOH_J1_CTRL) identical expected message downloaded software. This when unstable counter reaches unstable counter incremented each message that differs from previously received message. This when same message received consecutive messages, depending THRSHD RXPOH_J1_CTRL. unstable counter also cleared.
J1_INV
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Table 42.RXPOH_STAT Receiver Path Status (Part
Field
PUNEQ
Specifications
Default
Bits
Access
Function
This when accepted path label (C2) code RXPOH_C2 matches pattern which indicates PUNEQ defect. This when accepted path label (C2) code RXPOH_C2 matches pattern which indicates PLM-P defect. PLM-P defect declared accepted code 8'h00 expected code anything 8'h00. This when unstable counter reaches unstable counter incremented each byte that differs from previously received byte. This when same byte received consecutive frames. unstable counter also cleared. This when accepted RDI-P code RXPOH_RDIP matches pattern which indicates RDI-P defect. single RDI-P (SRDI-P), RDI-P defect detected accepted RDI-P code enhanced RDI-P (ERDI-P), RDI-P defect detected accepted RDI-P code either 010, 101, 110. This when RDI-P unstable counter reaches where value RDIP_THRSHD field RXPOH_RDIP register. RDI-P unstable counter incremented each code that differs from previously received byte. This when same RDI-P code received consecutive frames. RDI-P unstable counter also cleared. Regardless RDI-P type selected, bits always used determining consistency state RDIP code. This when SONET receiver path processor detects incoming stream. detected when pointer interpretation finite state machine (FSM) path processor state. This when pointer interpretation path processor state.
PLMP
C2_INV
RDIP
RDIP_INV
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SONET/SDH STS-3c/STM-1 Framer MegaCore Function (STS3CFRM) User Guide
Table 42.RXPOH_STAT Receiver Path Status (Part
Field
AISP
Bits
Access
Function
Default
This when SONET receiver path processor detects AIS-P incoming stream. AIS-P detected when pointer interpretation path processor state. This when pointer interpretation path processor state.
Table 43.RXPOH_IS Receiver Path Interrupt Status (Part
Field
AISC LOPC TIMP
Bits
Access
RW1C RW1C RW1C
Function
This AISC interrupt enabled change occurs RXSPOH_AISC_STAT register.
Default
This TIMP interrupt enabled change occurs TIMP RXPOH_STAT register. This J1_CONS interrupt enabled change occurs J1_INV RXPOH_STAT register. This J1_NEW interrupt enabled different consistent message detected SONET receiver. consistent message which received times succession. This RDIP_CONS interrupt enabled change occurs RDIP_INV RXPOH_STAT register.
J1_CONS
RW1C
J1_NEW
RW1C
RDIP_CONS
RW1C
RDIP_NEW
RW1C
This RDIP_NEW interrupt enabled different RDI-P value accepted SONET receiver. RDI-P value accepted SONET receiver detected frames succession, where value RDIP_THRSHD. This REIP interrupt enabled SONET receiver detects non-zero REI-P (bits through byte) code. This PUNEQ interrupt enabled change occurs PUNEQ RXPOH_STAT register.
REIP
RW1C
PUNEQ
RW1C
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Table 43.RXPOH_IS Receiver Path Interrupt Status (Part
Field
PLMP
Specifications
Default
Bits
Access
RW1C
Function
This PLMP interrupt enabled change occurs PLMP RXPOH_STAT register. This C2_CONS interrupt enabled change occurs C2_INV RXPOH_STAT register.
C2_CONS
RW1C
C2_NEW
RW1C
This C2_NEW interrupt enabled different value accepted SONET receiver. value accepted SONET receiver detected frames succession. This interrupt enabled SONET receiver detects error (either frame). This high AIS_PTR interrupt enabled SONET receiver path processor detects pointer current frame. pointer defined pointer with bits
B3_ERR AIS_PTR
RW1C RW1C
PTR_CHANGE
RW1C
This high PTR_CHANGE interrupt enabled SONET receiver path processor accepted pointer value. This high NEW_PTR interrupt enabled SONET receiver path processor detects pointer current frame. pointer defined legal pointer with disabled whose value different from currently used SONET receiver path processor. This high INV_PTR interrupt enabled SONET receiver path processor detects pointer current frame. pointer defined pointer that neither pointer, pointer, decrement pointer, increment pointer, pointer.
NEW_PTR
RW1C
INV_PTR
RW1C
DEC_PTR
RW1C
This high DEC_PTR interrupt enabled SONET receiver path processor detects negative stuff pointer while pointer interpretation normal pointer state. This high INC_PTR interrupt enabled SONET receiver path processor detects negative stuff pointer while pointer interpretation NORM state.
INC_PTR
RW1C
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SONET/SDH STS-3c/STM-1 Framer MegaCore Function (STS3CFRM) User Guide
Table 43.RXPOH_IS Receiver Path Interrupt Status (Part
Field
NDF_PTR
Bits
Access
RW1C
Function
This high NDF_PTR interrupt enabled SONET receiver path processor detects pointer.
Default
AISP
RW1C RW1C
This interrupt enabled change occurs RXPOH_STAT register. This AISP interrupt enabled change occurs AISP RXPOH_STAT register.
POH_CAP_DONE
RW1C
This POH_CAP_DONE interrupt enabled after RXPOH block captured last byte (Z5) stored memory. captured bytes stored frame before being replaced captured bytes.
Table 44.RXPOH_IE Receiver Path Interrupt Enable (Part
Field
AISC LOPC TIMP J1_CONS J1_NEW RDIP_CONS RDIP_NEW REIP PUNEQ PLMP C2_CONS C2_NEW B3_ERR AIS_PTR PTR_CHANGE NEW_PTR INV_PTR DEC_PTR INC_PTR NDF_PTR
Bits
Access
Function
Writing enables AISC interrupt. Writing enables LOPC interrupt. Writing enables TIM-P interrupt. Writing enables consistency interrupt. Writing enables change interrupt. Writing enables RDI-P consistency interrupt. Writing enables RDI-P change interrupt. Writing enables REI-P interrupt. Writing enables UEQ-P interrupt. Writing enables interrupt. Writing enables consistency interrupt. Writing enables change interrupt. Writing enables error interrupt. Writing enables pointer interrupt. Writing enables H1/H2 pointer change interrupt. Writing enables H1/H2 pointer interrupt. Writing enables invalid H1/H2 pointer interrupt. Writing enables negative stuff interrupt. Writing enables positive stuff interrupt. Writing enables interrupt.
Default
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Table 44.RXPOH_IE Receiver Path Interrupt Enable (Part
Field
AISP POH_CAP_DONE
Specifications
Default
Bits
Access
Function
Writing enables interrupt. Writing enables AIS-P interrupt. Writing enables capture done interrupt.
Table 45.RXPOH_RDIP Receiver RDI-P 'h10
Field
ACCPT
Bits
Access
Function
Default
This field provides access filtered (valid) RDI-P value from SONET receiver. RDI-P value valid received frames succession, where value RDIP_THRSHD field. This field allows software specify number consecutive identical RDI-P codes (bits byte) that must observed SONET receiver before accepted.
THRSHD
Table 46.RXPOH_C2 Receiver Path Label (C2) 'h14
Field
ACCPT
Bits
15:8
Access
Function
Default
This field provides access filtered (valid) value 8'hff from SONET receiver. value valid received frames succession. This field allows software specify expected path label 8'hff (C2) value. This field compared with accepted value C2_ACCPT monitor PUNEQ PLM-P defects.
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Table 47.RXPOH_B3_ERR_CNT Receiver Error Count 'h18
Field
Bits
31:0
Access
RTCW
Function
Default
This register contains error count accumulated since last read software. counter will stop (saturate) when count reaches 32'hffffffff. counter counts either frames errors depending value B3_ERRTYPE RXPOH_CTRL. Writing this register will load counter with value written. Reading from this register will return current count reset counter.
Table 48.RXPOH_REIP_ERR_CNT Receiver REI-P Count 'h1C
Field
Bits
31:0
Access
RTCW
Function
Default
This register contains REI-P error count accumulated since last read software. counter will stop (saturate) when count reaches 32'hffffffff. counter counts either frames errors depending value REIP_ERRTYPE RXPOH_CTRL. Writing this register will load counter with value written. Reading from this register will return current count reset counter.
Table 49.RXPOH_CUR_PTR Receiver Pointer Value 'h20
Field
Bits
Access
Function
This register provides access current pointer interpreted SONET receiver path processor from H1/H2 bytes used SONET receiver locate start incoming frame.
Default
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Table 50.RXPOH_LOPC_STAT Receiver LOPC Status 'h24
Field
Specifications
Function Default
Bits
Access
This register contains concatenation indicator interpreter status numbers (with being first STS) path. concatenation indicators located bytes numbers through STS-Nc path. supposed contain value 16'b1001ss11_11111111. This register changes most once frame. concatenation indicator interpreter number LOPC state, concatenation indicator interpreter number LOPC state.
Table 51.RXPOH_RESERVED Reserved 'h28
Field
RESERVED
Bits
-1:0
Access
RESERVED
Function
Default
Table 52.RXPOH_AISC_STAT Receiver AISC Status 'h2C
Field
Bits
Access
Function
Default
This register contains concatenation indicator interpreter status numbers (with being first STS) path. concatenation indicators located bytes numbers through STSNc path. supposed contain value 16'b1001ss11_11111111. This register changes most once frame. concatenation indicator interpreter number AISC state, concatenation indicator interpreter number AISC state.
Table 53.RXPOH_RESERVED Reserved 'h30
Field
RESERVED
Bits
-1:0
Access
RESERVED
Function
Default
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Table 54.RXPOH_AUTO_AIS Receiver auto 'h34
Field
C2_INV
Bits
Access
Function
Default
This enables/disables downstream insertion when SONET receiver detects unstable alarm (C2_INV) when this register been This enables/disables downstream insertion when SONET receiver detects path unequipped alarm (UNEQ) when this register been This enables/disables downstream insertion when SONET receiver detects path label mismatch alarm (PLM) when this register been This enables/disables downstream insertion when SONET receiver detects unstable alarm (J1_INV) when this register been
UNEQ
J1_INV
TIMP
This enables/disables downstream insertion when SONET receiver detects path trace indicator mismatch alarm (TIM-P) when this register been This enables/disables downstream insertion when SONET receiver detects loss pointer alarm (LOP) when this register been
This enables/disables downstream (midbus) insertion when SONET receiver detects AIS-P alarm. This also serves global enable other autoAIS insertion conditions SONET receiver path section. insertion midbus causes extracted payload bytes 'mrxdat' port ones.
Table 55.RXPOH_SER_CTRL Receiver Path Serial Port Control 'h38
Field
POH_CLK_SPD
Bits
Access
Function
Default
This field allows software control speed serial output ports RXPOH block. period serial clocks Period(RCLK) (POH_CLK_SPD+1) Writing this field sets serial clock speed RXPOH block. Reading from this field returns current serial clock speed RXPOH block.
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Table 56.RXPOH_J1_CTRL Receiver Control 'h3C
Field
THRSHD
Specifications
Function Default
Bits
Access
This field determines message acceptance threshold when SONET receiver filtering message. (SONET) SONET receiver accepts message after received times succession. (SDH) SONET receiver accepts message after received times succession. This field sets algorithm used SONET receiver find message alignment byte. SONET termination) ('1' most significant first byte)
TYPE
READSEL
This field determines segment receiver trace buffer memory that accessed read using receiver trace buffer memory address range. read from valid message buffer. read from expected message buffer. This field sets length message being received. message length message length 10/11 message length
MSG_LEN
RXPOH_CAP Register Description
following tables describe registers used RXPOH_CAP block. Offsets table required offset each register.
Table 57.RXPOH_CAP_J1 Receiver Capture
Field
Bits
Access
Function
Default
This register contains value captured RXPOH block. After each byte captured, stored this register frame before overridden with next captured byte.
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Table 58.RXPOH_CAP_B3 Receiver Capture
Field
Bits
Access
Function
Default
This register contains value captured RXPOH block. After each byte captured, stored this register frame before overridden with next captured byte.
Table 59.RXPOH_CAP_C2 Receiver Capture
Field
Bits
Access
Function
Default
This register contains value captured RXPOH block. After each byte captured, stored this register frame before overridden with next captured byte.
Table 60.RXPOH_CAP_G1 Receiver Capture
Field
Bits
Access
Function
Default
This register contains value captured RXPOH block. After each byte captured, stored this register frame before overridden with next captured byte.
Table 61.RXPOH_CAP_F2 Receiver Capture 'h10
Field
Bits
Access
Function
This register contains value captured RXPOH block. After each byte captured, stored this register frame before overridden with next captured byte.
Default
Table 62.RXPOH_CAP_H4 Receiver Capture 'h14
Field
Bits
Access
Function
Default
This register contains value captured RXPOH block. After each byte captured, stored this register frame before overridden with next captured byte.
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SONET/SDH STS-3c/STM-1 Framer MegaCore Function (STS3CFRM) User Guide
GettiSpecifications
Table 63.RXPOH_CAP_Z3 Receiver Capture 'h18
Field
Specifications
Function Default
Bits
Access
This register contains value captured RXPOH block. After each byte captured, stored this register frame before overridden with next captured byte.
Table 64.RXPOH_CAP_Z4 Receiver Capture 'h1C
Field
Bits
Access
Function
Default
This register contains value captured RXPOH block. After each byte captured, stored this register frame before overridden with next captured byte.
Table 65.RXPOH_CAP_Z5 Receiver Capture 'h20
Field
Bits
Access
Function
This register contains value captured RXPOH block. After each byte captured, stored this register frame before overridden with next captured byte.
Default
TXTOH Register Description
following tables describe registers used TXTOH block. Offsets table required offset each register.
Table 66.TXTOH_CTRL Transmitter Transport Control (Part
Field
M0M1_RX_INS
Bits
Access
Function
Default
This field allows software specify insertion method M0/M1 byte transmitted frame. from receiver (RXTOH_B2_ERR). from other source (software hardware) M0M1_HW_INS TXTOH_SER_CTRL. Note that even hardware insertion selected, M0/M1 byte still taken from txtoh txtohen high M0/M1 bits.
Altera Corporation
Specifications
SONET/SDH STS-3c/STM-1 Framer MegaCore Function (STS3CFRM) User Guide
Table 66.TXTOH_CTRL Transmitter Transport Control (Part
Field
RDIL_FORCE
Bits
Access
Function
Default
This allows software enable/disable RDI-L insertion transmit stream. RDI-L inserted setting bits byte 3'b110. TXTOH_RDIL_CTRL. RDI-L priority over normal insertion code into byte. However, superseded AIS-L insertion. Writing this enables RDI-L insertion transmit stream. Writing this disables RDI-L insertion transmit stream. This allows software enable/disable AIS-L insertion transmit stream. AIS-L inserted writing ones every byte transmitted frame except section overhead bytes. AIS-L higher priority than other frame data transmission control with exception insertion. insertion AIS-L determined frame boundaries, i.e., AIS-L insertion will begin first byte frame immediately following enabling AIS-L insertion. Writing this enables AIS-L insertion transmit stream. Writing this disables AIS-L insertion transmit stream. This allows software enable/disable insertion transmit stream. inserted writing zeros every byte transmitted frame. higher priority than other frame data transmission control. insertion disabled. insertion enabled.
AISL_FORCE
LOS_INS
SCRAM_DIS
Scrambling controlled frame boundaries. That TXTOH block samples software control register beginning each frame scrambling performed entire frame. This allows software enable/disable scrambling SONET transmitter. scrambling algorithm identical descrambling algorithm. generating polynomial sequence length 127. Writing enables scrambling SONET transmitter. Writing disables scrambling SONET transmitter.
Altera Corporation
SONET/SDH STS-3c/STM-1 Framer MegaCore Function (STS3CFRM) User Guide
GettiSpecifications
Table 66.TXTOH_CTRL Transmitter Transport Control (Part
Field
B2_ERRINS
Specifications
Default
Bits
Access
Function
This allows software enable/disable error insertion transmit stream. Writing this enables error insertion transmit stream. error mask (TXTOH_B2_ERR_MASK) applied bytes determined TXTOH_B2_ERR_BYTES. Writing this disables error insertion transmit stream This allows software enable/disable A1/A2 error insertion transmit stream. erred hard coded 8'h09. (normally 8'hf6) erred hard coded 8'hd7. (normally 8'h28) Writing this enables A1/A2 error insertion transmit stream. bytes effected determined TXTOH_A1_ERR_BYTES, TXTOH_A2_ERR_BYTES. Writing this disables A1/A2 error insertion transmit stream.
A1A2_ERRINS
Table 67.TXTOH_STAT Transmitter Transport Status
Field
RESERVED
Bits
-1:0
Access
RESERVED
Function
Default
Table 68.TXTOH_IS Transmitter Transport Interrupt Status
Field
RESERVED
Bits
-1:0
Access
RESERVED
Function
Default
Table 69.TXTOH_IE Transmitter Transport Interrupt Enable
Field
RESERVED
Bits
-1:0
Access
RESERVED
Function
Default
Altera Corporation
Specifications
SONET/SDH STS-3c/STM-1 Framer MegaCore Function (STS3CFRM) User Guide
Table 70.TXTOH_A1_ERR_BYTES Transmitter Error Mask 'h10
Field
Bits
Access
Function
Default
This register allows software specify slots which corrupted A1/A2 error insertion been enabled. A1A2_ERRINS causes corrupt byte sent corresponding STS. represents number represents number corrupt value sent equal normal value with bits inverted (8'h09). Bits which used always
Table 71.TXTOH_RESERVED Reserved 'h14
Field
RESERVED
Bits
-1:0
Access
RESERVED
Function
Default
Table 72.TXTOH_A2_ERR_BYTES Transmitter Error Mask 'h18
Field
Bits
Access
Function
Default
This register allows software specify slots which corrupted A1/A2 error insertion been enabled. A1A2_ERRINS causes corrupt byte sent corresponding STS. represents number represents number corrupt value sent equal normal value with bits inverted (8'hd7). Bits which used always
Table 73.TXTOH_RESERVED Reserved 'h1C
Field
RESERVED
Bits
-1:0
Access
RESERVED
Function
Default
Altera Corporation
SONET/SDH STS-3c/STM-1 Framer MegaCore Function (STS3CFRM) User Guide
GettiSpecifications
Table 74.TXTOH_B1_ERR_MASK Transmitter Error Mask 'h20
Field
Specifications
Default
Bits
Access
Function
This register allows software insert error bits transmitted byte.The transmitted byte will section BIP-8 value calculated hardware XORed with contents this register.
Table 75.TXTOH_B2_ERR_BYTES Transmitter Byte Error Mask 'h24
Field
Bits
Access
Function
Default
This register allows software specify slots which corrupted insertion been enabled. B2_ERRINS causes byte(s) corresponding slot XORed with error mask B2_BIT_MASK. data bus, there's only byte slot. data bus, there bytes slot.
Table 76.TXTOH_B2_ERR_MASK Transmitter Error Mask 'h28
Field
Bits
Access
Function
Default
This register allows software specify slots which corrupted insertion been enabled. B2_ERRINS causes corresponding toggled during transmission bytes indicated B2_BYTE_MASK.
Table 77.TXTOH_J0 Transmitter Value 'h2C
Field
Bits
Access
Function
Default
This register allows software specify value transmitted TOH. contents this register written byte transmitted frame J0_BUF_INS J0_HW_INS txtohen bits.
Altera Corporation
Specifications
SONET/SDH STS-3c/STM-1 Framer MegaCore Function (STS3CFRM) User Guide
Table 78.TXTOH_E1 Transmitter Value 'h30
Field
Bits
Access
Function
Default
This register allows software specify value transmitted TOH. contents this register written byte transmitted frame E1_HW_INS txtohen bits.
Table 79.TXTOH_F1 Transmitter Value 'h34
Field
Bits
Access
Function
Default
This register allows software specify value transmitted TOH. contents this register written byte transmitted frame F1_HW_INS txtohen bits.
Table 80.TXTOH_K1K2 Transmitter K1K2 Value 'h38
Field
Bits
15:8
Access
Function
Default
This register allows software specify value transmitted TOH. contents this register written byte transmitted frame RDIL_FORCE K1K2_HW_INS txtohen bits. This register allows software specify value transmitted TOH. contents this register written byte transmitted frame K1K2_HW_INS txtohen bits
Table 81.TXTOH_RDIL_CTRL Transmitter RDI-L Control 'h3C (Part
Field
EXT_RDIL_EN
Bits
Access
Function
Default
This enables/disables insertion RDI-L from TXTOH serial pin. RDI-L inserted setting bits byte 3'b110. Writing this enables RDI-L insertion TXTOH serial pin. When most significant byte TXTOH serial then RDI-L will inserted into byte. Writing this disables RDI-L insertion TXTOH serial pin.
Altera Corporation
SONET/SDH STS-3c/STM-1 Framer MegaCore Function (STS3CFRM) User Guide
GettiSpecifications
Table 81.TXTOH_RDIL_CTRL Transmitter RDI-L Control 'h3C (Part
Field
AISL_RDIL
Specifications
Default
Bits
Access
Function
This enables/disables RDI-L insertion when AIS-L alarm detected SONET receive stream. RDI-L inserted setting bits byte 3'b110. Writing this enables RDI-L insertion when AISL alarm detected. Writing this disables RDI-L insertion when AISL alarm detected. This enables/disables RDI-L insertion when alarm detected SONET receive stream. RDI-L inserted setting bits byte 3'b110. Writing this enables RDI-L insertion when alarm detected. Writing this disables RDI-L insertion when alarm detected. This enables/disables RDI-L insertion when alarm detected SONET receive stream. RDI-L inserted setting bits byte 3'b110. Writing this enables RDI-L insertion when alarm detected. Writing this disables RDI-L insertion when alarm detected.
LOF_RDIL
LOS_RDIL
Table 82.TXTOH_S1 Transmitter Value 'h40
Field
Bits
Access
Function
Default
This register allows software specify value transmitted TOH. contents this register written byte transmitted frame S1_HW_INS txtohen bits.
Table 83.TXTOH_MOM1 Transmitter M0/M1 value 'h44
Field
Bits
Access
Function
Default
This register allows software specify M0/M1 value transmitted TOH. contents this register written M0/M1 byte transmitted frame M0M1_RX_INS M0M1_HW_INS txtohen M0M1 bits.
Altera Corporation
Specifications
SONET/SDH STS-3c/STM-1 Framer MegaCore Function (STS3CFRM) User Guide
Table 84.TXTOH_E2 Transmitter Value 'h48
Field
Bits
Access
Function
Default
This register allows software specify value transmitted TOH. contents this register written byte transmitted frame E2_HW_INS txtohen bits.
Table 85.TXTOH_SER_CTRL Transmitter Serial Port Control 'h4C (Part
Field
E2_HW_INS
Bits
Access
Function
Default
This allows software specify insertion method byte transmitted frame. from software register (TXTOH_E2). from serial hardware input. hardware insertion specified, byte transmitted either taken from TXE1F1E2 txtoh TXTOHEN high bits). Note that even this byte still taken from txtoh txtohen high bits. This field allows software specify insertion method M0/M1 byte transmitted frame. from software register (TXTOH_M0M1). from serial hardware input. Note that even hardware insertion selected, M0/M1 byte still taken from txtoh txtohen high M0/M1 bits. Also note M0M1_RX_INS TXTOH_CTRL register overrides this field. This allows software specify insertion method byte transmitted frame. from software register (TXTOH_S1). from serial hardware input. Note that even this byte still taken from txtoh txtohen high bits.
M0M1_HW_INS
S1_HW_INS
Altera Corporation
SONET/SDH STS-3c/STM-1 Framer MegaCore Function (STS3CFRM) User Guide
GettiSpecifications
Table 85.TXTOH_SER_CTRL Transmitter Serial Port Control 'h4C (Part
Field
K1K2_HW_INS
Specifications
Default
Bits
Access
Function
This allows software specify insertion method byte bits through byte transmitted frame. Insertion method bits through transmitted byte controlled RDIL_FORCE. from software register (TXTOH_K1K2). from serial hardware input. Note that even this byte still taken from txtoh txtohen high bits. Note that even this byte still taken from txtoh txtohen high bits. This allows software specify insertion method byte transmitted frame. from software register (TXTOH_F1). from serial hardware input. Note that even this byte still taken from txtoh txtohen high bits. This allows software specify insertion method byte transmitted frame. from software register (TXTOH_E1). from serial hardware input. Note that even this byte still taken from txtoh txtohen high bits. This allows software specify insertion method byte transmitted frame. from software register (TXTOH_J0). from serial hardware input. Note that even this byte still taken from txtoh txtohen high bits. Also note, J0_BUF_INS TXTOH_J0_CTRL overrides this field. This field allows software control speed serial output ports TXTOH block. period serial clocks Period(TCLK) (TOH_CLK_SPD+1) Writing this field sets serial clock speed TXTOH block. Reading from this field returns current serial clock speed TXTOH block.
F1_HW_INS
E1_HW_INS
J0_HW_INS
TOH_CLK_SPD
Altera Corporation
Specifications
SONET/SDH STS-3c/STM-1 Framer MegaCore Function (STS3CFRM) User Guide
Table 86.TXTOH_J0_CTRL Transmitter Control 'h50
Field
BUF_INS
Bits
Access
Function
Default
This allows software specify insertion method byte transmitted frame. insert from transmit trace buffer memory. insert from other source (software hardware) J0_HW_INS TXTOH_SER_CTRL. Note that even this field set, byte still taken from txtoh txtohen high bits. This field allows software specify length message transmitter trace buffer memory. message length message length 10/11 message length
MSG_LEN
TXPOH Register Description
following tables describe registers used TXPOH block. Offsets table required offset each register.
Table 87.TXPOH_CTRL Transmitter Path Control (Part
Field
REIP_AUTO_INS
Bits
Access
Function
Default
This field allows software specify insertion method bits through byte transmitted frame. from receiver (B3_ERR_CNT) from other source (software hardware) REIP_HW_INS TXPOH_SER_CTRL Note that even hardware insertion (10) selected, REI-P bits byte still taken from txpoh txpohen high REI-P bits.
Altera Corporation
SONET/SDH STS-3c/STM-1 Framer MegaCore Function (STS3CFRM) User Guide
GettiSpecifications
Table 87.TXPOH_CTRL Transmitter Path Control (Part
Field
RDIP_AUTO_INS
Specifications
Default
Bits
Access
Function
This field allows software specify insertion method bits byte transmitted frame. from receiver status. from other source (software hardware) RDIP_HW_INS TXPOH_SER_CTRL Note that even hardware insertion selected, RDIP bits byte still taken from txpoh txpohen high RDI-P bits. this field each RDI-P code generated transmitted frames unless alarm with higher priority than current RDI-P code detected. This allows software enable/disable AIS-P insertion transmit stream. AIS-P inserted writing ones bytes well bytes SPE. Writing this enables AIS-P insertion transmit stream. Writing this disables AIS-P insertion transmit stream.
AISP_INS
T

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