Packet Processor Mbps MegaCore Function PP155 December 2000

The Datasheet Archive - 100 Million Datasheets from 7500 Manufacturers.

Packet Processor Mbps MegaCore Function PP155 December 2000

Datasheet Thumbnail

Top Searches for this datasheet

MegaCore
Packet Processor Mbps MegaCore Function
PP155
December 2000 User Guide Version 1.00
Innovation Drive Jose, 95134 (408) 544-7000 http://www.altera.com
A-UG-IPPP155-1.0
Packet Processor Mbps MegaCore Function (PP155) User Guide
Copyright
Altera, APEX, APEX 20K, MegaCore, MegaWizard, OpenCore, Quartus trademarks and/or service marks Altera Corporation United States other countries. Altera Corporation acknowledges trademarks other organizations their respective products services mentioned this document. Altera products protected under numerous U.S. foreign patents pending applications, maskwork rights, copyrights. Altera warrants performance semiconductor products current specifications accordance with Altera's standard warranty, reserves right make changes products services time without notice. Altera assumes responsibility liability arising application information, product, service described herein except expressly agreed writing Altera Corporation. Altera customers advised obtain latest version device specifications before relying published information before placing orders products services. Copyright 2000 Altera Corporation. rights reserved.
Altera Corporation
About this User Guide
User Guide
This user guide provides comprehensive information about Altera® Packet Processor Mbps MegaCore® Function (PP155). Table shows user guide revision history. Table Revision History Revision
1.00
Date
Dec. 2000 First Release
Description
Find Information
Adobe Acrobat Find feature allows search contents file. Click binoculars icon toolbar open Find dialog box, click right mouse button pull-down menu. Bookmarks serve additional table contents. Thumbnail icons, which provide miniature previews each page, provide link pages. Numerous links, shown green text, allow jump related information.
Altera Corporation
About this User Guide
Packet Processor Mbps MegaCore Function (PP155) User Guide
Contact Altera
most up-to-date information about Altera products, Altera world-wide site http://www.altera.com. additional information about Altera products, consult sources shown Table
Table Contact Altera Information Type
Altera Literature Services Non-technical customer service
Access
Electronic mail Telephone hotline
Canada
lit_req@altera.com (800) SOS-EPLD
Other Locations
lit_req@altera.com (408) 544-7000 (7:30 a.m. 5:30 p.m. Pacific Time) (408) 544-7606 (408) 544-7000 (7:30 a.m. 5:30 p.m. Pacific Time) (408) 544-6401 telecom@altera.com ftp.altera.com (408) 544-7104 http://www.altera.com
Technical support Telephone hotline
(408) 544-7606 (800) 800-EPLD (6:00 a.m. 6:00 p.m. Pacific Time) (408) 544-6401 telecom@altera.com ftp.altera.com (408) 544-7104 http://www.altera.com
Electronic mail site General product information Note:
Telephone World-wide site
also contact your local Altera sales office sales representative.
Altera Corporation
Packet Processor Mbps MegaCore Function (PP155) User Guide
About this User Guide
Typographic Conventions
Table Conventions Visual
Bold Type with Initial Capital Letters bold type
Packet Processor Mbps MegaCore Function (PP155) User Guide uses typographic conventions shown Table
Meaning
Command names, dialog titles, checkbox options, dialog options shown bold, initial capital letters. Example: Save dialog box. External timing parameters, directory names, project names, disk drive names, filenames, filename extensions, software utility names shown bold type. Examples: fMAX, \maxplus2 directory, drive, chiptrip.gdf file. Book titles shown bold italic type with initial capital letters. Example: 1999 Device Data Book. Document titles shown italic type with initial capital letters. Example: (High-Speed Board Design). Internal timing parameters variables shown italic type. Examples: tPIA, Variable names enclosed angle brackets shown italic type. Example: <file name>, <project name>.pof file. Keyboard keys menu names shown with initial capital letters. Examples: Delete key, Options menu. References sections within document titles Quartus MAX+PLUS Help topics shown quotation marks. Example: "Configuring FLEX FLEX 8000 Device with BitBlasterDownload Cable." Signal port names shown lowercase Courier type. Examples: data1, tdi, input. Active-low signals denoted suffix e.g., reset_n. Anything that must typed exactly appears shown Courier type. example: Also, sections actual file, such Report File, references parts files (e.g., AHDL keyword SUBDESIGN), well logic function names (e.g., TRI) shown Courier.
Bold italic type Italic Type with Initial Capital Letters Italic type
Initial Capital Letters "Subheading Title"
Courier type
c.,. Numbered steps used list items when sequence items important, such steps listed procedure. Bullets used list items when sequence items important. checkmark indicates procedure that consists step only. hand points information that requires special attention. angled arrow indicates should press Enter key. feet direct more information particular topic.
Altera Corporation
About this User Guide
Packet Processor Mbps MegaCore Function (PP155) User Guide
Abbreviations Acronyms
ACCM AHDL AIRbus Atlantic (16/32) CRC-CCITT EDIF FIFO HDLC Midbus Mbps POS-PHY RXHLDC SONET STS-3 TXHLDC VHDL
Asynchronous Control Character Altera Hardware Description Language Access Internal Registers interface Atlantic interface Cyclic Redundancy Check 32-bit Cyclic Redundancy Check Electronic Design Automation Electronic Design Interchange Format Embedded System Block Frame Check Sequence First First Hardware Description Language High-Level Data Link Control Intellectual Property Logic Element Least Significant Least Significant Byte Middle interface Megabits second Most Significant Most Significant Byte Personal computer Packet Over SONET Physical layer Point-to-Point Protocol Receive Receive High-Level Data Link Control sub-block Synchronous Digital Hierarchy Synchronous Optical Network Synchronous Payload Envelope System Transport Signal level Transmit Transmit High-Level Data Link Control sub-block VHSIC Hardware Description Language
Altera Corporation
Contents
User Guide
Specifications
General Description.9 Features Receive Features.10 Transmit Features Functional Description Receiver Description.12 RXHDLC Descrambling.13 Processing 16/32.13 Deletion Transmitter Description TXHDLC.14 Processing 16/32.14 Scrambling Interfaces Protocols.14 Midbus.14 AIRbus.15 Atlantic Data Ordering.15 Transparency Pin-Outs.16 Performance.18 Software Interface Memory Registers Register Description.20 RX_CTRL Receive Control Register 'h00 RX_IS Receive Interrupt Register 'h02.21 RX_IE Receive Interrupt Enable Register 'h04 RX_PM_GOOD Receive Good Packet Count 'h06 RX_PM_FCS Receive Error Count 'h08.22 RX_PM_ABORT Receive Abort Count 'h0A RX_PM_RUNT Receive Runt Frame Count 'h0C
Altera Corporation
Packet Processor Mbps MegaCore Function (PP155) User Guide
Copyright
Register Description TX_CTRL Transmit Control Register 'h10 TX_IS Transmit Interrupt Register 'h12 TX_IE Transmit Interrupt Enable Register 'h14 TX_PM_GOOD Transmit Good Packet Count 'h16 TX_PM_ERR Transmit Error Packet Count 'h18
Getting Started
Design Walkthrough Obtaining Installing PP155 Installing MegaCore Files.28 Generating Custom PP155.28 Implementing System Compiling Performing Place Route Performing Synthesis Compilation Post-Routing Simulation.29 Using Third-Party Tools.29 Using Quartus Software Functional Simulation Using Visual Models Downloading Installing Visual Software.31 Licensing Configuring Device.31
Altera Corporation
viii
Specifications
User Guide
General Description
Packet Processor Mbps MegaCore® Function (PP155) uses MegaWizard® Plug-In-within Quartussoftware-to generate variants VHDL, AHDL, Verilog HDL, which instantiate into your design. Table shows optional features available generate PP155. Only basic configuration PP155 available. Note Parameters Choices
Specifications
Table Optional Features Options Basic Configuration
Note:
1,251
ESBs
numbers ESBs approximate Dec. 2000. Users strongly advised MegaWizard Plug-In Quartus software exact numbers PP155.
When finish going through wizard, generates following files:
following depending your tool selection: AHDL text design file (.tdf) VHDL design file (.vhd) Verilog design file (.v) Sample Verilog instantiation Black (_inst.v) Black module (_bb.v) Symbol files (.bsf) Quartus software used instantiate PP155 into schematic design encrypted netlist file (.e.vqm.v)
Altera Corporation
Specifications
Packet Processor Mbps MegaCore Function (PP155) User Guide
PP155 encapsulates user data packets using HDLC-type framing, compliance with Internet Request Comment (RFC1662) document. link this document, please visit Internet Engineering Task Force site http://www.ietf.org/rfc. following functions supported PP155:
RFC1662 ACCM stuffing. Non-flag inter-frame fill Transparent mode (FCS appended transmit frame) Maximum length frame check purpose this user guide, "receive" indicates data flowing into PP155 from Midbus interface transmission through Atlantic interface; "transmit" indicates data received from Atlantic interface transmission through Midbus interface. Thus Atlantic interface source transmit packets, sink received packets.
Features
Receive Features
Extraction octet-synchronous packets from single STS-3 Arbitrary packet length (one more octets) Packet delineation destuffing stuffed octets Byte-alignment (software programmable) Descrambling (software programmable) Error detection CRC-32 CRC-CCITT Flag sequence deletion deletion (software programmable) RFC1662 compliant HDLC-type framing (some sections implemented) Performance monitoring counting: Good frames Aborted frames Runt frames Error detection: Runt Optional removal
Transmit Features
RFC1662 compliant HDLC-type framing (some sections implemented)
Altera Corporation
Packet Processor Mbps MegaCore Function (PP155) User Guide
Specifications
Flag octets control-escape octets stuffing message transparency 32-bit appended packet Flag sequence insertion between packets under utilized paths Flag sharing (single flag between frames) Scrambling (software programmable) Automatic abortion case transmit underflow, host command from Atlantic interface Arbitrary packet length (one more octets) Automatic appending transmitted frames Performance monitoring counting: Good frames Underflows Aborted packets
Specifications
Functional Description
PP155 fully static, reusable, easy replicate, single channel processor interleaving) which operates octet-synchronous mode, offers full-duplex processing capability. Figure shows complete block diagram PP155, including three interfaces that support "Interfaces Protocols" page more information.
Figure Block Diagram
PP155 arxena
rxclk
rxreset_n
RXHDLC
arxdav arxdiv arxval arxdat[7:0] arxsop arxeop arxerr
Midbus
mrxdat[7:0] mrxena
Atlantic
txclk txreset_n
atxena TXHDLC atxdiv atxdav atxval atxdat[7:0] atxeop atxsop atxerr
Midbus
mtxdat[7:0] mtxena
read
dtack
wdata[15:0]
addr[4:1]
AIRbus
Altera Corporation
rdata[15:0]
Specifications
Packet Processor Mbps MegaCore Function (PP155) User Guide
Receiver Description
PP155 receives data from Midbus interface forwards RXHLDC block processing.
RXHDLC
RXHDLC block processes data incoming packet. following descriptions explain principle functions RXHLDC block. Byte Alignment Byte alignment aligns boundaries bytes (flags, CRC, etc.) with boundaries packet processor. This function necessary transmission facility does preserve byte boundaries. byte boundaries preserved SONET), this function should disabled. Assume following packet: Clock Cycle
Contents
flag flag data data flag flag
data becomes misaligned bits, bytes Midbus follows: Clock Cycle
Altera Corporation
Packet Processor Mbps MegaCore Function (PP155) User Guide
Specifications
Symptoms misalignment are:
Specifications
Extremely long packets: They typically occur during line idle, when normally carrying flags. flags longer look like flags, like packet data. above example, flags converted into 10011111. Excessive error rate: Random data patterns may, when shifted, masquerade flags hence mark start stop packets. This likely cause errors and, less likely, runts aborts.
detects misalignment, aligner reassembles data compensate. This function enabled Receive Control Register. Descrambling receive frame between-frame flags descrambled using selfsynchronizing descrambler. generator polynomial used standard x43+1. Descrambling enabled disabled Receive Control Register. inter-frame fill then discarded, frame forwarded processing. Processing Processing involves taking descrambled frame, detecting start frame frame indicated flags, removing stuff octets (control escape characters). Aborted frames also detected. 16/32 16/32 blocks check errors calculating syndrome, using either CRC-16 (x16+ x12+ CRC-32 (x32+ x26+ x22+ x16+ x12+ x11+ x10+ generator polynomial FCS. packets-good packets, packets with errors, aborted packets, runt packets-are counted statistics registers. Deletion Deletion removes from frame. Removal enabled disabled Receive Control Register. frame then passed Atlantic interface.
Transmitter Description
PP155 takes packets from Atlantic interface TXFIFO, passes them TXHDLC block processing.
Altera Corporation
Specifications
Packet Processor Mbps MegaCore Function (PP155) User Guide
TXHDLC
TXHDLC block frames data incoming transmit stream. following descriptions explain principle functions TXHLDC block. Processing TXHDLC block inserts into data stream stuffing normal packet. TXHDLC also inserts abort sequence needed into data stream aborted packets, inserts flags between frames. also stuffs data octets transparency. Stuffing performed bits time (byte oriented) high performance, gate count. When enabled, delivers octets Midbus interface. 16/32 calculated using CRC-16 CRC-32 generating polynomial. Scrambling transmit data stream scrambled using x43+1 polynomial. Scrambling enabled disabled Transmit Control Register. packet sent Midbus interface transmission.
Interfaces Protocols
Midbus
Midbus interface simple synchronous full-duplex data path bus. PP155 Midbus runs 19.44 over single byte lane each direction. receive direction (RX), data transferred from Midbus master slave (PP155). transmit direction (TX), data transferred from slave (PP155) master. each direction, Midbus carry bits clock cycle. includes midbus receive data (mrxdat[7:0]) midbus receive enable (mrxena) lines indicate valid data transfers direction, midbus transmit data (mtxdat[7:0]) midbus transmit enable (mtxena) lines indicate valid data requests direction. Since PP155 slave Midbus work with Midbus master.
Altera Corporation
Packet Processor Mbps MegaCore Function (PP155) User Guide
Specifications
AIRbus
AIRbus interface provides access internal registers using simple synchronous internal protocol. This consists separate read data (rdata[15:0]) write data (wdata[15:0]) buses, data transfer acknowledge (dtack) signal, select (sel) signal. address (addr[4:1]) read (read) signal indicate location type access within block. rdata buses dtack signals merged from multiple blocks using simple function. dtack signal sustained until block removed (four-way handshaking) meaning AIRbus cross clock domain boundaries. PP155 AIRbus slave with data width bits.
Specifications
Atlantic
Atlantic interface full-duplex synchronous protocol supporting both packets cells. PP155 Atlantic interface master using 8-bit wide data path, clocked 19.44 MHz, deliver packets slave. arxdav, atxdiv, atxsop signals provided, used.
More detailed information Midbus, AIRbus, Atlantic available from Altera site
Data Ordering
Data transferred parallel bits time) same order received internally between PP155 interfaces, ultimately transmitted/received first through external bit-serial mediums such SONET (optical fibre), keeping with telephony convention. This convention first followed doing (FCS/syndrome) calculations, which data communications first conventions. calculations, each octet nominally processed first. calculations actually done parallel though calculation simulates bit-serial first calculation. order that octets into calculation same transmission order. difference ordering practical effect long both ends follow same convention. important specify nominal order within bits Atlantic Midbus interfaces.
Altera Corporation
Specifications
Packet Processor Mbps MegaCore Function (PP155) User Guide
Transparency
Special flag characters delimit start frame. These special characters known Flag Sequence, which binary sequence 01111110 (hexadecimal 0x7e). There length field, loss carrier, other delimiter packet boundaries. Since data packet unrestricted, data patterns valid. Transparency achieved when framing protocol stuffs flag escape characters explained RFC1662: octet stuffing procedure used. Control Escape octet defined binary 01111101 (hexadecimal 0x7d), most significant first After computation, transmitter examines entire frame between Flag Sequences. Each Flag Sequence, Control Escape octet replaced octet sequence consisting Control Escape octet followed original octet exclusive-or'd with hexadecimal 0x20 0x7e encoded 0x7d, 0x5e. (Flag Sequence) 0x7d encoded 0x7d, 0x5d. (Control Escape) (.)" RFC1662 also defines ACCM convenience software hardware designed transferring text files. This allows other special characters stuffed directed user. PP155 does implement ACCM, thus TXHDLC does stuff anything other than flag control escape patterns. However, accordance with RFC1662, RXHDLC destuffs stuffed octets. reception Each Control Escape octet also removed, following octet exclusive-or'd with hexadecimal 0x20, unless Flag Sequence (which aborts frame)."
Pin-Outs
Port
Receive Interface Signals rxclk rxreset_n input input
following table describes pins used PP155.
Direction
Description
Clock Active reset
Midbus Receive Interface Signals mrxena mrxdat[7:0] input input Enable Data
Altera Corporation
Packet Processor Mbps MegaCore Function (PP155) User Guide
Specifications
Port
Direction
Description
Specifications
Atlantic Receive Interface Signals arxena arxdav arxdiv arxval arxdat[7:0] arxsop arxeop arxerr output input output output output output output output Enable Data available Data divider Enable Data Start packet packet Error indication
Transmit Interface Signals txclk txreset_n input input Clock Active reset
Midbus Transmit Interface Signals mtxena mtxdat[7:0] input output Enable Data
Atlantic Transmit Interface Signals atxena atxdav atxdiv atxval atxdat[7:0] atxsop atxeop atxerr AIRbus Interface Signals read addr[4:1] wdata[15:0] rdata[15:0] dtack input input input input output output output Select Read: High read cycles, writes Address Write data Read data: zeros asserted. Data transfer acknowledge Interrupt request output input input input input input input input Enable Data available Data divider Enable Data Start packet packet Error indication
Altera Corporation
Specifications
Packet Processor Mbps MegaCore Function (PP155) User Guide
Performance
Table shows required speed estimated gate count PP155 APEX 20KE device. Table Performance
1,251 Note:
numbers ESBs approximate Dec. 2000.
Note ESBs
fMAX (MHz)
19.44 required support 155.52 Mbps
Software Interface
Memory
addresses access 16-bit registers shown hexadecimal values. value byte address, thus used. addresses even. Address
'h00 'h02 'h04 'h06 'h08 'h0A 'h0C 'h10 'h12 'h14 'h16 'h18
Register
RX_CTRL RX_IS RX_IE RX_PM_GOOD RX_PM_FCS RX_PM_ABORT RX_PM_RUNT TX_CTRL TX_IS TX_IE TX_PM_GOOD TX_PM_ERR
Description
Receive Control Register Receive Interrupt Register Receive Interrupt Enable Register Receive Good Packet Count Receive Error Count Receive Abort Count Receive Runt Frame Count Transmit Control Register Transmit Interrupt Register Transmit Interrupt Enable Register Transmit Good Packet Count Transmit Error Packet Count
Altera Corporation
Packet Processor Mbps MegaCore Function (PP155) User Guide
Specifications
Registers
following list access codes used describe type register bits. Code
RW1C RW0S RTCW RTSW RWTC RWTS RWSC RWSS Read/Write Read-Only Read/Write Clear Read/Write Read Clear Read Read Clear/Write Read Set/Write Read/Write value Clear Read/Write value Read/Write Self-Clearing Read/Write Self-Setting Unused bits/Read Unused bits/Read
Specifications
Description
Altera Corporation
Specifications
Packet Processor Mbps MegaCore Function (PP155) User Guide
Register Description
following tables describe registers receiver section PP155. RX_CTRL Receive Control Register 'h00 Field
REALIGN
Bits
Access
RWSC
Function
Forces aligner alignment Writing this (note that always reads forces byte aligner alignment. This ignored align
Default
ALIGN
Byte alignment disabled. Byte alignment enabled. set, aligner monitors error rate determine bytes aligned mrxdat. data aligned, shifts data mrxdat attempt align data. cleared, bytes assumed aligned mrxdat.
CRCLEN
CRC-CCITT mode CRC-32 mode set, receiver computes syndromes received packets using CRC-32 polynomial, cleared, CRCCCITT 16-bit polynomial. syndrome always computed checked. Packets with syndromes (i.e. with errors) discarded, counted Receive Error Count register marked erroneous when sent Atlantic interface.
SCRAMEN
Enable descrambling transmit frame descrambling receive frame. This causes received data stream descrambled using x^43+1 scrambling polynomial. bits descrambled using most significant (higher-numbered) first. bits, including flags, body packet, scrambled. descrambling process selfsynchronizing. descrambler reset enable will therefore synchronize state with received data stream while enable cleared. should, therefore, desired value least bits data should received before turning enable bit.
Altera Corporation
Packet Processor Mbps MegaCore Function (PP155) User Guide DELFCS
Specifications
Store with received packet. Delete from received frame. cleared, packet delivered Atlantic interface with appended. Setting this causes receiver remove before sending packet Atlantic interface. Users this improve performance Atlantic interface simplify downstream processing packet. This function requires that crclen properly.
Specifications
ENABLE
Disable packet reception. Enable packet reception. Clearing this zero places internal state variables idle condition, clears status register, receive performance monitor counts (good, FCS, runt, abort). Setting enables functions.
RX_IS Receive Interrupt Register 'h02 Field
GOOD
Bits
Access
RW1C
Function
good packet received. This legal, correct packet received.
Default
UNALIGNED
RW1C
receiver unaligned. This when receive aligner aligned state. determine when aligner regained alignment, software should read clear this periodically until stays cleared. Clearing align control register prevents this from being set, does clear bit.
RW1C
error occurs. This packet with incorrect received.
ABORT
RW1C
receive packet aborted. This packet terminated with abort sequence received.
RUNT
RW1C
runt packet received. This illegally short packet received.
Altera Corporation
Specifications
Packet Processor Mbps MegaCore Function (PP155) User Guide
RX_IE Receive Interrupt Enable Register 'h04 Field
GOOD UNALIGNED ABORT RUNT
Bits
Access
Function
Enables receive good interrupt status. Enables receive unaligned interrupt status. Enables receive interrupt status. Enables receive abort interrupt status. Enables receive runt interrupt status.
Default
RX_PM_GOOD Receive Good Packet Count 'h06 Field
Bits
15:0
Access
RTCW
Function
Count correctly received packets. Each correctly received packet (good FCS, aborted, runt) causes this count increment one. counter saturates 0xFFFF: will wrap Reading this register clears count. 16-bit values written this register testing.
Default
RX_PM_FCS Receive Error Count 'h08 Field
Bits
15:0
Access
RTCW
Function
Count received packets with FCS. Packets that runts aborted which have syndromes increment this count. counter saturates 0xFFFF does wrap Reading this register clears count.
Default
RX_PM_ABORT Receive Abort Count 'h0A Field
Bits
15:0
Access
RTCW
Function
Count received packets terminated with ABORT.
Default
Altera Corporation
Packet Processor Mbps MegaCore Function (PP155) User Guide
Specifications
RX_PM_RUNT Receive Runt Frame Count 'h0C Field
Specifications
Bits
15:0
Access
RTCW Count runt frames.
Function
Default
Runt packets packets received with frames shorter than octets (depending setting crclen), including stuff octets flags. Individual runt packets increment count. counter saturates 0xFFFF does wrap Reading this register clears count. 32-bit values written this register testing.
Register Description
following tables describe registers transmitter section PP155.
TX_CTRL Transmit Control Register 'h10 Field
CRCLEN
Bits
Access
Function
CRC-32 bits); CRC-CCITT bits). set, transmit section computes FCSs transmit packets using CRC-32 polynomial; cleared, CRCCCITT 16-bit polynomial used. always generated appended.
Default
SCRAMEN
Enables scrambling transmit frame. This causes transmitted data stream scrambled using x^43+1 scrambling polynomial. bits scrambled using most significant (higher-numbered) first. bits, including flags, body packet, scrambled.
Altera Corporation
Specifications ENABLE
Packet Processor Mbps MegaCore Function (PP155) User Guide
Disable packet transmission. Enable packet transmission. Clearing this zero places internal state variables idle condition, clears status registers transmit performance monitor counts (good, error). Setting enables functions.
TX_IS Transmit Interrupt Register 'h12 Field
GOOD
Bits
Access
RW1C
Function
packet transmitted correctly. This transmission complete packet with errors.
Default
RW1C
packet aborted (atxerr asserted simultaneously with atxeop). This atxerr asserted. Software writes this clear
UNDERFLOW
RW1C
FIFO underflowed. This Atlantic interface does supply data when required (i.e atxval middle packet). atxval negated after sending complete packet before starting packet underflow reported. underflow aborts current packet discards remainder. Subsequent packets transmitted normally. Software writes this clear
TX_IE Transmit Interrupt Enable Register 'h14 Field
GOOD UNDERFLOW
Bits
Access
Function
Enables transmit good interrupt status. Enables transmit interrupt status. Enables transmit underflow interrupt status.
Default
Altera Corporation
Packet Processor Mbps MegaCore Function (PP155) User Guide
Specifications
TX_PM_GOOD Transmit Good Packet Count 'h16 Field
Specifications
Bits
15:0
Access
RTCW
Function
Count correctly transmitted packets. Each correctly transmitted packet underflow, aborted) causes this count increment one. counter saturates 0xFFFF; does wrap Reading this register clears count. 16-bit values written this register testing.
Default
TX_PM_ERR Transmit Error Packet Count 'h18 Field
Bits
15:0
Access
RTCW
Function
Count transmitted packets terminated with ABORT. Packets which runts which terminated abort sequence increment this count. counter saturates 0xFFFF; does wrap Reading this register clears count.
Default
Altera Corporation
Notes:
Altera Corporation
Getting Started
User Guide
This section describes obtain variant from Packet Processor MegaCore® Function (PP155). explains install PP155 your walks through process implementing variant design. test-drive PP155 using Altera OpenCorefeature-within Quartussoftware-to instantiate perform place-and-route, perform static timing analysis, simulate using third-party simulator, within your custom logic. Only when ready generate programming files, need obtain licenses through your local Altera sales representative.
Design Walkthrough
This design walkthrough involves following steps: Obtaining installing Packet Processor Mbps MegaCore Function. Generating custom PP155 your system using MegaWizard® Plug-In. Implementing rest your system using AHDL, VHDL, Verilog HDL. Compiling your design performing place-and-route. Licensing PP155 configure device.
Getting Started
instructions assume that:
using familiar with Quartus software. Quartus software version higher) installed default location. using OpenCore feature test-drive PP155, have licensed
Altera Corporation
Getting Started
Packet Processor Mbps MegaCore Function (PP155) User Guide
Obtaining Installing PP155
start using PP155, need obtain MegaCore package from your local Altera representative. package includes:
MegaWizard Plug-In Encrypted gate level netlist Place Route constraints (where necessary) Secure simulation model Sanity test bench Access problem reporting system Interface Functional Specifications (AIRbus, Midbus, Atlantic, etc.) Data Sheet User Guide
Installing MegaCore Files
MegaWizard Plug-In generate files install them your following instructions describe this process. Before MegaWizard Plug-In, your must have Java runtime environment version installed. This file downloaded from Java site http://www.java.sun.com.
Windows 95/98 Windows 4.0, follow instructions below: Click (Start menu). Type <path name>\<filename>.exe, where <path name> location downloaded PP155 <filename> filename PP155. Click MegaCore Installer dialog appears. Follow wizard instructions finish installation. After have finished installing files, must specify directory which installed them user library Quartus software. Search "User Libraries" Quartus Help instructions these libraries.
Generating Custom PP155
This section describes design flow using Altera PP155 Quartus development system. MegaWizard Plug-In Manager provided with PP155. MegaWizard Plug-In Manager-used within Quartus software-allows create modify design files meet needs application. then instantiate PP155 your design file.
Altera Corporation
Packet Processor Mbps MegaCore Function (PP155) User Guide
Getting Started
create custom PP155 using wizard, follow these steps: Start MegaWizard Plug-In choosing MegaWizard Plug-In Manager command (File menu) Quartus software. MegaWizard Plug-In Manager dialog displayed. Refer Quartus Help detailed instructions MegaWizard Plug-In Manager.
Specify that want create custom variant click Next. second page wizard, select PP155 from OTC/POS folder. Choose type output files, specify folder name files wizard creates, click Next. Select optional parameters choices that require. Only basic configuration PP155 available.
Getting Started
final screen lists design files that wizard creates. Click Finish.
Implementing System Compiling Performing Place Route
Once have created your custom PP155, ready implement files generated MegaWizard, Quartus software, other tools create your design. Quartus software compile place-and-route your design. Refer Quartus Help instructions performing compilation. After have verified that your design functionally correct, ready perform system verification.
Performing Synthesis Compilation Post-Routing Simulation
Quartus software works seamlessly with tools from vendors, including Cadence, Exemplar Logic, Mentor Graphics, Synopsys, Synplicity, Viewlogic. After have licensed PP155, generate EDIF, VHDL, Verilog HDL, Standard Delay Output Files from Quartus software them with your existing tools perform functional modeling post-route simulation your design.
Using Third-Party Tools
synthesize your design third-party tool perform postroute simulation, follow these steps:
Altera Corporation
Getting Started
Packet Processor Mbps MegaCore Function (PP155) User Guide
Create your custom design instantiating PP155. Synthesize design using your third-party tool. Your tool should treat PP155 instantiation black either setting attributes ignoring instantiation. After compilation, generate hierarchical netlist file your thirdparty tool. Open your netlist file Quartus software. pre-synthesized encrypted .e.vqm.v file from your working directory.
Using Quartus Software
Select Compile mode (Processing menu). Specify Compiler settings Compiler Settings dialog (Processing menu) Compiler Settings wizard. Specify user libraries project order which Compiler searches libraries. Specify input settings project. Choose Tool Settings (Project menu). Select Custom EDIF Design entry/synthesis tool list. Click Settings. Tool Input Settings dialog box, make sure that relevant tool name option selected Design Entry/Synthesis Tool list. Depending type output file want, specify Verilog output settings VHDL output settings General Settings dialog (Project menu). 1993 VHDL language option. pre-synthesized encrypted .e.vqm.v file from your working directory. Compile your design. Quartus Compiler synthesizes performs place-and-route your design, generates output programing files. Import your Quartus-generated output files (.edo, .vho, .vo, .sdo) into your third-party tool post-route, device-level, system-level simulation.
Altera Corporation
Packet Processor Mbps MegaCore Function (PP155) User Guide
Getting Started
Functional Simulation Using Visual Models
This section describes Visual model verification provides instructions using those models. Figure shows example Visual model arrangement. Figure General Arrangement
(RTL) Hook-Up Model: Black Verilog VHDL Wrapper Empty Declaration
User Design (RTL)
Utility (RTL)
Utility (RTL)
Utility (RTL)
Getting Started
level Visual model treated sub-block design main design unit.
Downloading Installing Visual Software Visual software facilitates Visual simulation models allowing waveforms viewed, using third-party simulation tools. view simulation model, must have Visual software installed your system. download software, instructions software, refer Altera site
Licensing Configuring Device
After have compiled analyzed your design, ready configure your targeted Altera semiconductor device. evaluating PP155 with OpenCore feature, must license function before generate programming files. obtain licenses contact your local Altera sales representative. current PP155 variants single license, with ordering code: PLSM-PP155.
Altera Corporation

Packet Processor Mbps MegaCore Function PP155 December 2000

Top Searches for this datasheet

Other recent searches