CP155 June 2001 User Guide Version 1.01 Innovation Drive Jos
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ACell Processor Mbps MegaCore Function
CP155
June 2001 User Guide Version 1.01
Innovation Drive Jose, 95134 (408) 544-7000 http://www.altera.com
A-UG-IPCP155-1.01
ACell Processor Mbps MegaCore Function (CP155) User Guide
Copyright 2001 Altera Corporation. Altera, Programmable Solutions Company, stylized Altera logo, specific device designations, other words logos that identified trademarks and/or service marks are, unless noted otherwise, trademarks service marks Altera Corporation U.S. other countries. other product service names property their respective holders. Altera products protected under numerous U.S. foreign patents pending applications, maskwork rights, copyrights. Altera warrants performance semiconductor products current specifications accordance with Altera's standard warranty, reserves right make changes products services time without notice. Altera assumes responsibility liability arising application information, product, service described herein except expressly agreed writing Altera Corporation. Altera customers advised obtain latest version device specifications before relying published information before placing orders products services. rights reserved
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About this User Guide
User Guide
This user guide provides comprehensive information about Altera® ACell Processor Mbps MegaCore® Function (CP155). Table shows user guide revision history.
Table Revision History
Revision
1.00 1.01
Date
Dec. 2000 June 2001 First release
Description
First revision. Added "Core Verification Summary" section. Revised "Getting Started" chapter.
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About this User Guide
ACell Processor Mbps MegaCore Function (CP155) User Guide
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ACell Processor Mbps MegaCore Function (CP155) User Guide
About this User Guide
Typographic Conventions
Table Conventions
Visual
Bold Type with Initial Capital Letters bold type
ACell Processor Mbps MegaCore Function (CP155) User Guide uses typographic conventions shown Table
Meaning
Command names, dialog titles, checkbox options, dialog options shown bold, initial capital letters. Example: Save dialog box. External timing parameters, directory names, project names, disk drive names, filenames, filename extensions, software utility names shown bold type. Examples: fMAX, \maxplus2 directory, drive, chiptrip.gdf file. Book titles shown bold italic type with initial capital letters. Example: 1999 Device Data Book. Document titles shown italic type with initial capital letters. Example: (High-Speed Board Design). Internal timing parameters variables shown italic type. Examples: tPIA, Variable names enclosed angle brackets shown italic type. Example: <file name>, <project name>.pof file. Keyboard keys menu names shown with initial capital letters. Examples: Delete key, Options menu. References sections within document titles Quartus MAX+PLUS Help topics shown quotation marks. Example: "Configuring FLEX FLEX 8000 Device with BitBlasterDownload Cable." Signal port names shown lowercase Courier type. Examples: data1, tdi, input. Active-low signals denoted suffix e.g., reset_n. Anything that must typed exactly appears shown Courier type. example: Also, sections actual file, such Report File, references parts files (e.g., AHDL keyword SUBDESIGN), well logic function names (e.g., TRI) shown Courier.
Bold italic type Italic Type with Initial Capital Letters Italic type
Initial Capital Letters "Subheading Title"
Courier type
c.,. Numbered steps used list items when sequence items important, such steps listed procedure.
Bullets used list items when sequence items important. checkmark indicates procedure that consists step only. hand points information that requires special attention. angled arrow indicates should press Enter key. feet direct more information particular topic.
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About this User Guide
ACell Processor Mbps MegaCore Function (CP155) User Guide
Abbreviations Acronyms
AHDL ACLP FIFO LSByte Mbps MSByte RXATC TXATC UTOPIA VHDL VHSIC
Altera Hardware Description Language Asynchronous Transfer Mode Cell Loss Priority Central processing unit Electronic Design Automation Embedded System Block First First Generic Flow Control Header Error Control Input/Output Intellectual Property Logic Element Least Significant Least Significant Byte Megabits second Most Significant Most Significant Byte Operations, Administration, Maintenance Personal computer Physical Layer Receive Receive ATransmission Convergence sub-block Transmission Convergence Transmit Transmit ATransmission Convergence sub-block User Defined Field Universal Test Operations Physical Interface AVirtual Channel Identifier VHSIC Hardware Description Language Very High Speed Integrated Circuit Virtual Path Identifier
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Contents
User Guide
About this User Guide
Find Information Contact Altera Typographic Conventions Abbreviations Acronyms
Specifications
General Description Features Receiver Features Transmitter Features Functional Description Receiver Description RXATC Cell Delineation Error Correction Payload Descrambling Extraction Filtering (FILT) Arbitration Cell Insertion/Extraction (CIE) Performance Monitoring (PM) Formatting TXATC Formatting Filtering (FILT) Arbitration Cell Insertion/Extraction (CIE) Idle Cell Generation Performance Monitoring (PM) Generation Insertion Payload Scrambling Interfaces Protocols Midbus Interface AIRbus Interface Atlantic Interface Access Signals
Altera Corporation
Contents
Performance Software Interface Memory Memory Registers Registers RXATC Register Description RXATC_CTRL Control Register 'h00 RXATC_STAT Status Register 'h02 RXATC_IS Interrupt Status Register 'h04 RXATC_IE Interrupt Enable Register 'h06 RXATC_OAM Filter Control Register 'h08 RXATC_IMEM Insertion Memory Access 'h0A RXATC_EMEM Extraction Memory Access 'h0C RXATC_PM_ERR Error Performance Monitoring 'h20. RXATC_PM_CELL Cell Performance Monitoring 'h22. RXATC_PM_DISC Discard Cell Performance Monitoring 'h24. RXATC_PM_CHEC Correctable Performance Monitoring 'h26 RXATC_PM_UHEC Uncorrectable Performance Monitoring 'h28. RXATC_PM_OAM Filter Performance Monitoring 'h2A RXATC_PM_FILT0 Filter Performance Monitoring 'h2C RXATC_PM_FILT1 Filter Performance Monitoring 'h2E. RXATC_PM_FILT2 Filter Performance Monitoring 'h30 RXATC_PM_FILT3 Filter Performance Monitoring 'h32 RXATC_FILT0_CTRL Filter Control Register 'h40. RXATC_FILT0_PAT0 Filter Pattern 'h42 RXATC_FILT0_PAT1 Filter Pattern 'h44 RXATC_FILT0_CHK0 Filter Check 'h46 RXATC_FILT0_CHK1 Filter Check 'h48 RXATC_FILT1_CTRL Filter Control Register 'h4A RXATC_FILT1_PAT0 Filter Pattern 'h4C RXATC_FILT1_PAT1 Filter Pattern 'h4E. RXATC_FILT1_CHK0 Filter Check 'h50 RXATC_FILT1_CHK1 Filter Check 'h52 RXATC_FILT2_CTRL Filter Control Register 'h54. RXATC_FILT2_PAT0 Filter Pattern 'h56 RXATC_FILT2_PAT1 Filter Pattern 'h58 RXATC_FILT2_CHK0 Filter Check 'h5A. RXATC_FILT2_CHK1 Filter Check 'h5C RXATC_FILT3_CTRL Filter Control Register 'h5E RXATC_FILT3_PAT0 Filter Pattern 'h60 RXATC_FILT3_PAT1 Filter Pattern 'h62 RXATC_FILT3_CHK0 Filter Check 'h64 RXATC_FILT3_CHK1 Filter Check 'h66 TXATC Register Description TXATC_CTRL Control Register 'h80.
viii
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Contents
TXATC_STAT Status Register 'h82. TXATC_IS Interrupt Status Register 'h84 TXATC_IE Interrupt Enable Register 'h86. TXATC_OAM Filter Control Register 'h88. TXATC_IDLE Idle Cell Control Register 'h8A. TXATC_IMEM Insertion Memory Access 'h8C TXATC_EMEM Extraction Memory Access 'h8E. TXATC_PM_ERR Error Performance Monitoring 'hA0. TXATC_PM_CELL Cell Performance Monitoring 'hA2. TXATC_PM_DISC Discard Cell Performance Monitoring 'hA4. TXATC_PM_HERR Error Performance Monitoring 'hA6 TXATC_PM_AERR Atlantic Error Performance Monitoring 'hA8. TXATC_PM_OAM Filter Performance Monitoring 'hAA TXATC_PM_FILT0 Filter Performance Monitoring 'hAC TXATC_PM_FILT1 Filter Performance Monitoring 'hAE. TXATC_PM_FILT2 Filter Performance Monitoring 'hB0. TXATC_PM_FILT3 Filter Performance Monitoring 'hB2 TXATC_FILT0_CTRL Filter Control Register 'hC0 TXATC_FILT0_PAT0 Filter Pattern 'hC2. TXATC_FILT0_PAT1 Filter Pattern 'hC4. TXATC_FILT0_CHK0 Filter Check 'hC6 TXATC_FILT0_CHK1 Filter Check 'hC8 TXATC_FILT1_CTRL Filter Control Register 'hCA TXATC_FILT1_PAT0 Filter Pattern 'hCC. TXATC_FILT1_PAT1 Filter Pattern 'hCE TXATC_FILT1_CHK0 Filter Check 'hD0 TXATC_FILT1_CHK1 Filter Check 'hD2 TXATC_FILT2_CTRL Filter Control Register 'hD4. TXATC_FILT2_PAT0 Filter Pattern 'hD6 TXATC_FILT2_PAT1 Filter Pattern 'hD8 TXATC_FILT2_CHK0 Filter Check 'hDA TXATC_FILT2_CHK1 Filter Check 'hDC TXATC_FILT3_CTRL Filter Control Register 'hDE TXATC_FILT3_PAT0 Filter Pattern 'hE0 TXATC_FILT3_PAT1 Filter Pattern 'hE2 TXATC_FILT3_CHK0 Filter Check 'hE4. TXATC_FILT3_CHK1 Filter Check 'hE6. Core Verification Summary Simulation Environment Compatibility Testing Environment
Getting Started
Design Walkthrough Obtaining Installing CP155 Downloading MegaCore Function Installing MegaCore Files Generating custom CP155
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Contents
Implementing System Simulating Your Design Using Verilog Demo Testbench Using Visual Software Synthesis, Compilation Place Route Using Third-Party Tools Synthesis Using Quartus development tool compilation place-and-route Licensing Configuration Performing Post-Routing Simulation
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Specifications
User Guide
General Description
ACell Processor Mbps MegaCore® Function (CP155) uses MegaWizard® Plug-In-within Quartus® software-to generate variants AHDL, VHDL, Verilog HDL, which instantiate into your design. Table shows optional features available generate variants CP155.
Specifications
Table Optional Features
Options
Generic cell filters Cell insertion extraction processor interface Performance monitoring of-received transmitted- corrected, corrupted, filtered cells Notes:
cell filter included base core design filter cells. Requires four generic cell filters. allows performance monitor counts: received cells, transmitted cells, discarded cells, corrected HECs, uncorrected HECs, error cells, Atlantic error cells, cells, generic filtered cells. allows only count errored cells.
Parameters
FILT
Choices
0,1,4
CP155 capable performing operations required support sublayer APHY device, compliance with applicable standards, including:
International Telecommunications Union, Recommendation, ISDN User Network Interfaces, ITU-T I.432, March 1993 AForum, Utopia, ATM-PHY Interface Specification, Level Version 1.0, af-phy039.000, June 1995 Altera Corporation, AtlanticInterface Functional Specification. purpose this user guide, "receive" indicates data flowing into CP155 from Midbus interface transmission through Atlantic interface; "transmit" indicates data received from Atlantic interface transmission through Midbus interface. Thus Atlantic interface source transmit packets, sink received packets.
Altera Corporation
Specifications
ACell Processor Mbps MegaCore Function (CP155) User Guide
Features
This user guide aims describe full-feature CP155.
Receiver Features
Acell delineation Byte-boundary detection Loss cell delineation indication Header single-bit error correction multi-bit error detection External Acell extraction Payload descrambling Acell formatting bits) Discarding cells, selectable cell filtering Cell insertion extraction through AIRbus interface Performance monitoring corrected, corrupted, filtered cells
Transmitter Features
Internal generation insertion Cell rate decoupling with programmable idle cell header payload External Acell insertion Payload scrambling Acell formatting bits) Discarding cells, selectable cell filtering Cell insertion extraction through AIRbus interface Performance monitoring corrected, corrupted, filtered cells
Functional Description
CP155 operates full-duplex mode, comprises blocks: RXATC block, TXATC block. Figure shows block diagram CP155, including three interfaces that support "Interfaces Protocols" page more information.
Altera Corporation
ACell Processor Mbps MegaCore Function (CP155) User Guide
GettiSpecifications
Figure Block Diagram
CP155 rxclk rxreset_n RXATC mrxdat[7:0] mrxena rxgfcclk rxgfcfp rxgfc rxcp arxerr arxena arxdav arxval arxdat[15:0] arxsop arxeop
Specifications
Midbus
Extraction Interface
Atlantic
atxena TXATC atxdav atxval atxdat[15:0] atxsop atxeop atxerr
txclk
txreset_n
Midbus
Insertion Interface
mtxdat[7:0] mtxena txgfcclk txgfcfp txgfc txcp
read
addr[7:1]
wdata[15:0]
rdata[15:0]
dtack
AIRbus
Receiver Description
RXATC
RXATC block performs Acell delineation, payload descrambling, error detection, cell filtering, cell insertion/extraction, cell formatting. RXATC designed interface cell-based FIFO buffer, using Atlantic interface.
Cell Delineation
Cell delineation detects cell boundaries received data stream searching valid HECs. incoming data stream either bit- byte-aligned. incoming data stream bit-aligned, user enable software feature byte-align data. cells must sent contiguously, with same number octets. Acell octets length, therefore cell boundary should exist every 53rd octet.
Altera Corporation
Specifications
ACell Processor Mbps MegaCore Function (CP155) User Guide
Error Correction
Received cells that contain errors forwarded filtering circuit. incorrect detected, syndrome produced determine whether single- multi-bit error occurred. user choose (software programmable) whether discard, forward cell, depending what selected HECPASS bit. single-bit error corrected (software programmable). multi-bit error, recalculated from header information (software programmable).
Payload Descrambling
self-synchronous descrambler used optionally descramble (software programmable) payload data Acell.
Extraction
extraction allows field-a four value that carries information about local flow control within header Acell- extracted. Extraction achieved using serial input port controlled enable register bits. When enabled, value extracted during each cell processing period. modification made field since this only observation feature.
Filtering (FILT)
CP155 contains base filter that discards specified cells. CP155 also includes filtering option which allows four generic filters added. filters independent each other, because they perform their function parallel. filters selectively mask header bits comparison, find matching un-matching bits. sense bit-used select cells that match match pattern-is also programmable software. filters mark cell meets their filtering requirements. Then, arbitration process take appropriate action.
Arbitration
Once cell been identified from filtering stage, cell arbitration determines action performed that cell. There groups possible actions: first allows cell discarded, forwarded Atlantic interface; second provides ability copy, copy cell cell memory accessible AIRbus interface.
Altera Corporation
ACell Processor Mbps MegaCore Function (CP155) User Guide
GettiSpecifications
chosen action forward cell, filter circuits also used simply count traffic matching pattern, without discarding This feature allows user audit cell traffic activity without interrupting cell flow. Since pattern arbitrary, filter used count cells specific VPI, cells specific VCI, even cells with set. filter circuit also ability copying marked cells memory, then examining payload through AIRbus interface. counting copying done without affecting user traffic way. Cells only counted when cell delineation been achieved. Statistics collected cells that forwarded Atlantic, cells that have been internally discarded. discarding cell creates opening another cell inserted into data stream. Arbitration identifies this opening inserts available cell from cell insertion memory. Idle/unassigned cells added transmit data stream purpose cell rate decoupling. perform proper cell rate decoupling, filter, generic filters, should programmed discard incoming idle/unassigned cells, especially before cells forwarded Atlantic interface.
Specifications
Cell Insertion/Extraction (CIE)
four-cell FIFO buffer used both insertion extraction data path. Processor accesses used write insertion FIFO buffer read from extraction FIFO buffer. cell arbitrator controls insertion extraction cells from data stream. External devices only insert extract octet cell data plus associative control information access through AIRbus interface. RXATC data path simultaneous insertion extraction since separate four-cell FIFO buffers used. When cell identified extraction, arbitrator sends entire cell extraction memory raises interrupt flag event. interrupt also indicate that least cell available cell memory, interrupt only cleared when cells remain FIFO buffer.
Altera Corporation
Specifications
ACell Processor Mbps MegaCore Function (CP155) User Guide
insert cell into data stream, external device must place entire cell into memory. interrupt indicates whether there room available, only cleared when entire FIFO buffer filled. arbitrator waits cell discarded before places cell into data stream. When cell discarded, creates opportunity-a period time- when entire insertion cell inserted into data stream without interrupting main data stream, without causing valid cells discarded. data stream priority over cell insertion. This method used insert cells.
Performance Monitoring (PM)
CP155 also includes performance monitoring option which allows certain statistics collected:
Received cells Discarded cells Correctable cells Uncorrectable cells filtered cells Generic filtered cells
Formatting
RXATC connects 16-bit data path Atlantic interface. Formatting converts 53-octet cell 8-bit data path 54-octet cell 16-bit data path. UDF1-the fifth octet formatted octet cell-represents HEC, UDF2-the sixth octet-represents error status. pattern represents status error free sequence, represent uncorrectable sequence, alternating represent correctable sequence.
TXATC
TXATC performs cell formatting, cell filtering, cell insertion/extraction, regeneration insertion, payload scrambling. TXATC designed interface cell-based FIFO buffer, using Atlantic interface.
Formatting
TXATC connects 16-bit data path Atlantic interface. Formatting converts 54-octet cell 16-bit data path 53-octet cell 8-bit data path. UDF2 stripped discarded from cell.
Altera Corporation
ACell Processor Mbps MegaCore Function (CP155) User Guide
GettiSpecifications
Filtering (FILT)
CP155 contains base filter that discards specified cells. CP155 also includes filtering option which allows four generic filters added. filters independent each other, because they perform their function parallel. filters selectively mask header bits comparison, find matching un-matching bits. sense bit-used select cells that match match pattern-is also programmable software. filters mark cell meets their filtering requirements. Then, arbitration process take appropriate action.
Specifications
Arbitration
Once cell been identified from filtering stage, cell arbitration determines action performed that cell. There groups possible actions: first allows cell discarded, forwarded Atlantic interface; second provides ability copy, copy cell cell memory accessible AIRbus interface. chosen action forward cell, filter circuits also used simply count traffic matching pattern, without discarding This feature allows user audit cell traffic activity without interrupting cell flow. Since pattern arbitrary, filter used count cells specific VPI, cells specific VCI, even cells with set. filter circuit also ability copying marked cells memory, then examining payload through AIRbus interface. counting copying done without affecting user traffic way.
Cell Insertion/Extraction (CIE)
four-cell FIFO buffer used both insertion extraction data path. Processor accesses used write insertion FIFO buffer read from extraction FIFO buffer. cell arbitrator controls insertion extraction cells from data stream. External devices only insert extract octet cell data plus associative control information access through AIRbus interface. TXATC data path simultaneous insertion extraction since separate four-cell FIFO buffers used. When cell identified extraction, arbitrator sends entire cell extraction memory raises interrupt flag event. interrupt also indicate that least cell available cell memory, interrupt only cleared when cells remain FIFO buffer.
Altera Corporation
Specifications
ACell Processor Mbps MegaCore Function (CP155) User Guide
insert cell into data stream, external device must place entire cell memory. interrupt indicates whether there room available only cleared when entire FIFO buffer filled. arbitrator waits cell discarded, Atlantic interface indicate that cell available, before places cell into data stream. This method used insert cells.
Idle Cell Generation
valid cells available, from either Atlantic interface insertion memory, idle cell with programmable header payload inserted adapt cell rate cells being pulled from Midbus interface.
Performance Monitoring (PM)
CP155 also includes performance monitoring option which allows certain statistics collected:
Transmitted cells Discarded cells errors Atlantic errored cells filtered cells Generic filtered cells
Generation
generated inserted into transmitted Acell. other options (software programmable) available user: forwarding received HEC, inverting transmitted debugging purposes.
Insertion
insertion allows value inserted into field header Acell. Insertion made using serial input port controlled enable register bits. enable bits must existing value modified. When enabled, value inserted during each cell processing period. next transmit cell idle/unassigned cell enable register bits set, value Idle Cell Header register overwritten.
Payload Scrambling
self-synchronous scrambler used optionally scramble (software programmable) payload data Acell.
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ACell Processor Mbps MegaCore Function (CP155) User Guide
GettiSpecifications
Interfaces Protocols
Midbus Interface
Midbus interface simple synchronous full-duplex data path bus. CP155 Midbus runs 19.44 over single byte lane each direction. direction, data transferred from Midbus master slave (CP155). direction, data transferred from slave (CP155) master. each direction, Midbus carry eight bits clock cycle. includes midbus receive data (mrxdat[7:0]) midbus receive enable (mrxena) lines indicate valid data transfers direction, midbus transmit data (mtxdat[7:0]) midbus transmit enable (mtxena) lines indicate valid data requests direction. Since CP155 slave Midbus work with Midbus master.
Specifications
AIRbus Interface
AIRbus interface provides access internal registers using simple synchronous internal processor protocol. This consists separate read data (rdata[15:0]) write data (wdata[15:0]) buses, data transfer acknowledge (dtack) signal, select (sel) signal. address (addr[7:1]) read (read) signal indicate location type access within block. rdata buses dtack signals merged from multiple blocks using simple function. dtack signal sustained until block removed (four-way handshaking) meaning AIRbus cross clock domain boundaries. CP155 AIRbus slave with data width bits.
Atlantic Interface
Atlantic interface full-duplex synchronous protocol supporting both packets cells. CP155 Atlantic interface master using 16-bit wide data path deliver cells slave.
More detailed information Midbus, AIRbus, Atlantic interfaces available from Altera site http://www.altera.com.
Altera Corporation
Specifications
ACell Processor Mbps MegaCore Function (CP155) User Guide
Access
access provides ability insert extract field header Acell. field represented first four bits first header byte carrying information about local flow control. Access made using serial input port. separate enable register exists directions. enable corresponding set, existing value replaced with value serial interface. When enabled, value inserted extracted during each cell processing period. next transmit cell idle/unassigned cell enable register set, value Idle Cell Header register overwritten. signal called rxgfcfp/txgfcfp used align serial data relating GFC[3]. signal called rxgfcclk/txgfcclk synthesized clock created from rxclk/txclk divided Figure shows timing diagram extraction. rxgfcclk, rxgfcfp rxgfc signals outputs. rxgfcfp indicates value rxgfc line GFC[3] contiguously followed GFC[2], GFC[1] GFC[0] synchronous rxgfcclk. data transmitted falling edge clock data should sampled rising edge rxgfcclk external circuitry.
Figure Receive Extraction
rxgfcclk rxgfcfp rxgfc
GFC[3] GFC[2] GFC[1] GFC[0]
Figure shows timing diagram insertion. txgfcclk txgfcmsb signals outputs txgfc signal input. txgfcmsb indicates next value required txgfc line GFC[3] contiguously followed GFC[2], GFC[1] GFC[0] synchronous txgfcclk. data transmitted falling edge clock from external circuitry data should sampled rising edge txgfcclk internal circuitry.
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ACell Processor Mbps MegaCore Function (CP155) User Guide
GettiSpecifications
Figure Transmit Insertion
Specifications
txgfcclk txgfcfp txgfc
GFC[3] GFC[2] GFC[1] GFC[0]
Signals
following table describes pins used CP155.
Table Signals (Part
Port Direction Description
Receive Interface Signals
rxclk rxreset_n rxcp Input Input Output Output Clock Active reset Cell pulse: indicates cell been received. Loss cell delineation
Receive Interface Signals
rxgfcclk rxgfcfp rxgfc Output Output Output Serial generic flow control clock Serial generic flow control frame pulse Serial generic flow control data
Midbus Receive Interface Signals
mrxena mrxdat[7:0] Input Input Enable Data
Atlantic Receive Interface Signals
arxena arxdav arxval arxdat[15:0] arxsop arxeop arxerr Output Input Output Output Output Output Output Enable Data available Data valid Data Start packet packet Error indication
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Specifications
ACell Processor Mbps MegaCore Function (CP155) User Guide
Table Signals (Part
Port Direction Description
Transmit Interface Signals
txclk txreset_n txcp Input Input Output Clock Active reset Cell pulse: indicates cell been transmitted.
Transmit Interface Signals
txgfcclk txgfcfp txgfc Output Output Output Serial generic flow control clock Serial generic flow control frame pulse Serial generic flow control data
Midbus Transmit Interface Signals
mtxena mtxdat[7:0] Input Output Enable Data
Atlantic Transmit Interface Signals
atxena atxdav atxval atxdat[15:0] atxsop atxeop atxerr Output Input Input Input Input Input Input Enable Data available Data valid Data Start packet packet Error indication
AIRbus Interface Signals
read addr[7:0] wdata[15:0] rdata[15:0] dtack Input Input Input Input Output Output Output Select Read: high read cycles, write. Address Write data Write data: zeros asserted. Data transfer acknowledge Interrupt request
Performance
Table shows required speed estimated gate count CP155 APEX 20KE device.
Table Performance
1,925 4,746
Note
ESBs
fMAX (MHz)
19.44 required support 155.52 Mbps
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ACell Processor Mbps MegaCore Function (CP155) User Guide Note from Table
GettiSpecifications
numbers ESBs approximate June 2001. They reflect range from basic full feature variant.
Specifications
Software Interface
Memory
addresses access 16-bit registers shown hexadecimal values. value byte address, thus used. addresses even.
Memory (Part
Byte Address
'h00 'h02 'h04 'h06 'h08 'h0A 'h0C 'h20 'h22 'h24 'h26 'h28 'h2A 'h2C 'h2E 'h30 'h32 'h40 'h42 'h44 'h46 'h48 'h4A 'h4C 'h4E 'h50 'h52 'h54 'h56
Register
RXATC_CTRL RXATC_STAT RXATC_IS RXATC_IE RXATC_OAM RXATC_IMEM RXATC_EMEM RXATC_PM_ERR RXATC_PM_CELL RXATC_PM_DISC RXATC_PM_CHEC RXATC_PM_UHEC RXATC_PM_OAM RXATC_PM_FILT0 RXATC_PM_FILT1 RXATC_PM_FILT2 RXATC_PM_FILT3 Control Register Status Register
Description
Interrupt Status Register Interrupt Enable Register Filter Control Register Insertion Memory Access Extraction Memory Access Error Performance Monitoring Cell Performance Monitoring Discard Cell Performance Monitoring Correctable Performance Monitoring Uncorrectable Performance Monitoring Filter Performance Monitoring Filter Performance Monitoring Filter Performance Monitoring Filter Performance Monitoring Filter Performance Monitoring
RXATC_FILT0_CTRL Filter Control Register RXATC_FILT0_PAT0 Filter Pattern RXATC_FILT0_PAT1 Filter Pattern RXATC_FILT0_CHK0 Filter Check RXATC_FILT0_CHK1 Filter Check RXATC_FILT1_CTRL Filter Control Register RXATC_FILT1_PAT0 Filter Pattern RXATC_FILT1_PAT1 Filter Pattern RXATC_FILT1_CHK0 Filter Check RXATC_FILT1_CHK1 Filter Check RXATC_FILT2_CTRL Filter Control Register RXATC_FILT2_PAT0 Filter Pattern
Altera Corporation
Specifications
ACell Processor Mbps MegaCore Function (CP155) User Guide
Memory (Part
Byte Address
'h58 'h5A 'h5C 'h5E 'h60 'h62 'h64 'h66 'h80 'h82 'h84 'h86 'h88 'h8A 'h8C 'h8E 'hA0 'hA2 'hA4 'hA6 'hA8 'hAA 'hAC 'hAE 'hB0 'hB2 'hC0 'hC2 'hC4 'hC6 'hC8 'hCA 'hCC 'hCE 'hD0 'hD2
Register
RXATC_FILT2_PAT1 Filter Pattern RXATC_FILT2_CHK0 Filter Check RXATC_FILT2_CHK1 Filter Check
Description
RXATC_FILT3_CTRL Filter Control Register RXATC_FILT3_PAT0 Filter Pattern RXATC_FILT3_PAT1 Filter Pattern RXATC_FILT3_CHK0 Filter Check RXATC_FILT3_CHK1 Filter Check TXATC_CTRL TXATC_STAT TXATC_IS TXATC_IE TXATC_OAM TXATC_IDLE TXATC_IMEM TXATC_EMEM TXATC_PM_ERR TXATC_PM_CELL TXATC_PM_DISC TXATC_PM_HERR TXATC_PM_AERR TXATC_PM_OAM TXATC_PM_FILT0 TXATC_PM_FILT1 TXATC_PM_FILT2 TXATC_PM_FILT3 TXATC_FILT0_PAT0 TXATC_FILT0_PAT1 Control Register Status Register Interrupt Status Register Interrupt Enable Register Filter Control Register Idle Cell Control Register Insertion Memory Access Extraction Memory Access Error Performance Monitoring Cell Performance Monitoring Discard Cell Performance Monitoring Error Performance Monitoring Atlantic Error Performance Monitoring Filter Performance Monitoring Filter Performance Monitoring Filter Performance Monitoring Filter Performance Monitoring Filter Performance Monitoring Filter Pattern Filter Pattern
TXATC_FILT0_CTRL Filter Control Register
TXATC_FILT0_CHK0 Filter Check TXATC_FILT0_CHK1 Filter Check TXATC_FILT1_CTRL Filter Control Register TXATC_FILT1_PAT0 TXATC_FILT1_PAT1 Filter Pattern Filter Pattern
TXATC_FILT1_CHK0 Filter Check TXATC_FILT1_CHK1 Filter Check
Altera Corporation
ACell Processor Mbps MegaCore Function (CP155) User Guide
GettiSpecifications
Memory (Part
Byte Address
'hD4 'hD6 'hD8 'hDA 'hDC 'hDE 'hE0 'hE2 'hE4 'hE6
Specifications
Description
Register
TXATC_FILT2_CTRL Filter Control Register TXATC_FILT2_PAT0 TXATC_FILT2_PAT1 Filter Pattern Filter Pattern
TXATC_FILT2_CHK0 Filter Check TXATC_FILT2_CHK1 Filter Check TXATC_FILT3_CTRL Filter Control Register TXATC_FILT3_PAT0 TXATC_FILT3_PAT1 Filter Pattern Filter Pattern
TXATC_FILT3_CHK0 Filter Check TXATC_FILT3_CHK1 Filter Check
Registers
following table lists access codes used describe type register bits.
Registers
Code
RW1C RW0S RTCW RTSW RWTC RWTS RWSC RWSS Read/Write Read-Only Read/Write Clear Read/Write Read Clear Read Read Clear/Write Read Set/Write Read/Write value Clear Read/Write value Read/Write Self-Clearing Read/Write Self-Setting Unused bits/Read Unused bits/Read
Description
Altera Corporation
Specifications
ACell Processor Mbps MegaCore Function (CP155) User Guide
RXATC Register Description
following tables describe registers receiver section CP155.
RXATC_CTRL Control Register 'h00 (Part
Field
BITALIGN
Bits
Access
Function
Default
Alignment When this '1', enables alignment cell delineation. cell byte boundary exist anywhere received data. alignment shifts searches data until cell alignment found. data byte-aligned, this should because lengthen duration cell delineation. Extraction These bits determine whether send each individual received serial output interface. When corresponding '1', from Aheader placed serial interface, otherwise forced low. extraction provides ability extract value from field header Acell. field represented first four bits first header byte carrying information about local flow control. Extraction made using serial input port controlled enable register bit. When enabled, value extracted during each cell-processing period. modification made field since this only observation feature. Threshold thresholds indicate number valid cells required detection state return back correction state. example, HECTHRD 'b10, RXATC detection state, then after detecting cells, RXATC goes back correction state. 'b00 Acell with valid (default) 'b01 Acells with valid 'b10 Acells with valid 'b11 Acells with valid
GFCEXT
13:10
HECTHRD
Altera Corporation
ACell Processor Mbps MegaCore Function (CP155) User Guide
GettiSpecifications
RXATC_CTRL Control Register 'h00 (Part
Field
HECSTAT
Specifications
Function Default
Bits
Access
Status When this '1', status information written UDF2. Status information: 'h00 error free sequence 'hFF uncorrectable sequence 'hAA correctable sequence Insert When this '1', inserts octet into UDF1.
HECINS
HECADD
Addition When this '1', performs modula addition ('b0101_0101) header before comparison. Pass Controls cell discard when error detected. this '0', cells with uncorrectable headers discarded. Cells only passed SYNC delineation state, cells with uncorrectable headers normally discarded. this '1', uncorrectable headers passed SYNC state, correction state machine remains correction state. Correction Controls error correction header. When this '1', single header errors corrected. When '0', single errors always treated uncorrectable errors. Regenerate When this '1', regenerated cells with uncorrectable headers. generating polynomial with optional modula addition based HECADD bit. Descrambling When this '1', payload self-synchronous descrambling performed, using x*43 polynomial.
HECPASS
HECCOR
HECRGN
DESCRAM
Enable When this '0', cell processor disabled. cell processor remains static state continues ignore enables until '1'. must before cells received.
Altera Corporation
Specifications
ACell Processor Mbps MegaCore Function (CP155) User Guide
RXATC_STAT Status Register 'h02
Field
IMEMDAV
Bits
Access
Function
Insertion Memory Data Available This indicates current Insertion Memory Data Available status. when insertion memory room entire cell written memory.
Default
EMEMDAV
Extraction Memory Data Available This indicates current Extraction Memory Data Available status. when extraction memory entire cell read from memory. Loss Cell Delineation This indicates current Loss Cell Delineation status. when cell delineation state machine transitions from SYNC state back HUNT state. This transition occurs after ALPHA (=7) consecutive incorrect HECs have been received, remains until SYNC achieved. Cell Delineation These bits indicate current Cell Delineation status. When 'b11, they indicate that cell delineation HUNT state. beginning cell delineation, state machine HUNT state looking correct HEC. correct found, state machine transitions PRESYNC state, represented 'b01. incorrect detected before DELTA (=6) consecutive correct HECs received, state machine goes back HUNT state. DELTA (=6) correct cells detected consecutively, proceeds SYNC state represented value 'b00.
RXATC_IS Interrupt Status Register 'h04 (Part
Field
IMEMOFLW
Bits
Access
RW1C
Function
Default
Insertion Memory Overflow Interrupt When this '1', indicates that insertion memory overflowed. Thus attempt write cell extraction memory results cell being discarded. Extraction Memory Overflow Interrupt When this '1', indicates that extraction memory overflowed. Thus attempt write cell extraction memory results cell being discarded.
EMEMOFLW
RW1C
Altera Corporation
ACell Processor Mbps MegaCore Function (CP155) User Guide
GettiSpecifications
RXATC_IS Interrupt Status Register 'h04 (Part
Field
IMEMDAV
Specifications
Function Default
Bits
Access
RW1C
Insertion Memory Data Available Interrupt When this '1', indicates that insertion memory room available entire cell written memory. Extraction Memory Data Available Interrupt When this '1', indicates that extraction memory entire cell available read from memory. Cell Insertion Interrupt When this '1', indicates that cell been drawn from memory, been inserted into data path.
EMEMDAV
RW1C
IMEMCELL
RW1C
EMEMCELL
RW1C
Cell Extraction Interrupt When this '1', indicates that cell been extracted from data path, placed into extraction memory. Uncorrectable Error Interrupt When this '1', indicates that uncorrectable error been detected. Uncorrectable errors occur multi-bit errors. also single errors, only when correction state machine been disabled. Correctable Error Interrupt When this '1', indicates that correctable error been detected. Correctable errors occur single errors only when correction state machine been detect correct. Loss Cell Delineation Interrupt This indicates Loss Cell Delineation. when cell delineation state machine transitions from SYNC state back HUNT state. This transition occurs after ALPHA (=7) consecutive incorrect HECs have been received.
UHEC
RW1C
CHEC
RW1C
RW1C
Altera Corporation
Specifications
ACell Processor Mbps MegaCore Function (CP155) User Guide
RXATC_IS Interrupt Status Register 'h04 (Part
Field
Bits
Access
RW1C
Function
Default
Cell Delineation Interrupt This indicates Cell Delineation. '1', this indicates that cell delineation HUNT PRESYNC state. beginning cell delineation, state machine HUNT state looking correct HEC. found, transitions PRESYNC state remains there. incorrect detected before DELTA (=6) consecutive correct HECs received, state machine goes back HUNT state. DELTA (=6) correct cells detected consecutively, proceeds SYNC state. This interrupt only cleared when state machine SYNC state.
RXATC_IE Interrupt Enable Register 'h06 (Part
Field
IMEMOFLW
Bits
Access
Function
Default
Insertion Memory Overflow Interrupt Enable This enables Insertion Memory Overflow interrupt asserted line. Extraction Memory Overflow Interrupt Enable This enables Extraction Memory Overflow interrupt asserted line. Insertion Memory Data Available Interrupt Enable This enables Insertion Memory Data Available interrupt asserted line. Extraction Memory Data Available Interrupt Enable This enables Extraction Memory Data Available interrupt asserted line.
EMEMOFLW
IMEMDAV
EMEMDAV
IMEMCELL
Cell Insertion Interrupt Enable This enables Cell Insertion interrupt asserted line. Cell Extraction Interrupt Enable This enables Cell Extraction interrupt asserted line. Uncorrectable Error Interrupt Enable This enables Uncorrectable Error interrupt asserted line. Correctable Error Interrupt Enable This enables Correctable Error interrupt asserted line.
EMEMCELL
UHEC
CHEC
Altera Corporation
ACell Processor Mbps MegaCore Function (CP155) User Guide
GettiSpecifications
RXATC_IE Interrupt Enable Register 'h06 (Part
Field
Specifications
Function Default
Bits
Access
Loss Cell Delineation Interrupt Enable This enables Loss Cell Delineation interrupt asserted line. Cell Delineation Interrupt Enable This enables Cell Delineation interrupt asserted line.
RXATC_OAM Filter Control Register 'h08 (Part
Field
MGFC
Bits
15:12
Access
Function
Default
Match 4'b1111 These four bits used include specified bits filter pattern. When '0', corresponding masked from pattern represents don't care that matches both logical logical zero. Match 3'b111 These three bits used include specified bits filter pattern. When '0', corresponding masked from pattern represents don't care that matches both logical logical zero. Match 1'b1 This used include specified filter pattern. When '0', masked from pattern represents don't care that matches both logical logical zero. These four bits identify Generic Flow Control (GFC) bits first octet filter pattern. Together, GFC, form base filter pattern. header value matching this pattern discarded. filter statically '0'. match used exclude certain bits from this filter pattern. Payload Type These three bits used determine payload type (PT) filtering cells. bits precede found fourth octet. Together, GFC, form base filter pattern. header value matching this pattern discarded. filter statically '0'. match used exclude from filter pattern.
11:9
MCLP
Altera Corporation
Specifications
ACell Processor Mbps MegaCore Function (CP155) User Guide
RXATC_OAM Filter Control Register 'h08 (Part
Field
Bits
Access
Function
Default
Cell Loss Priority 1'b1 When this '1', asserts cell loss priority (CLP) cell '1'; otherwise '0'. last header found fourth octet. Together, GFC, bits form base filter pattern. header value matching this pattern discarded. filter statically '0'. match used exclude certain bits from filter pattern.
RXATC_IMEM Insertion Memory Access 'h0A
Field
Bits
Access
Function
Default
Insertion Memory When this '1', indicates that octet written insertion memory first word cell, start cell. This when first octet cell word placed data line, again until cell transaction been completed, thus allowing proper cell insertion. This should after first octet been written. Cell Insertion Memory Data When data written this location, data transferred Insertion Memory. entire cell transfer, octets must written before next cell data accessed. Remember, MUST first octet cell placed into insertion memory.
RXATC_EMEM Extraction Memory Access 'h0C (Part
Field
Bits
Access
Function
Default
Extraction Memory When this '1', indicates that octet read from extraction memory first octet cell, start cell. This when first octet cell word placed data line, again until cell transaction been completed.
Altera Corporation
ACell Processor Mbps MegaCore Function (CP155) User Guide
GettiSpecifications
RXATC_EMEM Extraction Memory Access 'h0C (Part
Field
Specifications
Function Default
Bits
Access
Cell Insertion/Extraction Memory Data When data read from this location, data transferred from Extraction Memory. When data written this location, data transferred Insertion Memory. entire cell transfer, 53-octets must read before next cell data accessed. Remember, indicates first octet cell.
RXATC_PM_ERR Error Performance Monitoring 'h20
Field
Bits
15:0
Access
RTCW
Function
Default
Error Counter This 16-bit register represents number errors detected transmitter cell processor. includes header Atlantic interface errors. counter incremented each error, will saturate after reaches 'hFFFF.
RXATC_PM_CELL Cell Performance Monitoring 'h22
Field
Bits
15:0
Access
RTCW
Function
Default
Cell Counter This 16-bit register represents number cells that have been written into cell buffer. Cells that have been discarded errors, filtering, non-successful writes caused overflow cell buffer counted. This register incremented each cell that successfully written. counter will saturate after reaches 'hFFFF.
RXATC_PM_DISC Discard Cell Performance Monitoring 'h24
Field
Bits
15:0
Access
RTCW
Function
Default
Discarded Cell Counter This 16-bit register represents number discarded cells. errors, filtering, non-successful writes provoked overflow cell buffer cause cells discarded. This counter incremented each discarded cell, will saturate after reaches 'hFFFF.
Altera Corporation
Specifications
ACell Processor Mbps MegaCore Function (CP155) User Guide
RXATC_PM_CHEC Correctable Performance Monitoring 'h26
Field
Bits
15:0
Access
RTCW
Function
Default
Correctable Counter This 16-bit register represents number cells that have single error header corrected. This register incremented when correctable sequence, correction mode, detected. counter will saturate after reaches 'hFFFF.
RXATC_PM_UHEC Uncorrectable Performance Monitoring 'h28
Field
Bits
15:0
Access
RTCW
Function
Default
Uncorrectable Counter This 16-bit register represents number cells that have multi-bit error uncorrected single error sequence. This register incremented each cell that uncorrected sequence, will saturate after reaches 'hFFFF.
RXATC_PM_OAM Filter Performance Monitoring 'h2A
Field
Bits
15:0
Access
RTCW
Function
Default
Filter Performance Monitoring This 16-bit register represents number cells that filtered filter. criteria cell filtering based upon filter control register. This counter incremented cells that match filter pattern, entire cell discarded. counter will saturate after reaches 'hFFFF.
RXATC_PM_FILT0 Filter Performance Monitoring 'h2C
Field
Bits
15:0
Access
RTCW
Function
Filter Performance Monitoring This 16-bit register represents number cells that filtered. cell filtering criteria based upon associative CTRL, filter registers. filter must enabled match cell based pattern, sense, check this register incremented. counter will saturate after reaches 'hFFFF.
Default
Altera Corporation
ACell Processor Mbps MegaCore Function (CP155) User Guide
GettiSpecifications
RXATC_PM_FILT1 Filter Performance Monitoring 'h2E
Field
Specifications
Function Default
Bits
15:0
Access
RTCW
Filter Performance Monitoring This 16-bit register represents number cells that filtered. cell filtering criteria based upon associative CTRL, filter registers. filter must enabled match cell based pattern, sense, check this register incremented. counter will saturate after reaches 'hFFFF.
RXATC_PM_FILT2 Filter Performance Monitoring 'h30
Field
Bits
15:0
Access
RTCW
Function
Filter Performance Monitoring This 16-bit register represents number cells that filtered. cell filtering criteria based upon associative CTRL, filter registers. filter must enabled match cell based pattern, sense, check this register incremented. counter will saturate after reaches 'hFFFF.
Default
RXATC_PM_FILT3 Filter Performance Monitoring 'h32
Field
Bits
15:0
Access
RTCW
Function
Filter Performance Monitoring This 16-bit register represents number cells that filtered. cell filtering criteria based upon associative CTRL, filter registers. filter must enabled match cell based pattern, sense, check this register incremented. counter will saturate after reaches 'hFFFF.
Default
Altera Corporation
Specifications
ACell Processor Mbps MegaCore Function (CP155) User Guide
RXATC_FILT0_CTRL Filter Control Register 'h40
Field
Bits
Access
Function
Default
Filter Action These bits control filter action. '1', filter performs copy cell action. '0', filter performs don't copy cell action. '1', filter performs discard cell action. '0', filter performs enqueue cell action. Filter Sense This controls filter mode. '1', acts cells that matches pattern. '0', acts cells that match pattern. Filter Enable When this '1', filter enabled.
RXATC_FILT0_PAT0 Filter Pattern 'h42
Field
MATCH
Bits
15:0
Access
Function
Default
Filter Pattern Lower These bits lower pattern that must match first bits incoming cell filter take action. Note, only bits with corresponding CHECK register actually checked.
RXATC_FILT0_PAT1 Filter Pattern 'h44
Field
MATCH
Bits
15:0
Access
Function
Default
Filter Pattern Upper These bits upper pattern that must match first bits incoming cell filter take action. Note, only bits with corresponding CHECK register actually checked.
Altera Corporation
ACell Processor Mbps MegaCore Function (CP155) User Guide
GettiSpecifications
RXATC_FILT0_CHK0 Filter Check 'h46
Field
MATCH
Specifications
Function Default
Bits
15:0
Access
Filter Check Lower These bits lower bits check area. position actually checked. corresponding must match corresponding incoming cell header there full match. position checked, therefore effectively don't care bit.
RXATC_FILT0_CHK1 Filter Check 'h48
Field
MATCH
Bits
15:0
Access
Function
Default
Filter Check Lower These bits lower bits check area. position actually checked. corresponding must match corresponding incoming cell header there full match. position checked, therefore effectively don't care bit.
RXATC_FILT1_CTRL Filter Control Register 'h4A
Field
Bits
Access
Function
Default
Filter Action These bits control filter action. '1', filter performs copy cell action. '0', filter performs don't copy cell action. '1', filter performs discard cell action. '0', filter performs enqueue cell action. Filter Sense This controls filter mode. '1', acts cells that matches pattern. '0', acts cells that match pattern. Filter Enable When this '1', filter enabled.
Altera Corporation
Specifications
ACell Processor Mbps MegaCore Function (CP155) User Guide
RXATC_FILT1_PAT0 Filter Pattern 'h4C
Field
MATCH
Bits
15:0
Access
Function
Default
Filter Pattern Lower These bits lower pattern that must match first bits incoming cell filter take action. Note, only bits with corresponding CHECK register actually checked.
RXATC_FILT1_PAT1 Filter Pattern 'h4E
Field
MATCH
Bits
15:0
Access
Function
Default
Filter Pattern Upper These bits upper pattern that must match first bits incoming cell filter take action. Note, only bits with corresponding CHECK register actually checked.
RXATC_FILT1_CHK0 Filter Check 'h50
Field
MATCH
Bits
15:0
Access
Function
Default
Filter Check Lower These bits lower bits check area. position actually checked. corresponding must match corresponding incoming cell header there full match. position checked, therefore effectively don't care bit.
RXATC_FILT1_CHK1 Filter Check 'h52
Field
MATCH
Bits
15:0
Access
Function
Default
Filter Check Lower These bits lower bits check area. position actually checked. corresponding must match corresponding incoming cell header there full match. position checked, therefore effectively don't care bit.
Altera Corporation
ACell Processor Mbps MegaCore Function (CP155) User Guide
GettiSpecifications
RXATC_FILT2_CTRL Filter Control Register 'h54
Field
Specifications
Function Default
Bits
Access
Filter Action These bits control filter action. '1', filter performs copy cell action. '0', filter performs don't copy cell action. '1', filter performs discard cell action. '0', filter performs enqueue cell action. Filter Sense This controls filter mode. '1', acts cells that matches pattern. '0', acts cells that match pattern. Filter Enable When this '1', filter enabled.
RXATC_FILT2_PAT0 Filter Pattern 'h56
Field
MATCH
Bits
15:0
Access
Function
Default
Filter Pattern Lower These bits lower pattern that must match first bits incoming cell filter take action. Note, only bits with corresponding CHECK register actually checked.
RXATC_FILT2_PAT1 Filter Pattern 'h58
Field
MATCH
Bits
15:0
Access
Function
Default
Filter Pattern Upper These bits upper pattern that must match first bits incoming cell filter take action. Note, only bits with corresponding CHECK register actually checked.
Altera Corporation
Specifications
ACell Processor Mbps MegaCore Function (CP155) User Guide
RXATC_FILT2_CHK0 Filter Check 'h5A
Field
MATCH
Bits
15:0
Access
Function
Default
Filter Check Lower These bits lower bits check area. position actually checked. corresponding must match corresponding incoming cell header there full match. position checked, therefore effectively don't care bit.
RXATC_FILT2_CHK1 Filter Check 'h5C
Field
MATCH
Bits
15:0
Access
Function
Default
Filter Check Lower These bits lower bits check area. position actually checked. corresponding must match corresponding incoming cell header there full match. position checked, therefore effectively don't care bit.
RXATC_FILT3_CTRL Filter Control Register 'h5E
Field
Bits
Access
Function
Default
Filter Action These bits control filter action. '1', filter performs copy cell action. '0', filter performs don't copy cell action. '1', filter performs discard cell action. '0', filter performs enqueue cell action. Filter Sense This controls filter mode. '1', acts cells that matches pattern. '0', acts cells that match pattern. Filter Enable When this '1', filter enabled.
Altera Corporation
ACell Processor Mbps MegaCore Function (CP155) User Guide
GettiSpecifications
RXATC_FILT3_PAT0 Filter Pattern 'h60
Field
MATCH
Specifications
Function Default
Bits
15:0
Access
Filter Pattern Lower These bits lower pattern that must match first bits incoming cell filter take action. Note, only bits with corresponding CHECK register actually checked.
RXATC_FILT3_PAT1 Filter Pattern 'h62
Field
MATCH
Bits
15:0
Access
Function
Default
Filter Pattern Upper These bits upper pattern that must match first bits incoming cell filter take action. Note, only bits with corresponding CHECK register actually checked.
RXATC_FILT3_CHK0 Filter Check 'h64
Field
MATCH
Bits
15:0
Access
Function
Default
Filter Check Lower These bits lower bits check area. position actually checked. corresponding must match corresponding incoming cell header there full match. position checked, therefore effectively don't care bit.
RXATC_FILT3_CHK1 Filter Check 'h66
Field
MATCH
Bits
15:0
Access
Function
Default
Filter Check Lower These bits lower bits check area. position actually checked. corresponding must match corresponding incoming cell header there full match. position checked, therefore effectively don't care bit.
Altera Corporation
Specifications
ACell Processor Mbps MegaCore Function (CP155) User Guide
TXATC Register Description
following tables describe registers transmitter section CP155.
TXATC_CTRL Control Register 'h80 (Part
Field
GFCINS
Bits
Access
Function
Default
Insert These bits determine whether each individually transmitted should inserted from serial input interface. When '1', altered with serial bit. Otherwise, value modified. insertion provides ability insert value into field header Acell. field represented first four bits first header byte carrying information about local flow control. Insertion done using serial input port controlled enable register bit. enable set, existing value modified. When enabled, value inserted during each cell-processing period. next transmit cell idle/unassigned cell, enable register set, value Idle Cell Header register overwritten. Check When this '1', incoming checked against regenerated HEC. When '0', error checking disabled, errors ignored. Invert When this '1', inversion performed.
HECCHK
HECINV HECADD
Addition When this '1', performs Modula addition ('b0101_0101) header, before comparison. Regenerate When this '1', cells with uncorrectable headers regenerated. generating polynomial with optional modula addition based hecadd bit. regenerate default. Scrambling When this '1', payload self-synchronous scrambling performed, using x*43 polynomial.
HECRGN
SCRAM
Altera Corporation
ACell Processor Mbps MegaCore Function (CP155) User Guide
GettiSpecifications
TXATC_CTRL Control Register 'h80 (Part
Field
Specifications
Function Default
Bits
Access
Enable When this '0', cell processor disabled. cell processor remains static state continues ignore enables until '1'. Note, must before cell received.
TXATC_STAT Status Register 'h82
Field
IMEMDAV
Bits
Access
Function
Insertion Memory Data Available This indicates current Insertion Memory Data Available status. when insertion memory room entire cell written memory.
Default
EMEMDAV
Extraction Memory Data Available This indicates current Extraction Memory Data Available status. when extraction memory entire cell read from memory.
TXATC_IS Interrupt Status Register 'h84 (Part
Field
IMEMOFLW
Bits
Access
RW1C
Function
Default
Insertion Memory Overflow Interrupt When this '1', indicates that insertion memory overflow occurred. attempt write cell insertion memory cause cell discarded. Extraction Memory Overflow Interrupt When this '1', indicates that extraction memory overflow occurred. attempt write cell extraction memory causes cell discarded.
EMEMOFLW
RW1C
IMEMDAV
RW1C
Insertion Memory Data Available Interrupt When this '1', indicates that insertion memory room entire cell written memory. Extraction Memory Data Available Interrupt When this '1', indicates that extraction memory entire cell read from memory. Cell Insertion Interrupt When this '1', indicates that cell been drawn from memory inserted into data path.
EMEMDAV
RW1C
IMEMCELL
RW1C
Altera Corporation
Specifications
ACell Processor Mbps MegaCore Function (CP155) User Guide
TXATC_IS Interrupt Status Register 'h84 (Part
Field
EMEMCELL
Bits
Access
RW1C
Function
Default
Cell Extraction Interrupt When this '1', indicates that cell been extracted from data path into memory. Atlantic Interface Error Interrupt this '1', indicates cell/packet error been detected. This register when cell/packet error found word incoming cell entering cell processor. Error Interrupt this '1', indicates error been detected. criteria based upon options found control register.
AERR
RW1C
HERR
RW1C
TXATC_IE Interrupt Enable Register 'h86
Field
IMEMOFLW
Bits
Access
Function
Default
Insertion Memory Overflow Interrupt Enable This enables Insertion Memory Overflow interrupt asserted line. Extraction Memory Overflow Interrupt Enable This enables Extraction Memory Overflow interrupt asserted line. Insertion Memory Data Available Interrupt Enable This enables Insertion Memory Data Available interrupt asserted line. Extraction Memory Data Available Interrupt Enable This enables Extraction Memory Data Available interrupt asserted line.
EMEMOFLW
IMEMDAV
EMEMDAV
IMEMCELL
Cell Insertion Interrupt Enable This enables Cell Insertion interrupt asserted line. Cell Extraction Interrupt Enable This enables Cell Extraction interrupt asserted line. Atlantic Interface Error Interrupt Enable This enables Cell/Packet Error interrupt asserted line. Error Interrupt Enable This enables Error interrupt asserted line.
EMEMCELL
AERR
HERR
Altera Corporation
ACell Processor Mbps MegaCore Function (CP155) User Guide
GettiSpecifications
TXATC_OAM Filter Control Register 'h88
Field
MGFC
Specifications
Function Default
Bits
15:12
Access
Match 4'b1111 These four bits used include specified bits filter pattern. When '0', corresponding masked from pattern represents don't care that matches both logical logical zero. Match 3'b111 These three bits used include specified bits filter pattern. When '0', corresponding masked from pattern represents don't care that matches both logical logical zero. Match 1'b1 This used include specified filter pattern. When '0', masked from pattern represents don't care that matches both logical logical zero. These four bits used identify Generic Flow Control (GFC) bits first octet filter pattern. Together, GFC, form base filter pattern. header value matching this pattern discarded. filter statically '0'. match used exclude certain bits from this filter pattern. Payload Type These three bits used determine payload type (PT) filtering cells. bits precede found fourth octet. Together, GFC, form base filter pattern. header value matching this pattern discarded. filter statically '0'. match used exclude from filter pattern. Cell Loss Priority 1'b1 When this '1', asserts cell loss priority (CLP) cell '1'; otherwise '0'. last header found fourth octet. Together, GFC, bits form base filter pattern. header value matching this pattern discarded. filter statically '0'. match used exclude certain bits from filter pattern.
11:9
MCLP
Altera Corporation
Specifications
ACell Processor Mbps MegaCore Function (CP155) User Guide
TXATC_IDLE Idle Cell Control Register 'h8A
Field
PYLD
Bits
15:8
Access
Function
Payload These eight bits used represent pattern inserted payload idle cells. Idle cells defaulted idle cell payload 'b01101010. These four bits used bits idle cell header. Idle cells defaulted 'b0000. Payload Type These three bits used bits idle cell header. Idle cells defaulted '0'.
Default
8'h6A
Cell Loss Priority This used idle cell header. Idle cells defaulted '1'.
TXATC_IMEM Insertion Memory Access 'h8C
Field
Bits
Access
Function
Default
Insertion Memory When this '1', indicates that octet written insertion memory first word cell, start cell. This must conjunction with first octet cell word being placed data line, again until cell transaction been completed, thus allowing proper cell insertion. After first octet been written, this should '0'. Cell Insertion Memory Data When data written this location, data transferred Insertion Memory. entire cell transfer, 53octets must written before next cell data accessed. Remember, must first octet cell placed into insertion memory.
Altera Corporation
ACell Processor Mbps MegaCore Function (CP155) User Guide
GettiSpecifications
TXATC_EMEM Extraction Memory Access 'h8E
Field
Specifications
Function Default
Bits
Access
Extraction Memory When this '1', indicates that octet read from extraction memory first octet cell, start cell. This conjunction with first octet cell word being placed data line, shall again until cell transaction been completed. Cell /Extraction Memory Data When data read from this location, data transferred from Extraction Memory. When data written this location, data transferred Insertion Memory. entire cell transfer, 53-octets must read before next cell data accessed. Remember, indicates first octet cell.
TXATC_PM_ERR Error Performance Monitoring 'hA0
Field
Bits
15:0
Access
RTCW
Function
Default
Error Counter This 16-bit register represents number errors detected transmitter cell processor, including header Atlantic interface errors. This register incremented each error, will saturate after reaches 'hFFFF.
TXATC_PM_CELL Cell Performance Monitoring 'hA2
Field
Bits
15:0
Access
RTCW
Function
Default
Cell Counter This 16-bit register represents number cells that have been read from cell buffer, that have been discarded because filtering overflow conditions. This register incremented each cell successfully read, will saturate after reaches 'hFFFF.
Altera Corporation
Specifications
ACell Processor Mbps MegaCore Function (CP155) User Guide
TXATC_PM_DISC Discard Cell Performance Monitoring 'hA4
Field
Bits
15:0
Access
RTCW
Function
Default
Discarded Cell Counter This 16-bit register represents number cells that have been discarded through cell filtering. This register incremented each discarded cell, will saturate after reaches 'hFFFF.
TXATC_PM_HERR Error Performance Monitoring 'hA6
Field
Bits
15:0
Access
RTCW
Function
Default
Error Counter This 16-bit register represents number cells that have error. This register incremented when cell error detected, will saturate after reaches 'hFFFF.
TXATC_PM_AERR Atlantic Error Performance Monitoring 'hA8
Field
Bits
15:0
Access
RTCW
Function
Default
Atlantic Interface Error Counter This 16-bit register represents number cells that have Atlantic Interface error. This register incremented each cell with this error, will saturate after reaches 'hFFFF.
TXATC_PM_OAM Filter Performance Monitoring 'hAA
Field
Bits
15:0
Access
RTCW
Function
Default
Filter Performance Monitoring This 16-bit register represents number cells that filtered filter. cell filtering criteria based upon filter control register. This register incremented cells that match filter pattern, entire cell discarded. counter will saturate after reaches 'hFFFF.
Altera Corporation
ACell Processor Mbps MegaCore Function (CP155) User Guide
GettiSpecifications
TXATC_PM_FILT0 Filter Performance Monitoring 'hAC
Field
Specifications
Function Default
Bits
15:0
Access
RTCW
Filter Performance Monitoring This 16-bit register represents number cells that filtered. cell filtering criteria based upon associative CTRL, filter registers. filter must enabled match cell based pattern, sense, check this register incremented. counter will saturate after reaches 'hFFFF.
TXATC_PM_FILT1 Filter Performance Monitoring 'hAE
Field
Bits
15:0
Access
RTCW
Function
Filter Performance Monitoring This 16-bit register represents number cells that filtered. cell filtering criteria based upon associative CTRL, filter registers. filter must enabled match cell based pattern, sense, check this register incremented. counter will saturate after reaches 'hFFFF.
Default
TXATC_PM_FILT2 Filter Performance Monitoring 'hB0
Field
Bits
15:0
Access
RTCW
Function
Filter Performance Monitoring This 16-bit register represents number cells that filtered. cell filtering criteria based upon associative CTRL, filter registers. filter must enabled match cell based pattern, sense, check this register incremented. counter will saturate after reaches 'hFFFF.
Default
Altera Corporation
Specifications
ACell Processor Mbps MegaCore Function (CP155) User Guide
TXATC_PM_FILT3 Filter Performance Monitoring 'hB2
Field
Bits
15:0
Access
RTCW
Function
Filter Performance Monitoring This 16-bit register represents number cells that filtered. cell filtering criteria based upon associative CTRL, filter registers. filter must enabled match cell based pattern, sense, check this register incremented. counter will saturate after reaches 'hFFFF.
Default
TXATC_FILT0_CTRL Filter Control Register 'hC0
Field
Bits
Access
Function
Default
Filter Action These bits control filter action. '1', filter performs copy cell action. '0', filter performs don't copy cell action. '1', filter performs discard cell action. '0', filter performs enqueue cell action. Filter Sense This controls filter mode. '1', acts cells that match pattern. '0', acts cells that match pattern. Filter Enable When this '1', filter enabled.
TXATC_FILT0_PAT0 Filter Pattern 'hC2
Field
MATCH
Bits
15:0
Access
Function
Default
Filter Pattern Lower These bits lower pattern that must match first bits incoming cell filter take action. Note, only bits with corresponding CHECK register actually checked.
Altera Corporation
ACell Processor Mbps MegaCore Function (CP155) User Guide
GettiSpecifications
TXATC_FILT0_PAT1 Filter Pattern 'hC4
Field
MATCH
Specifications
Function Default
Bits
15:0
Access
Filter Pattern Upper These bits upper pattern that must match first bits incoming cell filter take action. Note, only bits with corresponding CHECK register actually checked.
TXATC_FILT0_CHK0 Filter Check 'hC6
Field
MATCH
Bits
15:0
Access
Function
Default
Filter Check Lower These bits lower bits check area. position actually checked. corresponding must match corresponding incoming cell header there full match. position checked, therefore effectively don't care bit.
TXATC_FILT0_CHK1 Filter Check 'hC8
Field
MATCH
Bits
15:0
Access
Function
Default
Filter Check Lower These bits lower bits check area. position actually checked. corresponding must match corresponding incoming cell header there full match. position checked, therefore effectively don't care bit.
TXATC_FILT1_CTRL Filter Control Register 'hCA (Part
Field
Bits
Access
Function
Default
Filter Action These bits control filter action. '1', filter performs copy cell action. '0', filter performs don't copy cell action. '1', filter performs discard cell action. '0', filter performs enqueue cell action.
Altera Corporation
Specifications
ACell Processor Mbps MegaCore Function (CP155) User Guide
TXATC_FILT1_CTRL Filter Control Register 'hCA (Part
Field
Bits
Access
Function
Filter Sense This controls filter mode. '1', acts cells that match pattern. '0', acts cells that match pattern. Filter Enable When this '1', filter enabled.
Default
TXATC_FILT1_PAT0 Filter Pattern 'hCC
Field
MATCH
Bits
15:0
Access
Function
Default
Filter Pattern Lower These bits lower pattern that must match first bits incoming cell filter take action. Note, only bits with corresponding CHECK register actually checked.
TXATC_FILT1_PAT1 Filter Pattern 'hCE
Field
MATCH
Bits
15:0
Access
Function
Default
Filter Pattern Upper These bits upper pattern that must match first bits incoming cell filter take action. Note, only bits with corresponding CHECK register actually checked.
TXATC_FILT1_CHK0 Filter Check 'hD0
Field
MATCH
Bits
15:0
Access
Function
Default
Filter Check Lower These bits lower bits check area. position actually checked. corresponding must match corresponding incoming cell header there full match. position checked, therefore effectively don't care bit.
Altera Corporation
ACell Processor Mbps MegaCore Function (CP155) User Guide
GettiSpecifications
TXATC_FILT1_CHK1 Filter Check 'hD2
Field
MATCH
Specifications
Function Default
Bits
15:0
Access
Filter Check Lower These bits lower bits check area. position actually checked. corresponding must match corresponding incoming cell header there full match. position checked, therefore effectively don't care bit.
TXATC_FILT2_CTRL Filter Control Register 'hD4
Field
Bits
Access
Function
Default
Filter Action These bits control filter action. '1', filter performs copy cell action. '0', filter performs don't copy cell action. '1', filter performs discard cell action. '0', filter performs enqueue cell action. Filter Sense This controls filter mode. '1', acts cells that match pattern. '0', acts cells that match pattern. Filter Enable When this '1', filter enabled.
TXATC_FILT2_PAT0 Filter Pattern 'hD6
Field
MATCH
Bits
15:0
Access
Function
Default
Filter Pattern Lower These bits lower pattern that must match first bits incoming cell filter take action. Note, only bits with corresponding CHECK register actually checked.
Altera Corporation
Specifications
ACell Processor Mbps MegaCore Function (CP155) User Guide
TXATC_FILT2_PAT1 Filter Pattern 'hD8
Field
MATCH
Bits
15:0
Access
Function
Default
Filter Pattern Upper These bits upper pattern that must match first bits incoming cell filter take action. Note, only bits with corresponding CHECK register actually checked.
TXATC_FILT2_CHK0 Filter Check 'hDA
Field
MATCH
Bits
15:0
Access
Function
Default
Filter Check Lower These bits lower bits check area. position actually checked. corresponding must match corresponding incoming cell header there full match. position checked, therefore effectively don't care bit.
TXATC_FILT2_CHK1 Filter Check 'hDC
Field
MATCH
Bits
15:0
Access
Function
Default
Filter Check Lower These bits lower bits check area. position actually checked. corresponding must match corresponding incoming cell header there full match. position checked, therefore effectively don't care bit.
TXATC_FILT3_CTRL Filter Control Register 'hDE (Part
Field
Bits
Access
Function
Default
Filter Action These bits control filter action. '1', filter performs copy cell action. '0', filter performs don't copy cell action. '1', filter performs discard cell action. '0', filter performs enqueue cell action.
Altera Corporation
ACell Processor Mbps MegaCore Function (CP155) User Guide
GettiSpecifications
TXATC_FILT3_CTRL Filter Control Register 'hDE (Part
Field
Specifications
Default
Bits
Access
Function
Filter Sense This controls filter mode. '1', acts cells that match pattern. '0', acts cells that match pattern. Filter Enable When this '1', filter enabled.
TXATC_FILT3_PAT0 Filter Pattern 'hE0
Field
MATCH
Bits
15:0
Access
Function
Default
Filter Pattern Lower These bits lower pattern that must match first bits incoming cell filter take action. Note, only bits with corresponding CHECK register actually checked.
TXATC_FILT3_PAT1 Filter Pattern 'hE2
Field
MATCH
Bits
15:0
Access
Function
Default
Filter Pattern Upper These bits upper pattern that must match first bits incoming cell filter take action. Note, only bits with corresponding CHECK register actually checked.
TXATC_FILT3_CHK0 Filter Check 'hE4
Field
MATCH
Bits
15:0
Access
Function
Default
Filter Check Lower These bits lower bits check area. position actually checked. corresponding must match corresponding incoming cell header there full match. position checked, therefore effectively don't care bit.
Altera Corporation
Specifications
ACell Processor Mbps MegaCore Function (CP155) User Guide
TXATC_FILT3_CHK1 Filter Check 'hE6
Field
MATCH
Bits
15:0
Access
Function
Default
Filter Check Lower These bits lower bits check area. position actually checked. corresponding must match corresponding incoming cell header there full match. position checked, therefore effectively don't care bit.
Core Verification Summary
full-feature variant CP155 object very thorough verification, thus should operate according industry standards. CP155 tested simulation, third-party compatibility. Both testing environments described briefly, including number test programs, their results.
Simulation Environment
CP155 simulated using behavioral utilities with multiple simulators, including limited ModelSim behavioral utilities consist generic flow control generators monitors, Midbus generators monitors, Atlantic generators monitors, AIRbus master model, clock generators. test suite using utilities model CP155 used verify proper operation features listed page Table lists results simulation full-feature variant CP155
Table Results
Number test programs Number test programs passing Number test programs failing Number test cases Number test cases passing Number test cases failing Note:
Each test program contains least test case.
Altera Corporation
ACell Processor Mbps MegaCore Function (CP155) User Guide
GettiSpecifications
Compatibility Testing Environment
full-feature variant CP155 evaluated-within APEX EP20K1000EFC672 device-against commercial third-party cell processor with similar features, required industry standards. testing purposes, CP155 interconnected with Altera STS3CFRM MegaCore function, Altera MegaCore function used interface AIRbus third-party cell processor. Figure shows test board used. Software from host used registers CP155, third-party cell processor. effects setting these registers, corresponding registers, were observed determine functionality. Tests were extended periods time, thereby testing millions cells.
Specifications
Figure Test Board
Third-Party ASSP
APEX EP20K1000EFC672
Table lists results hardware verification full-feature variant CP155.
Table Results
Number test programs Number test programs passing Number test programs failing Number test cases Number test cases passing Number test cases failing Note:
Each test program contains least test case.
Altera Corporation
Notes:
Getting Started
User Guide
This section describes obtain variant from ACell Processor155 Mbps MegaCore® Function (CP155). explains install CP155 your walks through process implementing variant design. test-drive CP155 using Altera® OpenCore® feature-within Quartus® software-to instantiate perform place-and-route, perform static timing analysis, simulate using third-party simulator, within your custom logic. only need licenses when ready generate programming files.
Getting Started Getting Started
Design Walkthrough
This design walkthrough involves following steps: Obtaining installing CP155 MegaCore Function. Generating custom CP155 your system using MegaWizard® Plug-In. Implementing rest your system using AHDL, VHDL, Verilog HDL. Simulating CP155 within your design. Synthesis, compilation, place-and-route. Licensing CP155 configure device. Performing post-routing simulation.
instructions assume that:
using familiar with Quartus software. Quartus software (the newest version) installed default location. using OpenCore feature test-drive CP155, have licensed
Altera Corporation
Getting Started
ACell Processor Mbps MegaCore Function (CP155) User Guide
Obtaining Installing CP155
start using CP155, need obtain MegaCore package, which includes following:
Data sheet User guide AIRbus, Midbus, Atlantic interface functional specifications MegaWizard Plug-In Encrypted gate level netlist Place-and-route constraints (where necessary) Secure simulation model Demo testbench Access problem reporting system
Downloading MegaCore Function
have Internet access, download ACell Processor Mbps MegaCore function from Altera site. Follow instructions below obtain core Internet. have Internet access, obtain core from your local Altera representative. Point your browser MegaSearch keyword field type ATM. Click link ACell Processor Mbps MegaCore function. product page, click Free Test-Drive icon. Follow on-line instructions download function save your hard disk.
Installing MegaCore Files
MegaWizard Plug-In generate files install them your following instructions describe this process. UNIX systems, must have Java runtime environment version before MegaWizard Plug-In. download this file from Java site http://www.java.sun.com. Windows, follow instructions below: Click (Start menu).
Altera Corporation
ACell Processor Mbps MegaCore Function (CP155) User Guide
GettingGetting Started
Type <path name>\<filename>.exe, where <path name> location downloaded CP155 <filename> filename CP155. Click MegaCore Installer dialog appears. Follow MegaWizard Plug-In instructions finish installation. Disregard this step using Quartus version higher. Otherwise, after have finished installing files, must specify directory which installed them user library Quartus software. Search "User Libraries" Quartus Help instructions these libraries.
Getting Started
Generating custom CP155
This section describes design flow using ACell Processor MegaCore function Quartus development system. MegaWizard Plug-In provided with CP155. MegaWizard PlugIn Manager-used within Quartus software-allows create modify design files meet needs your application. then instantiate CP155 your design file. create custom CP155 using MegaWizard Plug-In, follow these steps: Start MegaWizard Plug-In choosing MegaWizard Plug-In Manager command (Tools menu) Quartus software. MegaWizard Plug-In Manager dialog displayed. Refer Quartus Help detailed instructions MegaWizard Plug-In Manager. Specify that want create custom variant click Next. second page MegaWizard Plug-In, open Communications folder, select CP155 from Afolder. Choose type output files (language), specify folder name files MegaWizard Plug-In creates, click Next. Select optional parameters choices that require. final screen lists design files created MegaWizard Plug-In, indicates location simulation models selected variant. Click Finish.
Altera Corporation
Getting Started
ACell Processor Mbps MegaCore Function (CP155) User Guide
Implementing System
Once have created your CP155, ready implement files generated MegaWizard Plug-In, Quartus software other tools create your design. Table lists generated files.
Table MegaWizard Plug-In Files
Description Design File Wrapper Sample Instantiation Black Module Symbol files Quartus software used instantiate UTOPIA3SL into schematic design encrypted netlist file Verilog
_inst.v _bb.v
VHDL
.vhd _inst.vhd
AHDL
.tdf _inst.tdf
.bsf
.bsf
.bsf
.e.vqm.v
.e.vqm.v
.e.vqm.v
Simulating Your Design
Altera provides three models used functional verification CP155 within your design. Verilog demo testbench, including scripts also provided. This demo testbench used with ModelSim SE/PE simulator demonstrates instantiate model design. find simulation models your selected variant, refer last page MegaWizard Plug-In Manager. These models demo testbench located your hard drive, paths are:
sim_lib/<variant>/visual_ip/ sim_lib/<variant>/test/ <variant> unique code (aotXXXX_#_cp155) assigned specific configuration requested through MegaWizard PlugIn.
Using Verilog Demo Testbench
demo testbench includes some simple stimulus control user interfaces CP155. Each CP155 variant includes scripts compile demo testbench using variety simulators models.
Altera Corporation
ACell Processor Mbps MegaCore Function (CP155) User Guide
GettingGetting Started
Using Visual Software
Visual software facilitates Visual simulation models with third-party simulation tools. view simulation model, must have Visual software installed your system. download software, instructions software, refer Altera site http://www.altera.com, search Visual examples provided Visual model, refer sample scripts included with demo testbench.
Synthesis, Compilation Place Route
After have verified that your design functionally correct, ready perform synthesis place-and-route. Synthesis performed Quartus development tool, third-party synthesis tool. Quartus software works seamlessly with tools from many vendors, including Cadence, Exemplar Logic, Mentor Graphics, Synopsys, Synplicity, Viewlogic.
Getting Started
Using Third-Party Tools Synthesis
synthesize your design third-party tool, follow these steps: Create your custom design instantiating CP155. Synthesize design using your third-party tool. Your tool should treat CP155 instantiation black either setting attributes ignoring instantiation. After compilation, generate netlist file your third-party tool.
Using Quartus development tool compilation placeand-route
Quartus software compile place-and-route your design, follow these steps: Select Compile mode (Processing menu). Specify Compiler settings Compiler Settings dialog (Processing menu) Compiler Settings wizard. Disregard this step using Quartus version higher. Otherwise, specify user libraries project order which Compiler searches libraries.
Altera Corporation
Getting Started
ACell Processor Mbps MegaCore Function (CP155) User Guide
Specify input settings project. Choose Tool Settings (Project menu). Select Custom EDIF Design entry/synthesis tool list. Click Settings. Tool Input Settings dialog box, make sure that relevant tool name option selected Design Entry/Synthesis Tool list. your third-party tool-generated netlist file your project. .tdf, .vhd, files synthesized third-party tool. pre-synthesized encrypted .e.vqm.v file from your working directory, created MegaWizard Plug-In Manager. Constrain your design needed. Compile your design. Quartus Compiler synthesizes performs place-and-route your design.
Refer Quartus Help further instructions performing compilation.
Licensing Configuration
After have compiled analyzed your design, ready configure your targeted Altera semiconductor device. evaluating CP155 with OpenCore feature, must license function before generate programming files. obtain licenses contact your local Altera sales representative.
current CP155 variants single license, with ordering code: PLSM-CP155.
Performing Post-Routing Simulation
After have licensed CP155, generate EDIF, VHDL, Verilog HDL, Standard Delay Output Files from Quartus software them with your existing tools perform functional modeling post-routing simulation your design. Open your existing Quartus project. Depending type output file want, specify Verilog output settings VHDL output settings General Settings dialog (Project menu). Compile your design with Quartus software, refer "Using Quartus development tool compilation placeand-route"section. Quartus software generates output programing files.
Altera Corporation
ACell Processor Mbps MegaCore Function (CP155) User Guide
GettingGetting Started
import your Quartus software-generated output files (.edo, .vho, .vo, .sdo) into your third-party tool postroute, device-level, system-level simulation.
Getting Started
Altera Corporation
Notes:
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