SKEW CMOS CLOCK DRIVER 3-State Versions TS88915T Clock Driver uti

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SKEW CMOS CLOCK DRIVER 3-State Versions TS88915T Clock Driver uti

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TS88915T
SKEW CMOS CLOCK DRIVER 3-State Versions
TS88915T Clock Driver utilizes phazed-locked loop (PLL) technology lock skew outputs' frequency phase onto input reference clock. designed provide clock distribution high performance microprocessors such TS68040, TSPC603E,TSPC603P,TSPC603R, bridge, RAM's, MMU's.
MAIN FEATURES
MILITARY TEMPERATURE RANGE TS68040 FULL COMPATIBLE FIVE SKEW OUTPUTS Five Outputs (Q0-Q4) with Output-to-Output skew each being phase frequency locked SYNC input. ADDITIONAL OUTPUTS Three additional outputs available 2X_Q output runs twice system frequency. output runs system frequency. output inverted (180° phase shift). SELECTABLE CLOCK INPUTS selectable CLOCK inputs available test redundancy purposes. Test Mode (PLL_EN) provided frequency testing. outputs into high impedance (3-state) board test purpose. INPUT FREQUENCY RANGE FROM 5MHz 2X_Q FMAX THREE INPUT/OUTPUT RATIOS Input/Output phase-locked frequency ratios 1:2, available. PART-TO-PART SKEW phase variation from part-to-part between SYNC FEEDBACK inputs less than (derived from specification, which defines part-to-part skew). CMOS COMPATIBLE outputs drive either CMOS inputs. inputs TTL-level compatible. LOCK Indicator (LOCK) indicated phase-locked state.
Suffix Ceramic grid array
suffix LDCC Leaded Ceramic Chip Carrier
SCREENING QUALITY
This product manufactured based upon generic flow MIL-STD-883. according standard.
April 1999
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TS88915T
SUMMARY
GENERAL DESCRIPTION
INTRODUCTION ASSIGNMENTS 2.1. 29-Lead Grid Array (PGA) 2.2. 28-Lead Ceramic Leaded Chip Carrier (LDCC) SIGNAL DESCRIPTION
ELECTRICAL CHARACTERISTICS 4.1. General requirements 4.2. Static characteristics 4.2.1. electrical characteristics 4.2.2. Capacitance power specifications 4.3. Dynamic characteristics 4.3.1. Frequency applications 4.3.2. SYNC input timing requirements 4.3.3. characteristics
DETAILED SPECIFICATIONS
SCOPE APPLICABLE DOCUMENTS REQUIREMENTS 3.1. General 3.2. Design construction 3.2.1. Terminal connections 3.2.2. Lead material finish 3.2.3. Package
APPLICATION INFORMATION 5.1. General specification notes 5.2. Timing notes Notes concerning loop filter board layout issues 5.4. TS88915T system level testing functionality PREPARATION DELIVERY 6.1. Packaging 6.2. Certificate compliance HANDLING PACKAGE MECHANICAL DATA ORDERING INFORMATION
3.3. Electrical characteristics 3.4. Mechanical environment 3.5. Marking
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TS88915T
GENERAL INTRODUCTION
TS88915T CMOS Clock Driver using phase-locked loop (PLL) technology. allows high current, skew outputs lock onto single input distribute with essentially zero delay multiple components board. also allows TS88915T multiply frequency input clock distribute locally higher (2X) system frequency. Multiple 88915's lock onto single reference clock, which ideal applications when central system clock must distributed synchronously multiple boards (see Figure 12). Figure shows TS88915T block diagram.
FEEDBACK LOCK SYNC[0]
PHASE/FREQ. DETECTOR
CHARGE PUMP/ LOOP FILTER
VOLTAGE CONTROLLED OSCILLATOR
SYNC[1]
EXT. NETWORK (RC1 pin) REF_SEL
PLL_EN
2X_Q
(+1) DIVIDE (+2) FREQ_SEL OE/RST
Figure TS88915T Block Diagram (All versions)
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TS88915T
ASSIGNMENTS
2.1. 29-Lead Grid Array (PGA)
F/SL GNDA VCCA SYC0 FDBK R/SL TS88915T (BOTTOM VIEW) SYC1 P/EN LOCK
Figure 29-Lead (Bottom View)
2.2. 28-Lead Ceramic Leaded Chip Carrier (LDCC)
OE/RST FEEDBACK 2X_Q
REF_SEL
SYNC[0]
(AN)
TS88915T (TOP VIEW)
(AN)
SYNC[1]
LOCK
FREQ_SEL
PLL_EN
Figure 28-Lead LDCC (Top View)
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TS88915T
SIGNAL Name SYNC[0] SYNC[1] REF_SEL FREQ_SEL FEEDBACK Q(0-4) 2x_Q LOCK OE/RST PLL_EN VCC, Input Input Input Input Input Input Output Output Output Output Output Input Input Power Reference clock input Reference clock input Chooses reference between SYNC[0] SYNC[1] Doubles internal frequency Feedback input phase detector Input external network Clock output (locked SYNC) Inverse clock output clock output frequency (synchronous) Clock output frequency (synchronous) Indicates phase lock been achieved (high when locked) Output Enable Asynchronous reset (active low) Disables phase-lock frequency testing Power Ground pins Pins "analog" supply pins internal only Signal function
Table Signal index
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TS88915T
DETAILED SPECIFICATIONS
SCOPE
This drawing describes specific requirements clock driver TS88915T, compliance with MIL-STD-883 class standard screening.
APPLICABLE DOCUMENTS
MIL-STD-883 Test methods procedures electronics. MIL-PRF-38535 appendix General specifications microcircuits.
REQUIREMENTS 3.1. General
microcircuits accordance with applicable documents specified herein.
3.2. Design construction
3.2.1. Terminal connections Depending package, terminal connections shall shown Figure Figure GENERAL DESCRIPTION). 3.2.2. Lead material finish Lead material finish shall specified MIL-STD-1835 (see 3.2.3. Package macrocircuits packaged hermetically sealed ceramic packages which conform case outlines MIL-STD-1835, precise case outlines described specification into MIL-STD-1835.
3.3. Absolute maximum ratings
Stresses above absolute maximum rating cause permanent damage device. Extended operation maximum levels degrade performance affect reliability.
Parameter Supply voltage Input voltage Storage temperature range Power dissipation Package LDCC package Thermal resistance Junction-Case PGA29 LDCC28
Symbol Tstg
-0.5 -0.5
+150
Unit
°C/W
Note
Functional operating conditions given electrical specifications. Stresses beyond absolute maximums listed affect device reliability cause permanent damage device. Caution input voltage must greater than supply voltage more than times including during power-on reset. Table Absolute maximum rating TS88915T
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TS88915T
3.4. Mechanical environment microcircuits shall meet environmental requirements either MIL-STD-883 class devices standard screening.
3.5. Marking document where defined marking identified related reference documents. Each microcircuit legible permanently marked with following information minimum Thomson logo Manufacturer's part number Class identification Date-code inspection identifier available Country manufacturing
ELECTRICAL CHARACTERISTICS 4.1. General requirements
static dynamic electrical characteristics specified inspection purposes relevant measurement conditions given below: Table Static Electrical Characteristics electrical variants Table Dynamic Electrical Characteristics TS88915T (70MHz 100MHz versions)
4.2. Static characteristics
4.2.1. electrical characteristics (Voltages Referenced GND) -55°C +125°C version VCC= Symbol Parameter Minimum High-Level Input Voltage Maximum Low-Level Input Voltage Minimum High-Level Output Voltage Maximum Low-Level Output Voltage Test Conditions Vout Vout VIL, VCCmin VCCmax VIL, VIL, ICCT Maximum Input Leakage Current Maximum ICC/Input Maximum Quiescent Supply Current (per package) Maximum 3-State Leakage Current GND, VCCmax VCCmax GND, VCCmax VIL,VO=VCC GND, VCCmax Limits 4.01 4.51 0.44 0.50 0.20 $1.0 Unit
Note respectively LOCK output. Note PLL_EN input guaranteed meet this specification. Note Maximum test duration output loaded time. Note Specification value static tests 25°C minimum rated operating temperature. Note Specification value static tests maximum rated operating temperature. Note Specifications values which used compability with Power
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4.2.2. Capacitance power specifications Symbol Input Capacitance Power Dissipation Capacitance Power Dissipation with Thevenin Termination Power Dissipation with Parallel Termination Parameter Typical values 23mW/Output 184mW/Device 57mW/Output 456mW/Device Unit Conditions 25°C 25°C
Note
mW/Output output.
4.3. Dynamic characteristics (Tc=-55° +125°
4.3.1. Frequency specifications Guaranteed Minimum Symbol fmax Parameter 88915T-70 Maximum Operating Frequency (2X_Q Output) Maximum Operating Frequency (Q0-Q4, Outputs) 88915T-100 Unit
Note Maximum Operating Frequency guaranteed with part phase-locked condition, outputs loaded with terminated
4.3.2. SYNC input timing requirements Minimum Symbol tRISE/FALL, SYNC Inputs tCYCLE, SYNC Inputs Duty Cycle SYNC Inputs Parameter 88915T-70 88915T-100 Rise/Fall Time, SYNC Inputs From Input Clock Period, SYNC Inputs Input Duty Cycle, SYNC Inputs 28.5 20.0 Maximum Maxim Unit
Note These tCYCLE minimum values valid when output back connected FEEDBACK pin. Note Information Table Note specification notes describe this specification limits depending what output back, FREQ_SEL high low.
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4.3.3. characteristics (Tc=-55° +125° Symbol tRISE/FALL Outputs tRISE/FALL 2X_Q Output tPULSE WIDTH (Q0-Q4, Q/2) tPULSE WIDTH (2X_Q Output) Parameter Rise/Fall Time, Outputs (Between 0.2VCC 0.8VCC) Rise/Fall Time into Load, with Termination specified Note Output Pulse Width: VCC/2 Output Pulse Width: 2X_Q 1.5V 40-49 50-65 66-100
Load terminated VCC/2) Unit Conditions into Load Terminated VCC/2 tRISE:0.8V 2.0V tFALL:2.0V 0.8V into Load Terminated VCC/2 Must termination specified Note2 into Load Terminated VCC/2 Note Figure detailed explanation
0.5tCYCLE
0.5tCYCLE
0.5tCYCLE 0.5tCYCLE 0.5tCYCLE 0.5tCYCLE 0.5tCYCLE 0.5tCYCLE 0.5tCYCLE
0.5tCYCLE 0.5tCYCLE 0.5tCYCLE 0.5tCYCLE 0.5tCYCLE 0.5tCYCLE 0.5tCYCLE
tPULSE WIDTH (2X_Q Output) SYNC Feedback
Output Pulse Width: 2X_Q VCC/2
SYNC Input Feedback Delay (Measured SYNC0 FEEDBACK input pins)
(With from VCC) -1.05 -1.05 -0.40 -0.30
(With from GND) +1.25 tSKEWr Output-to-Output Skew between Out(Rising) puts Q0-Q4, (Rising edges only) Note tSKEWf (Falling) Output-to-Output Skew between Outputs Q0-Q4 (Falling edges only) +3.25 Outputs into matched load Terminated VCC/2 Outputs into matched load Terminated VCC/2 Outputs into matched load Terminated VCC/2 Also time lock indicator High Measured with PLL_EN Measured with PLL_EN
tSKEWall (Falling)
Output-to-Output Skew 2X_Q, Q/2, Q0-Q4 Rising, Falling
tLOCK
Time required acquire Phase-Lock from time SYNC inputs signal received Output Enable Time OE/RST 2X_Q, Q0-Q4, Output Disable Time OE/RST 2X_Q, Q0-Q4,
tPZL
tPHZ, tPLZ
Note These specification tested, they guaranteed statistical characterization. General specification Note Note tCYCLE this specification 1/Frequency which particular output running. Note specification's min/max values shift closer zero larger pull resistor used. Note Under equally loaded conditions fixed temperature voltage.
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TS88915T
Note With fully powered-on, output properly connected FEEDBACK pin. tLOCK maximum with tLOCK minimum with 0.01
SYNC INPUT (SYNC[1] SYNC[0])
tCYCLE SYNC INPUT
FEEDBACK INPUT
OUTPUT
tSKEWall
tSKEWf
tSKEWr
tSKEWf
tSKEWr
Q0-Q4 OUTPUTS
tCYCLE OUTPUTS
OUTPUT
2X_Q OUTPUT
Figure Output/Input switching waveforms timing diagrams (These waveforms represent hook-up configuration Figure
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TS88915T
APPLICATION INFORMATION
5.1. General specification notes Several specifications only measured when TS88915T phase-locked operation. TS88915T units were fabricated with transistor properties intentionally varied create cell designed experimental matrix. These specs (tRISE/FALL tPULSE WIDTH 2X_Q output) guarantee that TS88915T meets 33MHz TS68040 P-Clock input specification 66MHz). these specs guaranteed TCS, termination scheme shown below Figure must used.
TS88915 2X_Q Output
(CLOCK TRACE)
TS68040 P-Clock Input
Rs=Z0-7W Rp=1.5Z0
Figure TS68040 P-Clock input termination scheme
meet TS68040 P-clock input specification tpulse width Mhz) FREQ-SEL must low. This configuration improve accuracy 88915T duty cycle. wiring diagrams explanations Figure demonstrate input output frequency relationships three possible feedback configurations. allowable SYNC input range each case also indicated. There allowable SYNC frequency ranges, depending whether FREQ_SEL high low. Although shown, possible feed back output, thus creating 180° phase shift between SYNC input outputs. Table below summarizes allowable SYNC frequency range each possible configuration. FREQ_SEL Level FEEDBACK Output Allowable SYNC Input Frequency Range (MHz) Corresponding Frequency Range Phase Relationships Outputs Rising SYNC Edge 180° 180°
HIGH HIGH HIGH HIGH
(Q0-Q4) 2X_Q (Q0-Q4) 2X_Q
(2X_Q FMAX Spec)/4 (2X_Q FMAX Spec)/2 (2X_Q FMAX Spec)/2 (2X_Q FMAX Spec) (2X_Q FMAX Spec)/8 (2X_Q FMAX Spec)/4 (2X_Q FMAX Spec)/4 (2X_Q FMAX Spec)/2
FMAX Spec) (2X_Q (2X_Q FMAX Spec) (2X_Q FMAX Spec) (2X_Q FMAX Spec) (2X_Q FMAX Spec) (2X_Q FMAX Spec) (2X_Q FMAX Spec) (2X_Q FMAX Spec)
Table Allowable SYNC input frequency range different feedback configurations
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resistor tied either Analog Analog shown Figure required ensure jitter present TS88915T outputs. This technique causes phase offset between SYNC input output connected FEEDBACK input, measured input pins. spec describes this offset varies with process, temperature voltage. specs were arrived measuring phase relationship lots described Note while part phase-locked operation. actual measurements were made with 10MHz SYNC input (1.0ns edge rate from 0.8V 2.0V) with output back. phase measurements were made 1.5V. output terminated FEEDBACK input with 100W 100W GND.
EXTERNAL LOOP FILTER
330W 0.1mF REFERENCE RESISTOR ANALOG REFERENCE RESISTOR
330W
0.1mF
With resistor tied this fashion, specification measured input pins 2.25ns 1.0ns
With resistor tied this fashion, specification measured input pins -0.775ns 0.275ns
3.0V SYNC INPUT 2.25ns OFFSET 5.0V FEEDBACK OUTPUT SYNC INPUT
3.0V -0.775ns OFFSET 5.0V
FEEDBACK OUTPUT
Figure Depiction fixed SYNC Feedback offset (tPD) which present when resistor tied
tSKEWr specification guarantees that rising edges outputs Q/2, will always fall within 500ps window within part. However, relative position each output within this window specified, 500ps window must added each side specification limits calculate total part-to-part skew. this reason absolute distribution these outputs provided Table When taking skew data, used reference, measurements relative this output. information Table derived from measurements taken from process lots described Note over temperature voltage range. (ps) -274 -633 (ps)
Output 2X_Q
Table Relative position outputs Q/2, Q0-Q4, 2X_Q, within 500ps tSKEWr spec window
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TS88915T
Calculation Total Output-to-Output skew between multiple parts (Part-to-Part Skew) combining specification information Note worst case Output-to-Output skew between multiple TS88915's connected parallel calculated. This calculation assumes that parts have common SYNC input clock with equal delay that input signal each part. This skew value valid TS88915 output pins only (equally loaded), does include trace delays varying loads. With resistor tied analog shown Note spec. limits between SYNC output (connected FEEDBACK pin) -1.05ns -0.5ns. calculate skew given output between more parts, absolute value distribution that output given Table must subtracted added lower upper spec limits respectively. output [276-(-44)] 320ps absolute value distribution. Therefore [-1.05 0.32] -1.37ns lower limit, [-0.5 0.32] -0.18ns upper limit. Therefore worst case skew output between number part [(-1.37)-(-0.18)] 1.19ns. worst case skew distribution output, 1.2ns absolute worst case Output-to-Output skew between multiple parts. Note explains that specification measured guaranteed configuration output connected FEEDBACK SYNC input running 10MHz. fixed offset (tPD) described above some dependence input frequency what frequency running. graphs Figure demonstrate this dependence. data presented Figure from devices representing process extremes, measurements were also taken voltage extremes (VCC 5.25V 4.75V). Therefore data Figure realistic representation variation tPD.
-0.50 -0.50
-0.75 SYNC FEEDBACK (ns) -1.00 SYNC FEEDBACK (ns) -1.50
-1.00
-1.25
-1.50
10.0
12.5
15.0
17.5
-2.00
12.5 17.5 22.5 27.5
SYNC INPUT FREQUENCY (MHz)
SYNC INPUT FREQUENCY (MHz)
versus Frequency output back, including process voltage variation 25°C (with resistor tied analog VCC)
versus Frequency output back, including process voltage variation 25°C (with resistor tied analog VCC)
SYNC FEEDBACK (ns) 10.0 12.5 15.0 17.5 SYNC INPUT FREQUENCY (MHz)
SYNC FEEDBACK (ns) SYNC INPUT FREQUENCY (MHz)
versus Frequency output back, including process voltage variation 25°C (with resistor tied analog GND)
versus Frequency output back, including process voltage variation 25°C (with resistor tied analog GND)
Figure
Lock indicator (LOCK) will reliably indicate phase-locked condition SYNC input frequencies down 10MHz. frequencies below 10MHz, frequency correction pulses going into phase detector from SYNC FEEDBACK pins sufficient allow lock indicator circuitry accurately predict phase-locked condition. TS88915T guaranteed provide stable phase-locked operation down appropriate minimum input frequency given Table even though LOCK frequencies below 10MHz.
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5.2. Timing notes TS88915T aligns rising edges FEEDBACK input SYNC input, therefore SYNC input does require duty cycle. skew specs measured between VCC/2 crossing point appropriate output edges. skews specified 'windows', deviation around center point. output connected FEEDBACK input (this situation shown), output frequency would match SYNC input frequency, 2X_Q output would twice SYNC frequency, output would half SYNC frequency. Figures below.
100MHz SIGNAL 25MHz FEEDBACK SIGNAL HIGH FEEDBACK CRYSTAL 25MHz INPUT OSC. EXTERNAL LOOP FILTER REF_SEL SYNC[0] ANALOG ANALOG CLOCK OUTPUTS 2X_Q
Input Output Frequency Relationship this application, output connected FEEDBACK input. internal will line positive edges SYNC, thus frequency will equal SYNC frequency. outputs (Q0-Q4, will always frequency, 2X_Q output will frequency. Allowable Input Frequency Range: (2X_Q FMAX Spec)/4 (for FREQ_SEL HIGH) (2X_Q FMAX Spec)/8 (for FREQ_SEL LOW)
FQ_SEL
PLL_EN
HIGH HIGH
Note: OE/RST input active, pull-up pull-down resistor isn't necessary FEEDBACK won't when back output goes into 3-state.
Figure Wiring diagram frequency relationship with output back
Input Output Frequency Relationship
50MHz FEEDBACK SIGNAL HIGH FEEDBACK CRYSTAL 50MHz INPUT OSC. EXTERNAL LOOP FILTER REF_SEL SYNC[0] ANALOG ANALOG CLOCK OUTPUTS 2X_Q 25MHz SIGNAL 100MHz SIGNAL
this application, output connected FEEDBACK input. internal will line positive edges SYNC, thus frequency (and rest outputs) will equal SYNC frequency. output will always frequency, 2X_Q output will frequency. Allowable Input Frequency Range: (2X_Q FMAX Spec)/2 (for FREQ_SEL HIGH) (2X_Q FMAX Spec)/4 (for FREQ_SEL LOW)
FQ_SEL
PLL_EN HIGH
HIGH
Figure Wiring diagram frequency relationship with output back
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TS88915T
Input Output Frequency Relationship
100MHz FEEDBACK SIGNAL HIGH FEEDBACK CRYSTAL 100MHz INPUT OSC. EXTERNAL LOOP FILTER REF_SEL SYNC[0] ANALOG ANALOG CLOCK OUTPUTS 2X_Q 25MHz SIGNAL
this application, 2X_Q output connected FEEDBACK input. internal will line positive edges 2X_Q SYNC, thus 2X_Q frequency will equal SYNC frequency. output will always frequency, outputs will 2X_Q frequency. Allowable Input Frequency Range: 20MHz (2X_Q FMAX Spec) (for FREQ_SEL HIGH) 10MHz (2X_Q FMAX Spec)/2 (for FREQ_SEL LOW)
FQ_SEL
PLL_EN
HIGH HIGH
Figure Wiring diagram frequency relationship with 2X_Q output back
5.3. Notes concerning Loop Filter Board Layout issues Figure shows loop filter analog isolation scheme which will effective most applications. following guidelines should followed ensure stable jitter-free operation: loop filter analog isolation components should tied close package possible. Stray current passing through parasitics long traces cause undesirable voltage transients pin. resistors, 10mF frequency bypass capacitor, 0.1mF high frequency bypass capacitor form wide bandwidth filter that will minimize 88915T's sensitivity voltage transients from system digital supply ground planes. This filter will typically ensure that 100mV step deviation digital supply will cause more than 100ps phase deviation 88915T outputs. 250mV step deviation using recommended filter values should cause more than 250ps phase deviation; 25mF bypass capacitor used (instead 1mF) 250mV step should cause more than 100ps phase deviation. good bypass techniques used board design near components which cause digital ground noise, above described step deviations should occur 88915T's digital supply. purpose bypass filtering scheme shown Figure give 88915T additional protection from power supply ground plane transients that occur high frequency, high speed digital system. There special requirements forth loop filter resistors (1MW 330W). loop filter capacitor (0.1mF) ceramic chip capacitor, same standard bypass capacitor. reference resistor injects current into internal charge pump PLL, causing fixed offset between outputs SYNC input. This also prevents excessive jitter caused inherent dead-band. (2X_Q output) running above 40MHz, resistor provides correct amount current injection into charge pump (2-3 mA). versions, running below 40MHz, 1.5MW resistor should used (instead 1MW). addition bypass capacitors used analog filter Figure there should 0.1mF bypass capacitor between each other (digital) four pins board ground plane. This will reduce output switching noise caused 88915T outputs, addition reducing potential noise 'analog' section chip. These bypass capacitors should also tied close package possible.
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TS88915T
BOARD
ANALOG
10mF FREQ BYPASS
0.1mF HIGH FREQ BYPASS
330W
ANALOG LOOP FILTER/VCO SECTION TS88915T (NOT DRAWN SCALE)
ANALOG
BOARD
SEPARATE ANALOG POWER SUPPLY NECESSARY SHOULD USED. FOLLOWING THESE PRESCRIBED GUIDELINES THAT NECESSARY TS88915T NORMAL DIGITAL ENVIRONMENT.
Figure Recommended loop filter analog isolation scheme TS88915T
CMMU TS88915T CLOCK
CMMU
CARD
CMMU
SYSTEM CLOCK SOURCE
CMMU
CMMU
CMMU TS88915T DISTRIBUTE CLOCK
CMMU
CARD
CMMU
CMMU CLOCK POINT
CMMU
TS88915T MEMORY CONTROL
MEMORY CARDS CLOCK POINT
Figure Representation potential Multi-Processing application utilizing TS88915T frequency multiplication Board-to-Board skew
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TS88915T
5.4. TS88915T System level testing functionality 3-State functionality been added TS88915T ease system board testing. Bringing OE/RST will outputs (except LOCK) into high impedance state. long PLL_EN low, Q0-Q4, outputs will remain state after OE/RST until falling SYNC edge seen. 2X_Q output will inverse SYNC signal this mode. 3-state functionality will used, pull-up pull-down resistor must tied FEEDBACK input prevent from floating when feedback output goes into high impedance. With PLL_EN selected SYNC signal gated directly into signal clock distribution network, bypassing disabling VCO. this mode outputs directly driven SYNC input (per block diagram). This mode also used frequency board testing. Note: outputs into 3-state during normal operation, loop will broken phase-lock will lost. will take maximum 10ms (tLOCK spec) regain phase-lock after OE/RST goes back high.
PREPARATION DELIVERY 6.1. Packaging
Microcircuits prepared delivery accordance with MIL-PRF-38535.
6.2. Certificate compliance
offers certificate compliances with each shipment parts, affirming products compliance either with MIL-STD-883 guarantying parameters tested temperature extremes entire temperature range.
HANDLING
devices must handled with certain precautions avoid damage accumulation static charge. Input protection devices have been designed chip minimize effect this static buildup. However, following handling practices recommended Devices should handled benches with conductive grounded surfaces. Ground test equipment, tools operator. handle devices leads. Store devices conductive foam carriers. Avoid plastic, rubber, silk areas. Maintain relative humidity above percent practical.
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PACKAGE MECHANICAL DATA
8.1. 29-pins
(TOP VIEW)
INCHES
MILLIMETERS
0.594 0.17 0.045 0.045
0.606 0.107 0.19 0.055 0.055
15.087 4.32 1.143 1.143
15.392 2.72 4.83 1.397 1.397
(BOTTOM VIEW)
0.100 0.017 0.019
2.54 0.43 0.48
8.2. 28-pins LDCC
Note
This package compatible with civil PLCC
(TOP VIEW)
(BOTTOM VIEW)
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TS88915T
ORDERING INFORMATION TS(X) 88915T
Maximum Output Frequency Prototype prefix prefix Type Screening level :Standard according MIL-STD-883 Burn-in Package LDCC
Temperature range -55, +125°C -40, +85°C +70°C
THOMSON-CSF SEMICONDUCTEURS SPECIFIQUES availability different versions, contact your sales office
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TS88915T
Information furnished believed accurate reliable. However THOMSON-CSF SEMICONDUCTEURS SPECIFIQUES assumes responsibility consequences such information infringement patents other rights third parties which result from use. license granted implication otherwise under patent patent rights THOMSON-CSF SEMICONDUCTEURS SPECIFIQUES. Specifications mentioned this publication subject change without notice. This publication supersedes replaces information previously supplied. THOMSON-CSF SEMICONDUCTEURS SPECIFIQUES products authorized critical components life support devices systems without express written approval from THOMSON-CSF SEMICONDUCTEURS SPECIFIQUES. 1999 THOMSON-CSF SEMICONDUCTEURS SPECIFIQUES Printed France rights reserved. This product manufactured THOMSON-CSF SEMICONDUCTEURS SPECIFIQUES 38521 SAINT-EGREVE FRANCE. further information please contact THOMSON-CSF SEMICONDUCTEURS SPECIFIQUES Route B.P. 91401 ORSAY Cedex FRANCE Phone (0)1 (0)1 E-mail lafrique@tcs.thomson.fr
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SKEW CMOS CLOCK DRIVER 3-State Versions TS88915T Clock Driver uti

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