SM5M2 SM5M2 CMOS 4-bit single-chip microcomputer operated single

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SM5M2 SM5M2 CMOS 4-bit single-chip microcomputer operated single

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SM5M2
SM5M2
SM5M2 CMOS 4-bit single-chip microcomputer operated single power supply. This microcomputer integrates 4-bit parallel processing function, ROM, RAM, display RAM, 15stage divider, 2-kind interrupt 4-level subroutine stack. With built-in drive circuit maximum elements, 2-mode standby function, voice synthesizer melody generator circuit single chip, SM5M2 permits design system configuration with minimum peripheral components. used variety products from handheld equipment electrical appliances, such hand held games with voice, also achieves power consumption.
4-Bit Single-Chip Microcomputer (LCD Driver)
CONNECTIONS
72-PIN VIEW
(NC) VOCS OSCOUT OSCIN VDSP
INTA (NC) VOICE
(NC) (NC)
FEATURES
capacity bits (For main program) bits (For voice) bits (For melody) capacity bits (including bits display RAM) Instruction sets Subroutine nesting levels port Input Output Input/output Interrupts Internal interrupt (divider overflow) External interrupt (INTA) Built-in voice synthesizer circuit (APCM) Number phrases Voice bits rate 25/35 kbps Number coded bits Sampling frequency Generation period 12.8 Built-in main clock oscillator system clock Built-in clock oscillator real time clock
Built-in stages divider real time clock Built-in driver segments, bias, duty cycle Built-in melody generator circuit Melody steps Generating time 32.768 kHz) (MAX.) Instruction cycle time 25.9 (MIN.) 10%) (TYP.) 32.768 kHz) When using clock with system clock. Standby function Supply voltage Package 72-pin (QFP072-P-1010)
absence confirmation device specification sheets, SHARP takes responsibility defects that occur equipment using SHARP devices shown catalogs, data books, etc. Contact SHARP order obtain latest device specification sheets before using SHARP device.
GND1 RESET VDD2 TOSC
SM5M2
BLOCK DIAGRAM
VDSP
BLEEDER
8-bit
4-bit
DISP
4-bit
OSC2 REAL TIME CLOCK OSC1 VOICE SYSTEM CLOCK
DRIVER
INTA OSCIN OSCOUT RESET
DIVIDER
INTERRUPT CONTROLLER
MELODY CONTROLLER MELODY
256-STEP
VOICE START ADDRESS
VOICE FLAG
HARDWARE RESET CIRCUIT
VOICE
k-STEP
TOSC VOSC
EXPANDER
8-bit
CONVERTER
VOICE
Nomenclature
OSCIN,OSCOUT Accumulator Arithmetic logic unit address register Carry flag Common signal generator circuit External interrupt flag Divider overflow flag Voice starting address Oscillator real time clock
P0-P2 Port registers Voice flag port Program counter Data memory Mode registers Program memory Stack register stack register register CK1,CK2 Oscillator voice system clock
SM5M2
NAME GND, VDD, VDSP, TOSC, VOSC FUNCTION Power supply pins. VDD, VDSP, pins apply positive supply with respect GND. chip test pins. Cannot used user. Connect TOSC GND. Connect VOSC VDD. Input with built-in pull-up resistor. Hardware-reset chip when RESET level signal input. Normally, capacitor connected between form power-on reset circuit. Crystal oscillator pins. Connect crystal oscillator accross [OSCIN-OSCOUT form clock generator circuit. oscillator pins. Connect resistor across [CK1-VDD form clock generator circuit. used test clock out. Voice output pin. Output contents voice ROM. Melody output pin. Outputs contents melody with standard musical scales (555 octaves. Pins LCD's common signals. Pins LCD's segment signals. Input external interrupt. flag rising edge INTA. Output ports. ports output port. accumulator transferred this port instruction. pins which switch input output pins 4/3-bit units instruction. They used output pins when configured matrix. SM5M2 forced hardware-reset when P10-P13 pins High level. mask option)
OSCIN, OSCOUT CK1, Voice H0-H3 S0-S33 INTA P00-P03
P10-P13, P20-P22
SM5M2
ABSOLUTE MAXIMUM RATINGS
PARAMETER Supply voltage Input voltage Output voltage SYMBOL TOPR TSTG RATING -0.3 -0.3 -0.3 UNIT NOTE
Source output current each
Sink output current each
Total source output current Total sink output current Operating temperature Storage temperature
NOTES
Applicable Applicable Applicable Applicable pins pins pins P00-P03 P10-P13, P20-P22 H0-H3, S0-S33
RECOMMENDED OPERATING CONDITIONS
PARAMETER Supply voltage Instruction cycle Oscillation starting voltage SYMBOL TSYS VOSC RATING Crystal+CR 25.9 31.7 Crystal 61.0 UNIT NOTE
NOTE
crystal oscillation circuit
Oscillation Circuit
Crystal oscillation (frequency 32.768 kHz)
OSCIN OSCOUT
oscillation (frequency kHz)
OSCIN OSCOUT
Crystal
Crystal 32.768
Crystal
Degree fluctuation frequency (VDD TOPR 25°C)
NOTE case using resonator, crystal also required.
NOTE Mount crystal close chip possible minimize effects stray capacitance.
SM5M2
CHARACTERISTICS
PARAMETER SYMBOL VIH1 Input voltage VIL1 VIH2 VIL2 IIH1 IIH2 IIL1 -IOH1 IOL1 -IOH2 Output current IOL2 IOP11 IOP12 ISt11 ISt12 ISt13 Supply current IOP21 IOP22 DCOM CONDITIONS MIN. -0.25 CRRUN1 CRRUN2 CRSTOP1 CRSTOP2 CRSTOP3 XTALRUN1 XTALRUN2 XTALHALT1 XTALHALT2 XTALHALT3 XTALSTOP VDD=3.0 VDD=3.0
(VDD TOPR +50°C)
TYP. MAX. 0.25 30.0 30.0 25.0 90.0 15.0 4.00 3.00 50.0 40.0 30.0 26.0 26.0
Applicable pins H0-H3 Applicable pins S0-S33
UNIT
NOTE
Input current
40.0 15.0 13.0 100.0 80.0 60.0 52.0 52.0 15.0
Output impedance
NOTES
Applicable pins P10-P13, P20-P22 Applicable pins OSCIN, RESET, INTA Applicable pins P20-P22 Applicable pins P10-P13 Applicable RESET Applicable pins P00-P03, Applicable pins P10-P13, P20-P22 Applicable pins VOICE, value external resistor Measurement conditions detail mentioned tables next page.
wave form (EXAMPLE)
SM5M2
X'TAL Standby Mode STATUS CRRUN1 CRRUN2 CRSTOP1 CRSTOP2 CRSTOP3 STOP X'TAL Voice Divider
NOTES
When OFF, Voice OFF. When Divider OFF, neither Melody operation (undefined). STOP stands executing STOP instruction.
Only X'TAL Standby Mode STATUS XTALRUN1 XTALRUN2 XTALHALT1 XTALHALT2 XTALHALT3 XTALSTOP STOP HALT X'TAL Voice Divider
NOTES
When OFF, Voice OFF. When Divider OFF, neither Melody operation (undefined). STOP stands executing STOP instruction. HALT stands executing HALT instruction.
SM5M2
SYSTEM CONFIGURATION Resister Register
register accumulator ACC) 4-bit general purpose register. register mainly used conjunction with ALU, flag transfer numerical value data perform various operations. register also used transfer data between input output pins. register auxiliary accumulator) 4-bit register used temporary register. loads contents register content transferred register. When table reference instruction used, registers load data. pair registers accommodate 8-bit data.
operates binary addition conjunction with RAM, flag register. carry signal generated carry occurs during operation. Some instructions instruction sets/clears content flag; instruction causes program skip next instruction. Note that symbol carry signal flag.
Register Register
register (BM, register 8-bit register that used specify address. upper 4-bit section called register lower 4-bit register register 8-bit register used save register register. contents register register exchanged through instruction.
register EXAX instruction
register
Fig. Data Transfer Example Between Register Register
register
register
register instruction (swap)
Arithmetic Logic Unit (ALU) Carry Signal
performs 4-bit parallel operation.
4-bit data 4-bit data
register
Fig. Register Register
Result operation
Areg
Fig.
SM5M2
Data Memory (RAM)
data memory (RAM) used data storage. capacity consists 4-bit (include 4-bit display RAM). Display RAM, which outputs data external driving segments LCD. Therefore, writing data display RAM, driven duty (1/2 bias) enable automatic display LCD. shown Fig. display connected segment outputs port from which correspond common outputs Data column display output pins drive waveform which corresponds outputs RAM, display operates exactly same other RAMs.
area surrounded thick line represents display where corresponds segment output.
Fig. Organization
SM5M2
Common outputs (Register) 1000 0000 1001 0000 1000 0001
Segment
Register 1000
drive circuit
1001 1111 1010 0000 1011 0000
(RAM bit)
Fig. Relationship between Display Segment Outputs/Common Outputs
SM5M2
Program Counter Stack Register
address specified program counter (PC). comprises 12-bit where 6bit (PU) used specify page (see Fig. 6-bit (PL) used specify step. register binary counter. table reference instruction executes similar operation that subroutine jump uses level stack register.
Program counter
Page Step
Push level level level level
Stack register
Program Memory (ROM)
used program storage. capacity SM5M2 072-step organized into 48-page where page organized into 64-step.
Fig. Program Counter Stack Register
Page 000000 000001 000010 000011 000100 000101 000110 000111 001000 001001 001010 001011 001100 001101 001110 001111
Program First page Interrupt Standby Table start release reference subroutine page
Page 010000 010001 010010 010011 010100 010101 010110 010111 011000 011001 011010 011011 011100 011101 011110 011111
Page 100000 100001 100010 100011 100100 100101 100110 100111 101000 101001 101010 101011 101100 101101 101110 101111
Last page
Fig. Organization
SM5M2
Flags
SM5M2 provides 4-flag flag interrupt request flag <IFA, IFD, P33>) which used determine conditions.
SM5M2
INTA Level interrupt controller
Output Latch Registers Mode Registers
output latch registers connected pins. instruction, contents transferred output latch registers. SM5M2 also contains mode registers Setting value each register enables voice start address, divider, LCD, melody interrupt controlled. Setting register performed same other output pins. functions mode registers shown Table INTA INTA level loaded (bit follows. LBLX INTA level does through noise debounce circuit.
Noise debounce circuit
CAUTION
Connecting considerations port When using port bidirectional such data bus, avoid setting port output when target also output. Whenever both output data conflict each other, system failure will caused damaged circuits instantaneous supply voltage drop.
SM5M2
DON'T
Data connected device
Output output
Output
SM5M2
Table Mode Register Setting REGISTER TYPE VALUE MODE DESCRIPTION Sets voice synthesizer starting address. Clears stop melody. Sets start melody from pointer address. Sets stop instruction melody code) reset instruction. Accepts divider clock-in. Masks divider clock-in. Sets voice synthesizer sampling rate. Sets voice synthesizer sampling rate. Masks interrupt based flag. Accepts interrupt based flag. Sets only. Masks interrupt based flag. Accepts interrupt based flag. setting. Turns LCD. Turns LCD. Stops function bleeder circuit. Operates function bleeder circuit. Creates system clock frequency dividing main oscillation frequency. Creates system clock frequency dividing four main oscillation frequency. Sets only.
SM5M2
System Clock Generator Dividers
main oscillation frequency oscillator) which input through divided into generate system clock fSYS (Fig. System clock fSYS determines execution instruction cycle that system clock period same instruction cycle. However, instruction execution cycle twoword instruction twice that one-word instructions.
OSCIN
oscillating element crystal oscillating element oscillator circuit determined mask option. crystal oscillator which input through "OSCIN-OSCOUT" used both real time clock display signal LCD. final stage divider, case crystal oscillation) depending mask option.
Divider
OSCOUT
OSCIN-OSCOUT Crystal oscillation (32.768 kHz)
Determined mask option
CK1-CK2 oscillation kHz)
fSYS MPX. fSYS 17.5
Fig. System Clock Generator Divider
Either system clock frequencies 17.5 case oscillation) selected flag (See Table 17.5 clock slower command execution speed, uses less power same function.
system clock initialized after hardware reset operation. Table shows relationship between contents flag resonator generated frequency, fSYS.
Table Resonator Frequency fSYS RESONATOR oscillation 32.768 crystal CONTENTS FLAG GENERATED FREQUENCY fSYS 17.5 16.384 8.192
SM5M2
FUNCTIONAL DESCRIPTION Voice Synthesizer
select voice start address There voice start address composed 8-bit select voice start address. Voice start address bits. However, register points only upper bits voice start address partial. Lower 8-bit always fixed "0". Refer register". Minimum unit (shortest block) equal voice capacity. Each minimum unit composed steps. Refer Fig.9. Core detects status whether voice synthesizer not, reading content flag. (P33 flag during voice generation.) Terminator (11111B) voice data voice ROM. When controller found terminator, immediately stops voice reset flag. When reached bottom voice data address, voice data address automatically becomes 0000H voice continuously generates until come across terminator. reset flag stop voice generation force.
NOTE
Voice data "11111" means terminator voice data. That encoder must encode voice data except "11111".
NOTE
voice start address corresponding register bits). Maximum (SM5M2) pieces voice start address selected. Each voice start address based multiple number 100H. When voice generates, flag becomes "1".
Voice start address
NOTE stands
Voice flag
Start address
Voice start address 0000H 0100H 0200H 0300H 0400H 0500H 0600H 0700H
Voice data (Voice ROM)
bits
register bits)
FF00H
register
Fig. Voice Configuration
Voice sampling frequency kHz) case sampling frequency kHz, total generation period becomes 12.8 case kHz, it's Voice sampling frequency kHz) selected register. case "0", voice sampling frequency becomes kHz. case "1", it's kHz. register register composed 8-bit. points only upper bits voice start address shown below. data filled with both registers.
First sampling rate voice synthesizer. voice synthesizer start address corresponding register bits register obtained register. After setting voice flag High, voice synthesizer would start playing. After detect Low, voice synthesizer could play next section voice.
SM5M2
Melody Output Function
built-in melody generation circuit provides variety sound signals. Fig. shows block diagram melody generating circuit. melody store notes, rest stop commands 256-step step consists 6-bit), allowing generation 12-scale over octaves (555 section time base notes (125/62.5 ms).
Melody address
8-bit preset binary counter (Melody address pointer)
(128
Melody 256-step 6-bit
Preset signal
Time base select signal
Rest tell signal
Decoder
flag
flag
Melody start/stop flag
N-stage counter
32.768
flag register flag register Fig. Melody Generating Circuit
SM5M2
CONTROL PROCEDURE binary counter designating address melody arbitrarily using instruction. performance started stopped RD0-flag "0". stop code generates "rest tell signal", same time, sets flag. melody found testing flag. Accordingly, stop performance melody, flag must clear upon detection flag Next step instruction, instruction. following example melody generating program.
MELO starting address melody 21st. Hexadecimal step. Dummy command
LBLX LBLX
Start melody Executed clear flag Dummy command
Test flag Loop detect stop code Stop melody
Using these functions, user generate music, sound effects, alarm signals, etc. desired, portion music repeated. Table lists melody output frequencies. output frequency halved making (OCT) melody (0). Table show data bits melody ROM.
Table Melody Output Frequency sol# 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 OUTPUT FREQUENCY (Hz) CLOCK NUMBER 2114.1 1985.9 1872.4 1771.2 1680.4 1560.4 1489.5 1394.4 1310.7 1236.5 1170.3 1110.8 15.5 16.5 17.5 18.5 19.5 21.0 22.0 23.5 25.0 26.5 28.0 29.5
Number clocks cycle number waveforms represents number periods oscillation frequency (32.768 kHz) from crystal oscillator duration that particular part waveform.
SM5M2
MELODY INSTRUCTION melody instruction composed 6-bit. This 6-bit instruction set), corresponding musical note, generates sound signal. EXAMPLE WRITING MELODY example writing tone such following, melody will shown.
MUSICAL SCALE TONE LENGTH (ms)
Control tone length. When "1", when "0", 62.5 When octave "1", frequency determined -m0. When octave "0", frequency determined m3-m0. Frequency shown Table Pause when stop instruction when
ADDRESS
DATA
MUSICAL NOTE INSTRUCTION pause stop
tone length initial musical note which generated from addressed data assigned instruction error maximum Therefore, applying pause initial note, melody performs with precisely regulated tone length.
SM5M2
Standby Function
standby function available which temporarily stops program execution conserve power consumption. state during which program execution called operation mode state during which execution temporarily stopped called standby mode. Either oscillator selected system clock generator circuit SM5M2. Each standby mode between only entirely different tables shown below. case X'TAL oscillator, HALT instruction used, only STOP instruction available. other hand, case only oscillator, both HALT STOP instruction available.
Table X'TAL Standby Mode Standby mode STATUS CRSTOP1 CRSTOP2 CRSTOP3 STOP HALT Register status X'TAL Chip's status Voice Divider
NOTES
When OFF, Voice OFF. When Divider OFF, neither Melody operation (undefined). STOP stands executing STOP instruction.
Table Only X'TAL Standby Mode Standby mode STATUS XTALHALT1 XTALHALT2 XTALHALT3 XTALSTOP STOP HALT Register status X'TAL Chip's status Voice Divider
NOTES
When OFF, Voice OFF. When Divider OFF, neither Melody operation (undefined). STOP stands executing STOP instruction. HALT stands executing HALT instruction.
condition mentioned first sixth boxes from right hand side, STOP HALT instruction must executed under condition mentioned fourth sixth boxes from left hand side. instance, status XTALHALT1, which contents OFF, OFF, Voice OFF, Divider only
standby mode, HALT instruction must executed under condition NOTE
halt mode stops only system clock generator circuit. This mode used activate system immediately after condition causes release operation mode.
SM5M2
During standby mode, contents stack retained. contents flags, registers output latches shown below also retained.
FLAG flag flag flag flag flag REGISTER register register register OUTPUT LATCH REGISTER register register register
release from standby mode operation mode performed reset port input, interrupt from nonmaskable INTA, port High Port divider. maskable interrupt request cannot become factor releasing back operation mode. mask setting performed with register. (see Table CAUTION
When level High, SM5M2 performed release standby mode enter normally hardware reset operation. (Mask option)
RELEASE FROM STANDBY MODE OPERATION MODE Release based interrupt request from INTA divider overflow. However, reset port High Port limited nonmaskable interrupt request. program restarts from step page However, flag set, instruction step page executed subroutine jump performed interrupt processing routine specified page according type interrupt. Even level input INTA removed before command cycles, stop mode released. However, program will jump page (interrupt process routine). Interrupt request flag program continues step page
Interrupts
Interrupts originate from INTA input divider overflow. flags become interrupt request flags. interrupt block composed mask flags (RE0, RE2), flag interrupt processing circuit. shown Fig. resetting mask flag enables interrupt request flag independently masked. Thus, mask flags used program establish interrupt priority. priority interrupts generated simultaneously shown Table
TRANSITION FROM OPERATION MODE STANDBY MODE HALT instruction executed halt mode STOP instruction executed stop mode. Since interrupt used release from standby mode, mode does transfer standby mode following conditions satisfied during execution STOP HALT instruction. INTA level High. flag set. conditions above satisfied, mode does transfer standby mode even STOP HALT instruction executed instruction address following that STOP HALT instruction executed. Therefore, place JUMP instruction which specifies step page location address following that STOP HALT instruction.
SM5M2
Stack register Program counter Mask flags Interrupt request flags
signal
Interrupt processing circuit
Interrupt enable flag
Fig. Interrupt Block Table Interrupt Event Summary INTERRUPT REQUEST (REQUEST FLAG) INTA input (IFA) Divider overflow (IFD) JUMP DESTINATION PAGE STEP PRIORITY ORDER INTERRUPT ENABLE FLAG
When flag set, interrupt circuit activates according interrupt request subroutine jump performed specified address. jump destinations according interrupt origin shown Table When flag cleared, interrupt accepted even interrupt request generated. interrupt timing shown Fig. Fig. timing chart shown Fig. shows interrupt enable state when interrupt request been generated. this case, interrupt processing signal goes High, instruction cycle after interrupt request flag set. When goes High, contents program counter pushed into stack register execution jumps specified address. this time, signal flag cleared establish interrupt disable mode. flag again when RTNI instruction executed
establish interrupt enable mode. timing chart shown Fig. shows state when interrupts enabled while multiple interrupts generated. this case, subroutine jump performed according interrupt having highest priority. When returning from subroutine executing RTNI instruction, instruction (two words executed two-word instruction) location return executed interrupt next highest priority accepted. interrupt request generated during execution two-cycle instruction, instruction executed after which interrupt processing performed. consecutive instructions skipped SKIP conditions satisfied, skip operation terminated after which interrupt processing performed.
SM5M2
Instruction cycle
System clock
Interrupt request flag
signal Interrupt enable flag
Interrupt processing routine
RTNI instruction
Interrupt processing routine
Fig. Interrupt Timing Chart
Instruction cycle
System clock Interrupt request flag
Interrupt request flag
signal
Interrupt enable flag
Interrupt processing routine
RTNI instruction
Interrupt processing routine
Fig. Interrupt Timing Chart
NOTE
Fig. Fig. show case where interrupt request flags masked.
SM5M2
Hardware Reset Function
hardware reset function mode activated instruction cycles after falling edge from RESET pin. When RESET changed from High Low, pulse which input OSCIN counted times after which reset mode clears program counter starts from address page initialized status system after reset shown Table following reset functions available. port input port mode register cleared. output only port (P0) cleared output Low. interrupt request flags (IFA, IFD) interrupt enable flag (IME) cleared interrupts become disabled. program counter start from step page activate reset function, when power turned must connect capacitor (0.1 TYP.) across RESET GND.
Table Reset Status FLAG REGISTER, X-REGISTER X-register P0-P2 output latch registers Divider flag flag flag flag flag registers Register (bit 7-0) Register (bit Register (bit Register (bit Register (bit Register (bit Register (bit Level Undefined Undefined Undefined Undefined Undefined Undefined STATUS reset mode program start)
NOTES Undefined flags registers should initialized software. When pins (P10 P13) level goes High, SM5M2 performed reset operation. (Mask option)
SM5M2
Function
Display segment SM5M2 contains built-in circuit which directly drive duty, bias LCD. sample pattern shown Fig.
Fig. Pattern
segment turned setting corresponding display (see Fig. "0". displayed segments assume configuration containing maximum segments. example 7segment numeric display shown Fig.
(1.5 (1.5
(1.5
(1.5
(1.5
Fig. Sample Pattern 7-Segment Numeric Display
drive waveforms drive waveforms pattern Fig. displaying shown Fig. (the segment output uses S1). Fig. applied pin, applied pin.
(1.5
Fig. Drive Waveforms (frame frequency
Frame frequency selectable mask option.
SM5M2
Bleeder resistors built-in drive bias. bieeder resistors have configuration shown Fig. When registor output Normally, used open state. drive with large display area, leading edge drive waveform improved connecting capacitor across VDD. same effect obtained connecting capacitor across GND. When register "0", drop level reduce power consumption. same time, H0-H3 S0-S33 level. Booster circuit necessary apply external capacitors between pin. (see Fig. Blank display There blank entire display match purpose. Blanking display short time. register Display register Blank state Blanking display long period mainy reduce supply current. register Display register Blank state When register "0", voltage (VDD) applied bleeder resistors turned common outputs segment outputs dropped level that display blanks. cutting bleeder supply, current consumption greatly reduced. However, when display blanked using method (b), response speed returning display state drops slightly. register blank state after initialization (reset state) from hardware reset.
SM5M2
Fig. Booster Circuit
SM5M2
Fig. Externally Connected Capacitor Circuit
SM5M2
INSTRUCTION Definition Symbols
following symbols used descriptions instructions. Contents address specified register Transfer direction Logical Logical Logical Push Content decremented stack register. decremented contents transferred back register register contents address within Carry (different from flag) Each register represented. example, register R(0) register represented R(0) Increment decrement denote binary addition respectively. skip certain instruction means that instruction ignored that operation performed until execution transfers next instruction. other words, instruction regarded instruction. Therefore, cycle required skip one-word instruction cycles required skip two-word instruction.
SM5M2
Instruction Summary
MNEMONIC MACHINE CODE OPERATION MNEMONIC TABL MACHINE CODE OPERATION Address Control Instructions I5-I0) I11-I6) I5-I0) Push, Push, I11-I6) I5-I0) Pop, Skip next step Pop, OUTL Test Instructions Skip Skip Skip Skip Skip Skip Skip
CALL RTNS RTNI LBMX LBLX
Manipulation Instructions
Data Transfer Instructions I3-I0) I3-I0) I3-I0) ACC, BL+1 Skip =1(BL ACC, BL+0FH
Control Instructions
EXCI
EXCD EXAX EXBM EXBL
Skip =1(BL 0FH)
Table Reference Instruction Push (X1, ACC) ACC) I7-I0
Divider Instructions f7-f0) Reset Divider
Arithmetic Instructions COMA INCB DECB ACC+x I3-I0), Skip ACC+M M+C, Skip BL+1, Skip BL-1, Skip
Melody Control Instruction Melody pointer preset Melody pointer Special Instructions Standby mode (STOP) Standby mode (HALT) operation
STOP HALT
SM5M2
SYSTEM CONFIGURATION EXAMPLE
Handheld game
Hello! DOWN
TIME START SELECT
VOSC TOSC
RESET
VOICE P10-P13 P20-P22 INTA
SHOT CHARGE
Pause Open
SM5M2
P00-P03 S0-S33 H0-H3
panel
OSCIN
OSCOUT
SM5M2
(QFP072-P-1010)
0.5TYP.
0.08
0.08 (1.0)
0.15 0.05
11.0 0.65 1.45
(1.0)
10.0 12.0
(1.0)
(1.0)
10.0 12.0
Package base plane

SM5M2 SM5M2 CMOS 4-bit single-chip microcomputer operated single

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