BLOCK DIAGRAVCC 1K/2K/4K 2.0V Microwire® Serial EEPRO Single

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BLOCK DIAGRAVCC 1K/2K/4K 2.0V Microwire® Serial EEPRO Single

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93LC46/56/66
BLOCK DIAGRAVCC
1K/2K/4K 2.0V Microwire® Serial EEPRO
Single supply with programming operation down 2.0V (Commercial only) power CMOS technology active current typical standby current (typical) 3.0V selectable memory configuration 16-bit organization (93LC46) 16-bit organization(93LC56) 16-bit organization(93LC66) Self-timed ERASE WRITE cycles (including auto-erase) Automatic ERAL before WRAL Power on/off data protection circuitry Industry standard 3-wire serial Device status signal during ERASE/WRITE cycles Sequential READ function 10,000,000 ERASE/WRITE cycles guaranteed 93LC56 93LC66 1,000,000 cycles guaranteed 93LC46 Data retention years 8-pin PDIP/SOIC 14-pin SOIC package (SOIC JEDEC EIAJ standards) Temperature ranges supported Commercial (C): +70°C Industrial (I): -40°C +85°C
MEMORY ARRAY
ADDRESS DECODER
ADDRESS COUNTER
DATA REGISTER MODE DECODE LOGIC
OUTPUT BUFFER
CLOCK GENERATOR
DESCRIPTION
Microchip Technology Inc. 93LC46/56/66 low-voltage serial Electrically Erasable PROMs. device memory configured bits, depending setup. Advanced CMOS technology makes these devices ideal low-power, nonvolatile memory applications. 93LC46/56/66 available standard 8-pin 14-pin surface mount SOIC packages. 93LC46X/ 56X/66X only offered "SN" package.
PACKAGE TYPES
SOIC
SOIC
SOIC
93LC56 93LC66
93LC46 93LC56 93LC66
93LC46 93LC56 93LC66
93LC46X 93LC56X 93LC66X
1997 Microchip Technology Inc.
DS11168L-page
93LC46/56/66
ELECTRICAL CHARACTERISTICS
Maximum Ratings*
function Table
Name
Function Chip Select Serial Data Clock Serial Data Input Serial Data Output Ground Memory Configuration Utilized Connect Power Supply
.7.0V inputs outputs w.r.t. -0.6V +1.0V Storage temperature -65°C +150°C Ambient temp. with power applied. -65°C +125°C Soldering temperature leads seconds) +300°C protection pins.4
*Notice: Stresses above those listed under "Maximum ratings" cause permanent damage device. This stress rating only functional operation device those other conditions above those indicated operational listings this specification implied. Exposure maximum rating conditions extended periods affect device reliability.
TABLE
ELECTRICAL CHARACTERISTICS
Commercial (C): +2.0V +6.0V (C): Tamb +70°C Industrial (I): +2.5V +6.0V (I): Tamb -40°C +85°C Symbol Min. Max. Units Conditions
Parameter
High level input voltage level input voltage level output voltage High level output voltage Input leakage current Output leakage current capacitance (all inputs/outputs) Operating current Standby current Clock frequency Clock high time Clock time Chip select setup time Chip select hold time Chip select time Data input setup time Data input hold time Data output delay time Data output disable time Status valid time Program cycle time Endurance 93LC46 93LC56/66
Note
VIH1 VIH2 VIL1 VIL2 VOL1 VOL2 VOH1 VOH2 CIN, COUT read write ICCS FCLK TCKH TCKL TCSS TCSH TCSL TDIS TDIH
-0.3 -0.3 Vcc-0.2
cycles
2.7V 2.7V 2.7V 2.7V 4.5V =100 Min. -400 4.5V -100 Min. 0.1V VOUT 0.1V VIN/VOUT (Notes Tamb +25°C, FCLK FCLK MHz; 6.0V FCLK MHz; 3.0V FCLK MHz; 6.0V (Note 6.0V 3.0V 4.5V 4.5V
Relative Relative Relative Relative (Note ERASE/WRITE mode (Note ERAL mode WRAL mode 25°C, 5.0V, Block Mode (Note
This parameter tested Tamb 25°C FCLK MHz. Typical program cycle time word. This parameter periodically sampled 100% tested. This application tested guaranteed characterization. endurance estimates specific application, please consult Total Endurance Model which obtained website.
DS11168L-page
1997 Microchip Technology Inc.
93LC46/56/66
DESCRIPTION
Chip Select (CS)
Data (DI)
Data (DI) used clock START bit, opcode, address, data synchronously with input.
high level selects device. level deselects device forces into standby mode. However, programming cycle which already initiated and/or progress will completed, regardless input signal. brought during program cycle, device will into standby mode soon programming cycle completed. must minimum (TCSL) between consecutive instructions. low, internal control logic held RESET status.
Data (DO)
Data (DO) used READ mode output data synchronously with input (TPD after positive edge CLK). This also provides READY/BUSY status information during ERASE WRITE cycles. READY/BUSY status information available brought high after being minimum chip select time (TCSL) ERASE WRITE operation been initiated. status signal available held high during entire WRITE ERASE cycle. other cases HIGH-Z mode. status checked after ERASE/WRITE cycle, pull-up resistor required read READY signal.
Serial Clock (CLK)
Serial Clock (CLK) used synchronize communication between master device 93LCXX. Opcodes, addresses, data bits clocked positive edge CLK. Data bits also clocked positive edge CLK. stopped anywhere transmission sequence high level) continued anytime with respect clock high time (TCKH) clock time (TCKL). This gives controlling master freedom preparing opcode, address, data. "Don't Care" (device deselected). high, START condition been detected, number clock cycles received device without changing status (i.e., waiting START condition). cycles required during self-timed WRITE (i.e., auto ERASE/WRITE) cycle. After detecting START condition, specified number clock cycles (respectively high transitions CLK) must provided. These clock cycles required clock required opcodes, addresses, data bits before instruction executed (Table Table 2-6). then become don't care inputs waiting START condition detected. Note: must between consecutive instructions.
Organization (ORG)
When tied VSS, (x8) memory organization selected. When connected floated, (x16) memory organization selected. only floated clock speeds less (X16) memory organization. clock speeds greater than MHz, must tied VSS.
1997 Microchip Technology Inc.
DS11168L-page
93LC46/56/66
TABLE
Instruction ERASE ERAL EWDS EWEN READ WRITE WRAL
INSTRUCTION 93LC46: ORGANIZATION)
Opcode Address Data Data (RDY/BSY) (RDY/BSY) HIGH-Z HIGH-Z (RDY/BSY) (RDY/BSY) Req. Cycles
TABLE
Instruction ERASE ERAL EWDS EWEN READ WRITE WRAL
INSTRUCTION 93LC46: ORGANIZATION)
Opcode Address Data Data (RDY/BSY) (RDY/BSY) HIGH-Z HIGH-Z (RDY/BSY) (RDY/BSY) Req. Cycles
TABLE
Instruction ERASE ERAL EWDS EWEN READ WRITE WRAL
INSTRUCTION 93LC56: ORGANIZATION)
Opcode Address Data Data (RDY/BSY) (RDY/BSY) HIGH-Z HIGH-Z (RDY/BSY) (RDY/BSY) Req. Cycles
TABLE
Instruction ERASE ERAL EWDS EWEN READ WRITE WRAL
INSTRUCTION 93LC56: ORGANIZATION)
Opcode Address Data Data (RDY/BSY) (RDY/BSY) HIGH-Z HIGH-Z (RDY/BSY) (RDY/BSY) Req. Cycles
TABLE
Instruction ERASE ERAL EWDS EWEN READ WRITE WRAL
INSTRUCTION 93LC66: ORGANIZATION)
Opcode Address Data Data (RDY/BSY) (RDY/BSY) HIGH-Z HIGH-Z (RDY/BSY) (RDY/BSY) Req. Cycles
TABLE
Instruction READ EWEN ERASE ERAL WRITE WRAL EWDS
INSTRUCTION 93LC66: ORGANIZATION)
Opcode Address Data Data High-Z (RDY/BSY) (RDY/BSY) (RDY/BSY) (RDY/BSY) High-Z Req. Cycles
DS11168L-page
1997 Microchip Technology Inc.
93LC46/56/66
FUNCTIONAL DESCRIPTION
Data (DI) Data (DO)
When connected ground, (x8) organization selected. When connected Vcc, (x16) organization selected. Instructions, addresses write data clocked into rising edge clock (CLK). normally held HIGH-Z state, except when reading data from device when checking READY/BUSY status during programming operation. READY/BUSY status verified during ERASE/WRITE operation polling pin; indicates that programming still progress, while high indicates device ready. will enter HIGH-Z state falling edge possible connect Data (DI) Data (DO) pins together. However, with this configuration, logic-high level, possible "bus conflict" occur during "dummy zero" that precedes READ operation. Under such condition voltage level seen undefined will depend upon relative impedances Data Out, signal source driving higher current sourcing capability higher voltage pin.
Data Protection
START Condition
START detected device both high with respect positive edge first time. Before START condition detected, CLK, change combination (except that START condition), without resulting device operation (READ, WRITE, ERASE, EWEN, EWDS, ERAL, WRAL). soon high, device longer standby mode. instruction following START condition will only executed required amount opcodes, addresses, data bits particular instruction clocked After execution instruction (i.e., clock last required address data bit) become don't care bits until START condition detected.
During power-up, programming modes operation inhibited until reached level greater than 1.4V. During power-down, source data protection circuitry acts inhibit programming modes when fallen below 1.4V nominal conditions. ERASE/WRITE Disable (EWDS) ERASE/ WRITE Enable (EWEN) commands give additional protection against accidentally programming during normal operation. After power-up, device automatically EWDS mode. Therefore, EWEN instruction must performed before ERASE WRITE instruction executed.
FIGURE 3-1:
SYNCHRONOUS DATA TIMING
TCSS TCKH TCKL TCSH
TDIS (READ) STATUS VALID TDIH
(PROGRAM)
1997 Microchip Technology Inc.
DS11168L-page
93LC46/56/66
ERASE Erase (ERAL)
ERASE instruction forces data bits specified address logical state. brought following loading last address bit. This falling edge initiates self-timed programming cycle. indicates READY/BUSY status device brought high after minimum (TCSL). logical indicates that programming still progress. logical indicates that register specified address been erased device ready another instruction. ERASE cycle takes word (Typical). Erase (ERAL) instruction will erase entire memory array logical state. ERAL cycle identical ERASE cycle except different opcode. ERAL cycle completely self-timed commences falling edge Clocking necessary after device entered self clocking mode. ERAL instruction guaranteed +4.5V +6.0V. indicates READY/BUSY status device brought high after minimum (TCSL) before entire write cycle complete. ERAL cycle takes maximum typical).
FIGURE 3-2:
ERASE TIMING
TCSL CHECK STATUS STANDBY
An-1
An-2
TRI-STATE
TRI-STATE
BUSY
READY
FIGURE 3-3:
ERAL TIMING
TCSL
CHECK STATUS
STANDBY
TRI-STATE BUSY READY
TRI-STATE
Guarantee +4.5V +6.0V.
DS11168L-page
1997 Microchip Technology Inc.
93LC46/56/66
ERASE/WRITE Disable Enable (EWEN, EWDS) READ
READ instruction outputs serial data addressed memory location pin. dummy zero precedes 8-bit organization) 16-bit (x16 organization) output string. output data bits will toggle rising edge stable after specified time delay (TPD.). Sequential read possible when held high. memory data will automatically cycle next register output sequentially.
93LC46/56/66 powers ERASE/WRITE Disable (EWDS) state. programming modes must preceded ERASE/WRITE Enable (EWEN) instruction. Once EWEN instruction executed, programming remains enabled until EWDS instruction executed removed from device. protect against accidental data disturb, EWDS instruction used disable ERASE/WRITE functions should follow programming operations. Execution READ instruction independent both EWDS EWEN instructions.
FIGURE 3-4:
EWDS TIMING
TCSL
FIGURE 3-5:
EWEN TIMING
FIGURE 3-6:
READ TIMING
TCSL
TRI-STATE® TRI-STATET
TRI-STATE registeredof National National Semiconductor Incorporated. Tri-State trademark trademark Semiconductor.
1997 Microchip Technology Inc.
DS11168L-page
93LC46/56/66
WRITE Write (WRAL)
WRITE instruction followed bits bits) data which written into specified address. After last data pin, must brought before next rising edge clock. This falling edge initiates selftimed auto-erase programming cycle. indicates READY/BUSY status device, brought high after minimum (TCSL) before entire write cycle complete. logical indicates that programming still progress. logical indicates that register specified address been written with data specified device ready another instruction. WRITE cycle takes word (Typical). Write (WRAL) instruction will write entire memory array with data specified command. WRAL cycle completely self-timed commences falling edge Clocking necessary after device entered self clocking mode. WRAL command does include automatic ERAL cycle device. Therefore, WRAL instruction does require ERAL instruction, chip must EWEN status. WRAL instruction guaranteed +4.5V +6.0V. indicates READY/BUSY status device brought high after minimum (TCSL). WRAL cycle takes maximum typical).
FIGURE 3-7:
WRITE TIMING
TCSL STANDBY
TRI-STATE
BUSY
READY
TRI_STATE
FIGURE 3-8:
WRAL TIMING
STANDBY
TRI-STATE
BUSY
READY
TRI-STATE
Guarantee +4.5V +6.0V.
DS11168L-page
1997 Microchip Technology Inc.
93LC46/56/66
NOTES:
1997 Microchip Technology Inc.
DS11168L-page
93LC46/56/66
NOTES:
DS11168L-page
1997 Microchip Technology Inc.
93LC46/56/66
93LC46/56/66 PRODUCT IDENTIFICATION SYSTETo order obtain information, e.g., pricing delivery, refer factory listed sales office. 93LC46/56/66 Plastic (300 Body), 8-lead Package: Plastic SOIC (107 Body), 14-lead Plastic SOIC (150 Body), 8-lead Plastic SOIC (207 Body), 8-lead Temperature Range: Blank +70°C -40°C +85°C 93LC46 93LC46T 93LC46X 93LC46XT 93LC56 93LC56T Device: 93LC56X 93LC56XT 93LC66 93LC66T 93LC66X 93LC66XT Microwire Serial EEPROM Microwire Serial EERPOM, Tape Reel Microwire Serial EEPROM alternate pinouts package only) Microwire Serial EEPROM alternate pinouts, Tape Reel package only) Microwire Serial EEPROM Microwire Serial EERPOM, Tape Reel Microwire Serial EEPROM alternate pinouts package only) Microwire Serial EEPROM alternate pinouts, Tape Reel package only) Microwire Serial EEPROM Microwire Serial EERPOM, Tape Reel Microwire Serial EEPROM alternate pinouts package only) Microwire Serial EEPROM alternate pinouts, Tape Reel package only)
Sales Support
Data Sheets Products supported preliminary Data Sheet have errata sheet describing minor operational differences recommended workarounds. determine errata sheet exists particular device, please contact following: Your local Microchip sales office Microchip Corporate Literature Center U.S. FAX: (602) 786-7277 Microchip's Bulletin Board, your local CompuServe number (CompuServe membership required).
1997 Microchip Technology Inc.
DS11168L-page
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rights reserved. 1997, Microchip Technology Incorporated, USA. 6/97 Printed recycled paper.
Preliminary
Information contained this publication regarding device applications like intended suggestion only superseded updates. representation warranty given liability assumed Microchip Technology Incorporated with respect accuracy such information, infringement patents other intellectual property rights arising from such otherwise. Microchip's products critical components life support systems authorized except with express written approval Microchip. licenses conveyed, implicitly otherwise, under intellectual property rights. Microchip logo name registered trademarks Microchip Technology Inc. U.S.A. other countries. rights reserved. other trademarks mentioned herein property their respective companies.
DS11168L-page
1997 Microchip Technology Inc.

BLOCK DIAGRAVCC 1K/2K/4K 2.0V Microwire® Serial EEPRO Single

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