Type 5209 (MTIA H-Bridge) Model Release Simulation Tool SABER 4.1.1 De

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Type 5209 (MTIA H-Bridge) Model Release Simulation Tool SABER 4.1.1 De

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Behavioral Model Document
Type 5209 (MTIA H-Bridge) Model Release Simulation Tool SABER 4.1.1 Description language MAST Hardware Platform Workstation (ULTRA Support: simulate@infineon.com
Infineon Technologies 04/18/2001
Introduction Functional description
2.1-Input block 2.1.a Input buffer 2.1.b Input logic 2.2-Outside world transfer block.6 2.2.a chip supply 2.2.b Static Current consumption IC.6 2.2.c Thermal network 2.3-Diagnostic functions control blocks.7 2.3.a Overtemperature detection.7 2.3.b Overcurrent detection.7 2.3.c Open load detection.8 2.3.d Undervoltage detection.9 2.3.e Diagnostic control block (Errlog) 2.4-Output blocks 2.4.a Status blocks 2.4.b High side switch.11 2.4.c side switch.11 2.5-Complete model simulation
Operating range external pins, error warning messages. Supported analyses. SABER call Appendix
Introduction
This document describes behavioral model 5209 This model allows simulation whole systems embedding 5209 GP.The model considerably reduces simulation time includes diagnostic functions such overcurrent, open load, overtemperature supply voltage detection. model valid over full operating range 5209 covers parameter variations specified data sheet such input output voltages, supply voltage temperature range. charge pump modeled. template parameters based values extracted during characterization Error Warning messages issued when input output limits results prejudiceable device life. error detected, immediatly stops simulation. user inhibit Warning messages setting variable level model been implemented Mast description language, SABER simulator, version 4.1.1. from Avant!, Inc. Most templates included model custom made, only them came from standard library.
Functional description
block diagram 5209 shown below figure 2.0.a includes four power switches (two side transistors high side transistors), input block, control block, diagnostic block allowing overtemperature, overcurrent, open load undervoltage detection, power supply block current consumption block.
Figure 2.0.a Block diagram 5209 MAST model.
2.1-Input block
input block (c.f. figure 2.1.a) converts signals, (electrical type SABER simulation) into digital signals (state logic_4 type SABER simulation) generates digital signals controling logic state H-Bridge inputs (figure 2.1.b).
Figure 2.1.a Block diagram input block
AOH1 AOH2 AUH1 AUH2 OUT1 OUT2
Figure 2.1.b Truth table input logic
2.1.a Input buffer input buffers described converters, shown figure 2.1.c. This block includes structure's resistor, pulldown current sink IinH, input
transistor gate capacitance block I_bufdig. I_bufdig converter with hysteresis, which converts analog input signal into digital signal. Figure 2.1.c Block diagram I_buf addition, this block checks input level within limits -0.3V +7V. diode protection diode overvoltage included, since their role protect against range input signal; such input signal would generate error message, thus stopping simulation. value pull-down current sinked input 45µA, internal bias voltage VCC1 (see Appendix greater equal When VCC1 smaller than pulldown current decreases until reaches zero VCC1=1V 2.1.b Input logic power switches control signals generated according truth table shown figure 2.1.b. They function input signals dDIR, dPWM error bits "off" "tmpoff". "resh" signal ensures that side transistor before high side transistor switch input signals switching time also monitored: when frequency greater than 1KHz input logic sends warning message.
2.2-Outside world transfer block
transfer block describes chip dependence over supply voltage external temperature ranges. 2.2.a chip supply supply block generates internal bias voltage VCC1 When battery voltage equal zero, value VCC1 also zero. value between 5.3V, VCC1 increases linearly when higher than 5.3V, VCC1 stays voltage VCC1 temperature dependent. This block also checks battery voltage operating range, which between 40V. When battery voltage range, error message generated simulation stops. pins electrical type pins MAST description. 2.2.b Static Current consumption This block models static current consumption 5209 current consumption temperature battery voltage dependent.
-40°C 25°C 125°C
Figure 2.2.a Measurement current consumption 2.2.c Thermal network temperature variations TLE5209 chip power losses (only power losses high side side power transistors) modeled using simple conventional description thermal conduction network, shown below:
package
solder
silicon
junction
Figure Thermal network
thermal contact between chip package represented three thermal resistance capacitance cluster series, solder, heat slug silicon respectively. power source representing total power losses chip, connected thermal network junction temperature node right end. junction temperature expresses thermal condition left end, temperature source another resistance-capacitance network describing thermal characteristics board, must connected. pins "Tp" "TGND" type thermal_c SABER simulation.
2.3-Diagnostic functions control blocks
diagnostic control block monitors temperature, supply voltage current through high side side transistors. When error detected, status flags "dst1" "dst2" (type state logic_4) case overcurrent, overtemperature undervoltage, error message back input block power transistors shut down. 2.3.a Overtemperature detection overtemperature detection, shown block 3.1., works with hysteresis. junction temperature figure compared reference temperature (175°C) overtemperature detection block generating digital signal 175°C 175°C. When chip cooling down, overtemperature signal switches back soon lower than 165°C. When higher than overtemperature detection block sends warning signal. 2.3.b Overcurrent detection When current least highside power transistor exceeds upper current limit 5.8A, signal "OCH"is When "OCH" stays high more than 17µs, switch control block sets logic level signals "dst1" "dst2" shuts down power transistors.
Figure 2.3.a Simulation results When current through power device higher than 5.8A, overcurrent signal 'OCH' High shown figure 2.3.a. 2.3.c Open load detection open load detection works with hysteresis. When current flowing through active side transistor less than 42mA logic signal "OL" When "OL" stays high longer than 5ms, "dst1" "dst2" power transistors shut down. current rises above 52mA open load error signal "OL" switches back Both current limits, 42mA 52mA temperature dependent.
Figure 2.3.b Open Load error detection side switch
simulation shown figure 2.3.b 25°C. When current greater than 6.1A "OCL" switches high signaling overcurrent. When current lower than 42mA open load signal "OL" switches high. When current over 52mA again, logic error signal "OL" switches back low. this figure, Open Load signals have their axis, with different scale). Therefore, they don't show time which current reaches limit. This time measured plot.) 2.3.d Undervoltage detection When supply voltage lower than 4.87V power transistors shut down. undervoltage limits with hysteresis between 4.87V 4.99V- temperature dependent.
Figure 2.3.c Undervoltage detection simulation undervoltage block 25°C shown figure 2.3.c. battery voltage 'VS' above 'uvht' error signal 'UVLO' 'VS' lower than 'uvlt' logic signal 'UVLO' high error message sent. 2.3.e Diagnostic control block (Errlog) error logic description block shown figure 2.3.d quite similar IC's.
Figure 2.3.d Diagnostic control block When overcurrent error detected longer than 17µs, 'dst1' 21.4us while 'dst2' until next reset signal 'res' occurs; "Off" signal switches DMOS. When undervoltage error detected, DMOS switched When overtemperature error detected logic signal 'dst1', 'dst2' 'off' contrarely overcurrent detection, `dst1' stays high until overtemperature error gone. open load error appears only when 'dpwm' high 'ol1' 'ol2' high longer than 5.3ms. 'dpwm' switches back during open load detection, counter stops after 5.3ms, error displayed 'dst1' 'dst2'. open load error does switch output DMOS.('off' stays low).
2.4-Output blocks
ST1, ST2, OUT1 OUT2 analog outputs described type electrical SABER simulation. 2.4.a Status blocks modeled switch with resistance 1.4k room temperature when digital input signal dst1 -state, switch resistance pull-up resistor external. Similarly switched when dst2 This Output internal pull-up resistor 19k. block sends error message output signals within limits -0.3V +7V. diodes implemented.
2.4.b High side switch high side switch submodel describes high side power driver. diode resistor represent drain-bulk diode DMOS. power which lost diode heats circuit causing junction temperature rise.
sollkurve
Figure 2.4.a Model high side switch DMOS modeled voltage controlled resistor, which value varies from 250m. control voltage transistor gate voltage. DMOS thermal power also cause junction temperature rise. output voltage monitored warning message sent when +0.3V above battery voltage -0.3V below Ground. cell "sollkurve" generates gate signal DMOS: varies between (DMOS off) on-resistance DMOS 250m room temperature. output signal sine wave delay between input output signals 15µs. slew-rate falling slope higher than slew rate rising slope. (Note: slew-rates silicon slew-rate model defined from 80%). 2.4.c side switch model side switch looks very similar highside `s.(figure 2.4.b). DMOS Roff resistance times lower output signal voltage monitored. block "sollkurve" works highside block includes fast turn DMOS case Short. turn time 100ns.
open
sollkurve
Figure 2.4.b Model side switch
2.5-Complete model simulation
complete model simulated over full temperature supply voltage range shown figure 2.5.a. This allows discuss thermal dependence show accuracy model versus real circuit 5209 capacitor resistor connected outputs OUT1 OUT2 better convergence model.
Figure 2.5.a Simulation circuit full model
Figure 2.5.b Simulation results with load R=68
Figure 2.5.c measurement under same conditions figure 2.5.b Figures 2.5.b show that model display similar behavior. However, during change input signal, switching delays different side switches.
Figure 2.5.d Simulation results battery voltage VS=12V, resistive load=13.5
Figure 2.5.e Measurement under same conditions figure 2.5.d rising falling edges output signals during switching have similar delay times model measurement (both 25°C) shown figures 2.5.d
Figure 2.5.f change with load R=13.5 L=1mH VS=12V
Figure 2.5.g Measurement under same conditions figure 2.5.f shown figures 2.5.f same results observed resistive- inductive load. following figures show, behavior model under different operating conditions such implementation various errors, supply voltage temperature sweeps over
full range applying various loads.
Figure 2.5.h Detection open load VS=12V temperature=25°C result open load simulation (figure 2.5.h) shows that when 'npwm' high open load error detected 2ms) error output signals 'dst1' 'dst2' show error after 5ms. output signals 'nout1' 'nout2' stay they because DMOS switches turned off. open load gone `dst2' stays same level until change 'ndir' 'npwm' occurs.
Figure 2.5.i Detection short OUT1 GND(left) (right) shown figure 2.5.i. short (right picture) signal 'short' means that short occurs. This causes error signal 'OCL1' switch high 'nout1' 'nout2' 'VS'. 'state1' 'state2' switch DMOS's switched off. After delay time 'state1' returns high when short longer exist outputs 'nout1' 'nout2' back DMOS turned off. soon reset signal 'res' (change 'npwm') occurs 'state2', 'nout1' 'nout2' switch back high.
short Ground scheme shows similar behavior (left picture).
Figure 2.5.k Detection overtemperature (with different thermal network parameter) temperature simulation shown figure 2.5.k; simulation with various thermal network parameters, increase junction temperature faster. When temperature rises above upper limit, internal error signal 'tmpoff' switches high turn DMOS switches. outputs 'nout1' 'nout2' then 'dst1' stays until overtemperature error disappears.
Figure 2.5.l Undervoltage detection Figure 2.5.l. shows undervoltage detection Supply Voltage
DMOS switches turned error signal 'dst2' follows supply voltage drop because internal pull-up.
Figure 2.5.m Temperature dependence model -40°C, 25°C 125°C. output signals temperature dependence current consumption represented Figure 2.5.m temperatures varying from -40°C 125°C.
Figure 2.5.n model simulated maximum minimum supply voltages temperatures, with resistive (picture left) resistive -inductive loads (picture right) Figures 2.5.n displays convergence model over full range supply voltage, temperature various loads. figure 2.5.o loads varies from R=2.3 with inductance inductive load varying from L=1mH 200mH. simulation shown figure 2.5.p, capacitor 100nF (_wC) both outputs parallel normal load consisting resistor 13.5 inductance 1mH.
Figure 2.5.o Convergence test with resistive loads resistive-inductive load.
Figure 2.5.p Effect large capacitor outputs H-bridge
Operating range external pins, error warning messages
following table shows operating range external pins device (figure 3.0.a) well error warning message.
name signal type OUT1 OUT2 TGND signal name -0,3 -0,3 -0,3 -0,3 100u 100u unit message error error error warning warning warning warning voltage supply voltage current supply current voltage input voltage current input current voltage input voltage current input current voltage output voltage voltage output voltage voltage output voltage voltage output voltage temperature external temperature temperature reference temperature
Figure 3.0.a Pins model their operating range Figure 3.0.b shows list error warning messages model their descriptions. parameter "warnflag" level used remove warning messages.
name limit message type error error error error warning error error warning warning warning warning warning warning warning warning warning warning suppressable supply voltage must between supply voltage must between (Vdir Vpwm) must between -0.3V (Vdir Vpwm) must between -0.3V input frequency above 1kHz (Vdir Vpwm) must between -0.3V (Vdir Vpwm) must between -0.3V input frequency above 1kHz Vout (Vst1 Vst2) must between -0.3V Vout (Vst1 Vst2) must between -0.3V Vout (Vst1 Vst2) must between -0.3V Vout (Vst1 Vst2) must between -0.3V Vout1 Vout2 lower than -0.3V Vout1 Vout2 higher than 0.3V Vout1 Vout2 lower than -0.3V Vout1 Vout2 higher than 0.3V junction temperature chip above degree message
<-1V >+40V <-0.3V >+7V freq. >1000Hz <-0.3V >+7V freq. >1000Hz <-0.3V >+7V <-0.3V >+7V OUT1 <-0.3V 0.3V OUT2 <-0.3V 0.3V >200°C
Figure 3.0.b List error warning messages error warning messages show that limit been violated. However they give quantitative indication about violation. warning messages pins OUT1 OUT2 shows normal operating conditions 5209 need worry.
description
Figure 4.0.a describes model pins.
name OUT1 OUT2 TGND type electrical electrical electrical electrical electrical electrical electrical electrical thermal_c thermal_c signal type voltage voltage voltage voltage voltage voltage voltage voltage temperature temperature signal name supply voltage supply ground input voltage input voltage output voltage output voltage output voltage output voltage external temperature reference temperature comment
added comparison added comparison
Figure 4.0.a Input output list model
Supported analyses
different analyses supported this model simulation shown below. Transient Analysis must Newton-Raphson algorithm.
Analysis type Analysis Transfer Analysis Transient Analysis AC-Analysis Noise Analysis Distortion Analysis Sensitivity Analysis Monte Carlo Analysis short TRANS NOISE DISTO SENS supported supported
Figure 5.0.a Supported analyses.
SABER call
following command used SABER call model: TLE5209.ITLE5209 DIR:DIR PWM:PWM ST1:ST1 ST2:ST2 OUT1:OUT1 OUT2:OUT2 vcc:VCC gnd:GND Tp:Tp TGND:TGND warnflag=0
Appendix
A.1.-Model model

Type 5209 (MTIA H-Bridge) Model Release Simulation Tool SABER 4.1.1 De

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