Clock jitter deviation from ideal timing clock transition events. Beca

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Clock jitter deviation from ideal timing clock transition events. Beca

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Jitter Comparison Analysis: APEX 20KE Virtex-E
Clock jitter deviation from ideal timing clock transition events. Because such deviation detrimental high-speed data transfer degrade performance, jitter must kept minimum high-speed system.
Altera Corporation Innovation Drive Jose, 95134 (408) 544-7000 http://www.altera.com https://websupport.altera.com
High-speed signaling very sensitive jitter. signals toggle faster faster, tighter restrictions fall signal transmitter receiver. many high-speed data applications, clock edge must fall within tight margin time capture data correctly. more jitter system, more often clock edge will fall outside margin. frequency clock edge deviations from acceptable margin translates system's error rate (BER). Figure shows schematic representation clock jitter. Figure Clock Jitter
Ideal clock period
Ideal clock edge location
Jitter
Altera Applications conducted multiple tests comparing jitter characteristics Altera APEX20KE device's phase-locked loops (PLLs) Xilinx Virtex-E device's delay-locked loops (DLLs). results showed that APEX 20KE introduces less intrinsic jitter into system than Virtex-E DLL. APEX 20KE also filters much random input jitter, while Virtex-E introduces more jitter into system.
Test Flow
these experiments, Altera Applications created similar programming files APEX 20KE Virtex-E devices, using multiply incoming clock signal two. tests used Altera EP20K400EBC652-1X device Xilinx XCV1000E-6-BG560 device. Table shows specifications these devices. Table Device Specifications Feature
Package Speed grade Logic elements (LEs) Core voltage Notes:
BGA: ball-grid array package. Jitter function speed grade.
EP20K400E Device
652-pin 16,640
XCV1000E Device
560-pin 24,576
Altera Corporation
M-TB-070-01.1
Jitter Comparison Analysis: APEX 20KE Virtex-E Devices
Equipment
Altera used following equipment APEX 20KE Virtex-E device tests:
LeCroy LC584AL 1-GHz scope E3614A power supply E4433B signal generator 8133A pulse generator function/arbitrary waveform generator
Test Conditions
Altera used following test conditions APEX 20KE Virtex-E device tests:
Core voltage (VCCINT) voltage (VCCIO) Temperature room temperature
Intrinsic Jitter Test
Intrinsic jitter jitter created device itself. test intrinsic jitter, Altera Applications configured APEX 20KE Virtex-E devices with PLLs DLLs mode. 50-MHz low-jitter clock applied clock input devices, output jitter measured each device's external clock output pin. "period level" feature LC584AL scope measured period input waveform over number sweeps. After voltage level selected, scope measured time between successive positive edge crossings that voltage level determine period waveform. scope recorded period every sweep calculated sigma from distribution measured periods. This sigma equivalent root mean square (RMS) period jitter waveform. this experiment, large number sweeps were taken until sigma value visually stabilized scope. measurements were done under quiet conditions.
Altera Corporation
Jitter Comparison Analysis: APEX 20KE Virtex-E Devices
Figure shows input clock jitter distribution 50-MHz clock signal. Figure period jitter waveform that driven both devices approximately Figure Input Clock Jitter Distribution MHz)
Altera Corporation
Jitter Comparison Analysis: APEX 20KE Virtex-E Devices
APEX 20KE Jitter Distribution
Figure shows output jitter distribution APEX 20KE device output when 50-MHz signal (shown Figure driven into APEX PLL. output jitter distribution APEX 20KE device sigma value with frequency average 100.005 MHz. jitter distribution curve peak centered ideal period. Using sigma value peak-to-peak jitter, maximum peak-to-peak jitter Figure APEX 20KE Output Jitter Distribution mode)
Altera Corporation
Jitter Comparison Analysis: APEX 20KE Virtex-E Devices
Virtex-E Output Jitter Distribution
Virtex-E device, measured output jitter distribution sigma value with frequency average 100.073 MHz. jitter distribution measured periods four distinct peaks, indicating that four different fundamental periods used succession achieve average period This excessive amount jitter adversely affects system performance high-speed applications. "Virtex 1.8-V Field Programmable Gate Arrays Datasheet," Xilinx claims that maximum jitter measured clock output total excluding input clock jitter. input clock jitter introduced into intrinsic jitter test very small, with sigma about seen Figure maximum jitter approximately (five divisions each). Virtex-E DLLs violated their specifications. Figure Virtex-E Output Jitter Distribution mode)
same jitter tests were repeated different frequencies. Peak-to-peak jitter calculated from jitter, using multiplication factor Figure shows output jitter both devices percentage device's output clock period, measured varying input clock frequencies from MHz. Figure reveals that Virtex-E creates over five times more jitter than APEX 20KE PLL.
Altera Corporation
Jitter Comparison Analysis: APEX 20KE Virtex-E Devices
Figure APEX 20KE Virtex-E Intrinsic Jitter Comparison
3.0% APEX 20KE Virtex-E 2.5%
2.0% jitter Output clock period
1.5%
1.0%
0.5%
0.0% Output clock frequency (MHz)
Random Jitter Transfer Test
Random jitter unpredictable deviation clock input edge. test random jitter, Altera Applications applied 128-MHz clock containing clock period random jitter clock input APEX 20KE Virtex-E devices, then measured random jitter transferred mode. create sine wave containing random jitter, Altera modulated noise signal generated E4433B signal generator onto 128-MHz carrier. This sine wave used external trigger HP8133A pulse generator, creating square wave with random jitter. square wave used input clock devices. test results showed that Virtex-E adds additional jitter, while APEX 20KE filters -7.7 jitter. Figure shows results random jitter transfer test.
Altera Corporation
Jitter Comparison Analysis: APEX 20KE Virtex-E Devices
Figure Random Jitter Transfer mode)
jitter transfer (dB) APEX 20KE Virtex-E Input clock: Input jitter:
Test Results
results intrinsic jitter test show that:
APEX 20KE PLLs introduce smallest amount jitter into system, while Virtex-E DLLs introduce more jitter frequencies. APEX 20KE jitter distribution curve peaks ideal period, while curve Virtex-E does not. APEX 20KE device tunes every period nearly ideal, whereas jitter distribution Virtex-E uses four different successive periods achieve frequency average. APEX 20KE PLLs filter input random jitter, whereas Virtex-E DLLs more jitter into system.
Conclusion
Jitter makes system more likely behave incorrectly capture incorrect data. Xilinx Virtex-E DLLs introduce much more intrinsic jitter into system than Altera APEX 20KE PLLs. addition, APEX 20KE PLLs filter random system jitter, while Virtex-E DLLs more jitter into system. Altera APEX 20KE device best solution creating low-jitter system that will meet jitter specifications, capture correct data, maintain system integrity.
Innovation Drive Jose, 95134 (408) 544-7000 http://www.altera.com
Copyright 2001 Altera Corporation. Altera, APEX, APEX 20KE, APEX logo trademarks and/or service marks Altera Corporation United States other countries. Other brands products trademarks their respective holders. specifications contained herein subject change without notice. Altera assumes responsibility liability arising application information, product, service described herein except expressly agreed writing Altera Corporation. Altera customers advised obtain latest version device specifications before relying published information before placing orders products services. rights reserved.
Altera Corporation

Clock jitter deviation from ideal timing clock transition events. Beca

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